exetrace.cc revision 2973
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Lisa Hsu 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312665Ssaidi@eecs.umich.edu * Steve Raasch 322SN/A */ 332SN/A 342SN/A#include <fstream> 352SN/A#include <iomanip> 362SN/A 372973Sgblack@eecs.umich.edu#include "arch/regfile.hh" 3856SN/A#include "base/loader/symtab.hh" 391717SN/A#include "cpu/base.hh" 402518SN/A#include "cpu/exetrace.hh" 4156SN/A#include "cpu/static_inst.hh" 422518SN/A#include "sim/param.hh" 432518SN/A#include "sim/system.hh" 442SN/A 452SN/Ausing namespace std; 462973Sgblack@eecs.umich.eduusing namespace TheISA; 472SN/A 482SN/A//////////////////////////////////////////////////////////////////////// 492SN/A// 502SN/A// Methods for the InstRecord object 512SN/A// 522SN/A 532SN/A 542SN/Avoid 552SN/ATrace::InstRecord::dump(ostream &outs) 562SN/A{ 572973Sgblack@eecs.umich.edu if (flags[PRINT_REG_DELTA]) 582973Sgblack@eecs.umich.edu { 592973Sgblack@eecs.umich.edu outs << "PC = 0x" << setbase(16) 602973Sgblack@eecs.umich.edu << setfill('0') 612973Sgblack@eecs.umich.edu << setw(16) << PC << endl; 622973Sgblack@eecs.umich.edu outs << setbase(10) 632973Sgblack@eecs.umich.edu << setfill(' ') 642973Sgblack@eecs.umich.edu << setw(0); 652973Sgblack@eecs.umich.edu /* 662973Sgblack@eecs.umich.edu int numSources = staticInst->numSrcRegs(); 672973Sgblack@eecs.umich.edu int numDests = staticInst->numDestRegs(); 682973Sgblack@eecs.umich.edu outs << "Sources:"; 692973Sgblack@eecs.umich.edu for(int x = 0; x < numSources; x++) 702973Sgblack@eecs.umich.edu { 712973Sgblack@eecs.umich.edu int sourceNum = staticInst->srcRegIdx(x); 722973Sgblack@eecs.umich.edu if(sourceNum < FP_Base_DepTag) 732973Sgblack@eecs.umich.edu outs << " " << getIntRegName(sourceNum); 742973Sgblack@eecs.umich.edu else if(sourceNum < Ctrl_Base_DepTag) 752973Sgblack@eecs.umich.edu outs << " " << getFloatRegName(sourceNum - FP_Base_DepTag); 762973Sgblack@eecs.umich.edu else 772973Sgblack@eecs.umich.edu outs << " " << getMiscRegName(sourceNum - Ctrl_Base_DepTag); 782973Sgblack@eecs.umich.edu } 792973Sgblack@eecs.umich.edu outs << endl; 802973Sgblack@eecs.umich.edu outs << "Destinations:"; 812973Sgblack@eecs.umich.edu for(int x = 0; x < numDests; x++) 822973Sgblack@eecs.umich.edu { 832973Sgblack@eecs.umich.edu int destNum = staticInst->destRegIdx(x); 842973Sgblack@eecs.umich.edu if(destNum < FP_Base_DepTag) 852973Sgblack@eecs.umich.edu outs << " " << getIntRegName(destNum); 862973Sgblack@eecs.umich.edu else if(destNum < Ctrl_Base_DepTag) 872973Sgblack@eecs.umich.edu outs << " " << getFloatRegName(destNum - FP_Base_DepTag); 882973Sgblack@eecs.umich.edu else 892973Sgblack@eecs.umich.edu outs << " " << getMiscRegName(destNum - Ctrl_Base_DepTag); 902973Sgblack@eecs.umich.edu } 912973Sgblack@eecs.umich.edu outs << endl;*/ 922973Sgblack@eecs.umich.edu } 932973Sgblack@eecs.umich.edu else if (flags[INTEL_FORMAT]) { 941968SN/A#if FULL_SYSTEM 951968SN/A bool is_trace_system = (cpu->system->name() == trace_system); 961968SN/A#else 971968SN/A bool is_trace_system = true; 981968SN/A#endif 991968SN/A if (is_trace_system) { 1001967SN/A ccprintf(outs, "%7d ) ", cycle); 1011967SN/A outs << "0x" << hex << PC << ":\t"; 1021967SN/A if (staticInst->isLoad()) { 1031967SN/A outs << "<RD 0x" << hex << addr; 1041967SN/A outs << ">"; 1051967SN/A } else if (staticInst->isStore()) { 1061967SN/A outs << "<WR 0x" << hex << addr; 1071967SN/A outs << ">"; 1081967SN/A } 1091967SN/A outs << endl; 1101904SN/A } 1111904SN/A } else { 1121904SN/A if (flags[PRINT_CYCLE]) 1131904SN/A ccprintf(outs, "%7d: ", cycle); 114452SN/A 1151904SN/A outs << cpu->name() << " "; 1162SN/A 1171904SN/A if (flags[TRACE_MISSPEC]) 1181904SN/A outs << (misspeculating ? "-" : "+") << " "; 1192SN/A 1201904SN/A if (flags[PRINT_THREAD_NUM]) 1211904SN/A outs << "T" << thread << " : "; 1222SN/A 1232SN/A 1241904SN/A std::string sym_str; 1251904SN/A Addr sym_addr; 1261904SN/A if (debugSymbolTable 1272299SN/A && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr) 1282299SN/A && flags[PC_SYMBOL]) { 1291904SN/A if (PC != sym_addr) 1301904SN/A sym_str += csprintf("+%d", PC - sym_addr); 1311904SN/A outs << "@" << sym_str << " : "; 1321904SN/A } 1331904SN/A else { 1341904SN/A outs << "0x" << hex << PC << " : "; 1351904SN/A } 136452SN/A 1371904SN/A // 1381904SN/A // Print decoded instruction 1391904SN/A // 1402SN/A 1412SN/A#if defined(__GNUC__) && (__GNUC__ < 3) 1421904SN/A // There's a bug in gcc 2.x library that prevents setw() 1431904SN/A // from working properly on strings 1441904SN/A string mc(staticInst->disassemble(PC, debugSymbolTable)); 1451904SN/A while (mc.length() < 26) 1461904SN/A mc += " "; 1471904SN/A outs << mc; 1482SN/A#else 1491904SN/A outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable); 1502SN/A#endif 1512SN/A 1521904SN/A outs << " : "; 1532SN/A 1541904SN/A if (flags[PRINT_OP_CLASS]) { 1551904SN/A outs << opClassStrings[staticInst->opClass()] << " : "; 1561904SN/A } 1571904SN/A 1581904SN/A if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) { 1591904SN/A outs << " D="; 1601904SN/A#if 0 1611904SN/A if (data_status == DataDouble) 1621904SN/A ccprintf(outs, "%f", data.as_double); 1631904SN/A else 1641904SN/A ccprintf(outs, "%#018x", data.as_int); 1651904SN/A#else 1661904SN/A ccprintf(outs, "%#018x", data.as_int); 1671904SN/A#endif 1681904SN/A } 1691904SN/A 1701904SN/A if (flags[PRINT_EFF_ADDR] && addr_valid) 1711904SN/A outs << " A=0x" << hex << addr; 1721904SN/A 1731904SN/A if (flags[PRINT_INT_REGS] && regs_valid) { 1742525SN/A for (int i = 0; i < TheISA::NumIntRegs;) 1751904SN/A for (int j = i + 1; i <= j; i++) 1762525SN/A ccprintf(outs, "r%02d = %#018x%s", i, 1772525SN/A iregs->regs.readReg(i), 1782525SN/A ((i == j) ? "\n" : " ")); 1791904SN/A outs << "\n"; 1801904SN/A } 1811904SN/A 1821904SN/A if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid) 1831904SN/A outs << " FetchSeq=" << dec << fetch_seq; 1841904SN/A 1851904SN/A if (flags[PRINT_CP_SEQ] && cp_seq_valid) 1861904SN/A outs << " CPSeq=" << dec << cp_seq; 1871967SN/A 1881967SN/A // 1891967SN/A // End of line... 1901967SN/A // 1911967SN/A outs << endl; 1922SN/A } 1932SN/A} 1942SN/A 1952SN/A 1962SN/Avector<bool> Trace::InstRecord::flags(NUM_BITS); 1971967SN/Astring Trace::InstRecord::trace_system; 1982SN/A 1992SN/A//////////////////////////////////////////////////////////////////////// 2002SN/A// 2012SN/A// Parameter space for per-cycle execution address tracing options. 2022SN/A// Derive from ParamContext so we can override checkParams() function. 2032SN/A// 2042SN/Aclass ExecutionTraceParamContext : public ParamContext 2052SN/A{ 2062SN/A public: 2072SN/A ExecutionTraceParamContext(const string &_iniSection) 2082SN/A : ParamContext(_iniSection) 2092SN/A { 2102SN/A } 2112SN/A 2122SN/A void checkParams(); // defined at bottom of file 2132SN/A}; 2142SN/A 2152SN/AExecutionTraceParamContext exeTraceParams("exetrace"); 2162SN/A 2172SN/AParam<bool> exe_trace_spec(&exeTraceParams, "speculative", 2181413SN/A "capture speculative instructions", true); 2192SN/A 2202SN/AParam<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle", 2212SN/A "print cycle number", true); 2222SN/AParam<bool> exe_trace_print_opclass(&exeTraceParams, "print_opclass", 2232SN/A "print op class", true); 2242SN/AParam<bool> exe_trace_print_thread(&exeTraceParams, "print_thread", 2252SN/A "print thread number", true); 2262SN/AParam<bool> exe_trace_print_effaddr(&exeTraceParams, "print_effaddr", 2272SN/A "print effective address", true); 2282SN/AParam<bool> exe_trace_print_data(&exeTraceParams, "print_data", 2292SN/A "print result data", true); 2302SN/AParam<bool> exe_trace_print_iregs(&exeTraceParams, "print_iregs", 2312SN/A "print all integer regs", false); 2322SN/AParam<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq", 2332SN/A "print fetch sequence number", false); 2342SN/AParam<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq", 2352SN/A "print correct-path sequence number", false); 2362973Sgblack@eecs.umich.eduParam<bool> exe_trace_print_reg_delta(&exeTraceParams, "print_reg_delta", 2372973Sgblack@eecs.umich.edu "print which registers changed to what", false); 2382299SN/AParam<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol", 2392299SN/A "Use symbols for the PC if available", true); 2401904SN/AParam<bool> exe_trace_intel_format(&exeTraceParams, "intel_format", 2411904SN/A "print trace in intel compatible format", false); 2421967SN/AParam<string> exe_trace_system(&exeTraceParams, "trace_system", 2431967SN/A "print trace of which system (client or server)", 2441967SN/A "client"); 2451904SN/A 2462SN/A 2472SN/A// 2482SN/A// Helper function for ExecutionTraceParamContext::checkParams() just 2492SN/A// to get us into the InstRecord namespace 2502SN/A// 2512SN/Avoid 2522SN/ATrace::InstRecord::setParams() 2532SN/A{ 2542SN/A flags[TRACE_MISSPEC] = exe_trace_spec; 2552SN/A 2562SN/A flags[PRINT_CYCLE] = exe_trace_print_cycle; 2572SN/A flags[PRINT_OP_CLASS] = exe_trace_print_opclass; 2582SN/A flags[PRINT_THREAD_NUM] = exe_trace_print_thread; 2592SN/A flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr; 2602SN/A flags[PRINT_EFF_ADDR] = exe_trace_print_data; 2612SN/A flags[PRINT_INT_REGS] = exe_trace_print_iregs; 2622SN/A flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq; 2632SN/A flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq; 2642973Sgblack@eecs.umich.edu flags[PRINT_REG_DELTA] = exe_trace_print_reg_delta; 2652299SN/A flags[PC_SYMBOL] = exe_trace_pc_symbol; 2661904SN/A flags[INTEL_FORMAT] = exe_trace_intel_format; 2671967SN/A trace_system = exe_trace_system; 2682SN/A} 2692SN/A 2702SN/Avoid 2712SN/AExecutionTraceParamContext::checkParams() 2722SN/A{ 2732SN/A Trace::InstRecord::setParams(); 2742SN/A} 2752SN/A 276