exetrace.cc revision 2665
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Lisa Hsu 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312665Ssaidi@eecs.umich.edu * Steve Raasch 322SN/A */ 332SN/A 342SN/A#include <fstream> 352SN/A#include <iomanip> 362SN/A 3756SN/A#include "base/loader/symtab.hh" 381717SN/A#include "cpu/base.hh" 392518SN/A#include "cpu/exetrace.hh" 4056SN/A#include "cpu/static_inst.hh" 412518SN/A#include "sim/param.hh" 422518SN/A#include "sim/system.hh" 432SN/A 442SN/Ausing namespace std; 452SN/A 462SN/A 472SN/A//////////////////////////////////////////////////////////////////////// 482SN/A// 492SN/A// Methods for the InstRecord object 502SN/A// 512SN/A 522SN/A 532SN/Avoid 542SN/ATrace::InstRecord::dump(ostream &outs) 552SN/A{ 561904SN/A if (flags[INTEL_FORMAT]) { 571968SN/A#if FULL_SYSTEM 581968SN/A bool is_trace_system = (cpu->system->name() == trace_system); 591968SN/A#else 601968SN/A bool is_trace_system = true; 611968SN/A#endif 621968SN/A if (is_trace_system) { 631967SN/A ccprintf(outs, "%7d ) ", cycle); 641967SN/A outs << "0x" << hex << PC << ":\t"; 651967SN/A if (staticInst->isLoad()) { 661967SN/A outs << "<RD 0x" << hex << addr; 671967SN/A outs << ">"; 681967SN/A } else if (staticInst->isStore()) { 691967SN/A outs << "<WR 0x" << hex << addr; 701967SN/A outs << ">"; 711967SN/A } 721967SN/A outs << endl; 731904SN/A } 741904SN/A } else { 751904SN/A if (flags[PRINT_CYCLE]) 761904SN/A ccprintf(outs, "%7d: ", cycle); 77452SN/A 781904SN/A outs << cpu->name() << " "; 792SN/A 801904SN/A if (flags[TRACE_MISSPEC]) 811904SN/A outs << (misspeculating ? "-" : "+") << " "; 822SN/A 831904SN/A if (flags[PRINT_THREAD_NUM]) 841904SN/A outs << "T" << thread << " : "; 852SN/A 862SN/A 871904SN/A std::string sym_str; 881904SN/A Addr sym_addr; 891904SN/A if (debugSymbolTable 901904SN/A && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)) { 911904SN/A if (PC != sym_addr) 921904SN/A sym_str += csprintf("+%d", PC - sym_addr); 931904SN/A outs << "@" << sym_str << " : "; 941904SN/A } 951904SN/A else { 961904SN/A outs << "0x" << hex << PC << " : "; 971904SN/A } 98452SN/A 991904SN/A // 1001904SN/A // Print decoded instruction 1011904SN/A // 1022SN/A 1032SN/A#if defined(__GNUC__) && (__GNUC__ < 3) 1041904SN/A // There's a bug in gcc 2.x library that prevents setw() 1051904SN/A // from working properly on strings 1061904SN/A string mc(staticInst->disassemble(PC, debugSymbolTable)); 1071904SN/A while (mc.length() < 26) 1081904SN/A mc += " "; 1091904SN/A outs << mc; 1102SN/A#else 1111904SN/A outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable); 1122SN/A#endif 1132SN/A 1141904SN/A outs << " : "; 1152SN/A 1161904SN/A if (flags[PRINT_OP_CLASS]) { 1171904SN/A outs << opClassStrings[staticInst->opClass()] << " : "; 1181904SN/A } 1191904SN/A 1201904SN/A if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) { 1211904SN/A outs << " D="; 1221904SN/A#if 0 1231904SN/A if (data_status == DataDouble) 1241904SN/A ccprintf(outs, "%f", data.as_double); 1251904SN/A else 1261904SN/A ccprintf(outs, "%#018x", data.as_int); 1271904SN/A#else 1281904SN/A ccprintf(outs, "%#018x", data.as_int); 1291904SN/A#endif 1301904SN/A } 1311904SN/A 1321904SN/A if (flags[PRINT_EFF_ADDR] && addr_valid) 1331904SN/A outs << " A=0x" << hex << addr; 1341904SN/A 1351904SN/A if (flags[PRINT_INT_REGS] && regs_valid) { 1362525SN/A for (int i = 0; i < TheISA::NumIntRegs;) 1371904SN/A for (int j = i + 1; i <= j; i++) 1382525SN/A ccprintf(outs, "r%02d = %#018x%s", i, 1392525SN/A iregs->regs.readReg(i), 1402525SN/A ((i == j) ? "\n" : " ")); 1411904SN/A outs << "\n"; 1421904SN/A } 1431904SN/A 1441904SN/A if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid) 1451904SN/A outs << " FetchSeq=" << dec << fetch_seq; 1461904SN/A 1471904SN/A if (flags[PRINT_CP_SEQ] && cp_seq_valid) 1481904SN/A outs << " CPSeq=" << dec << cp_seq; 1491967SN/A 1501967SN/A // 1511967SN/A // End of line... 1521967SN/A // 1531967SN/A outs << endl; 1542SN/A } 1552SN/A} 1562SN/A 1572SN/A 1582SN/Avector<bool> Trace::InstRecord::flags(NUM_BITS); 1591967SN/Astring Trace::InstRecord::trace_system; 1602SN/A 1612SN/A//////////////////////////////////////////////////////////////////////// 1622SN/A// 1632SN/A// Parameter space for per-cycle execution address tracing options. 1642SN/A// Derive from ParamContext so we can override checkParams() function. 1652SN/A// 1662SN/Aclass ExecutionTraceParamContext : public ParamContext 1672SN/A{ 1682SN/A public: 1692SN/A ExecutionTraceParamContext(const string &_iniSection) 1702SN/A : ParamContext(_iniSection) 1712SN/A { 1722SN/A } 1732SN/A 1742SN/A void checkParams(); // defined at bottom of file 1752SN/A}; 1762SN/A 1772SN/AExecutionTraceParamContext exeTraceParams("exetrace"); 1782SN/A 1792SN/AParam<bool> exe_trace_spec(&exeTraceParams, "speculative", 1801413SN/A "capture speculative instructions", true); 1812SN/A 1822SN/AParam<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle", 1832SN/A "print cycle number", true); 1842SN/AParam<bool> exe_trace_print_opclass(&exeTraceParams, "print_opclass", 1852SN/A "print op class", true); 1862SN/AParam<bool> exe_trace_print_thread(&exeTraceParams, "print_thread", 1872SN/A "print thread number", true); 1882SN/AParam<bool> exe_trace_print_effaddr(&exeTraceParams, "print_effaddr", 1892SN/A "print effective address", true); 1902SN/AParam<bool> exe_trace_print_data(&exeTraceParams, "print_data", 1912SN/A "print result data", true); 1922SN/AParam<bool> exe_trace_print_iregs(&exeTraceParams, "print_iregs", 1932SN/A "print all integer regs", false); 1942SN/AParam<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq", 1952SN/A "print fetch sequence number", false); 1962SN/AParam<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq", 1972SN/A "print correct-path sequence number", false); 1981904SN/AParam<bool> exe_trace_intel_format(&exeTraceParams, "intel_format", 1991904SN/A "print trace in intel compatible format", false); 2001967SN/AParam<string> exe_trace_system(&exeTraceParams, "trace_system", 2011967SN/A "print trace of which system (client or server)", 2021967SN/A "client"); 2031904SN/A 2042SN/A 2052SN/A// 2062SN/A// Helper function for ExecutionTraceParamContext::checkParams() just 2072SN/A// to get us into the InstRecord namespace 2082SN/A// 2092SN/Avoid 2102SN/ATrace::InstRecord::setParams() 2112SN/A{ 2122SN/A flags[TRACE_MISSPEC] = exe_trace_spec; 2132SN/A 2142SN/A flags[PRINT_CYCLE] = exe_trace_print_cycle; 2152SN/A flags[PRINT_OP_CLASS] = exe_trace_print_opclass; 2162SN/A flags[PRINT_THREAD_NUM] = exe_trace_print_thread; 2172SN/A flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr; 2182SN/A flags[PRINT_EFF_ADDR] = exe_trace_print_data; 2192SN/A flags[PRINT_INT_REGS] = exe_trace_print_iregs; 2202SN/A flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq; 2212SN/A flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq; 2221904SN/A flags[INTEL_FORMAT] = exe_trace_intel_format; 2231967SN/A trace_system = exe_trace_system; 2242SN/A} 2252SN/A 2262SN/Avoid 2272SN/AExecutionTraceParamContext::checkParams() 2282SN/A{ 2292SN/A Trace::InstRecord::setParams(); 2302SN/A} 2312SN/A 232