exetrace.cc revision 1717
15390SN/A/* 25390SN/A * Copyright (c) 2001-2004 The Regents of The University of Michigan 35390SN/A * All rights reserved. 45390SN/A * 55390SN/A * Redistribution and use in source and binary forms, with or without 65390SN/A * modification, are permitted provided that the following conditions are 75390SN/A * met: redistributions of source code must retain the above copyright 85390SN/A * notice, this list of conditions and the following disclaimer; 95390SN/A * redistributions in binary form must reproduce the above copyright 105390SN/A * notice, this list of conditions and the following disclaimer in the 115390SN/A * documentation and/or other materials provided with the distribution; 125390SN/A * neither the name of the copyright holders nor the names of its 135390SN/A * contributors may be used to endorse or promote products derived from 145390SN/A * this software without specific prior written permission. 155390SN/A * 165390SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175390SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185390SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195390SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205390SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215390SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225390SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235390SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245390SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255390SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265390SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275390SN/A */ 285390SN/A 295390SN/A#include <fstream> 305390SN/A#include <iomanip> 3113665Sandreas.sandberg@arm.com 3213665Sandreas.sandberg@arm.com#include "sim/param.hh" 3313665Sandreas.sandberg@arm.com#include "encumbered/cpu/full/dyn_inst.hh" 3413665Sandreas.sandberg@arm.com#include "encumbered/cpu/full/spec_state.hh" 3513665Sandreas.sandberg@arm.com#include "encumbered/cpu/full/issue.hh" 3613665Sandreas.sandberg@arm.com#include "cpu/exetrace.hh" 3713665Sandreas.sandberg@arm.com#include "cpu/exec_context.hh" 3813665Sandreas.sandberg@arm.com#include "base/loader/symtab.hh" 395636SN/A#include "cpu/base.hh" 405390SN/A#include "cpu/static_inst.hh" 415636SN/A 425636SN/Ausing namespace std; 435636SN/A 445636SN/A 455636SN/A//////////////////////////////////////////////////////////////////////// 465390SN/A// 479338SAndreas.Sandberg@arm.com// Methods for the InstRecord object 485636SN/A// 495636SN/A 505636SN/A 515636SN/Avoid 525636SN/ATrace::InstRecord::dump(ostream &outs) 535818Sgblack@eecs.umich.edu{ 545831Sgblack@eecs.umich.edu 555831Sgblack@eecs.umich.edu if (flags[PRINT_CYCLE]) 565636SN/A ccprintf(outs, "%7d: ", cycle); 575636SN/A 585643Sgblack@eecs.umich.edu outs << cpu->name() << " "; 595636SN/A 605636SN/A if (flags[TRACE_MISSPEC]) 615636SN/A outs << (misspeculating ? "-" : "+") << " "; 625636SN/A 635818Sgblack@eecs.umich.edu if (flags[PRINT_THREAD_NUM]) 645831Sgblack@eecs.umich.edu outs << "T" << thread << " : "; 655636SN/A 665636SN/A 675643Sgblack@eecs.umich.edu std::string sym_str; 685636SN/A Addr sym_addr; 695833Sgblack@eecs.umich.edu if (debugSymbolTable 705833Sgblack@eecs.umich.edu && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)) { 715833Sgblack@eecs.umich.edu if (PC != sym_addr) 725833Sgblack@eecs.umich.edu sym_str += csprintf("+%d", PC - sym_addr); 735833Sgblack@eecs.umich.edu outs << "@" << sym_str << " : "; 745833Sgblack@eecs.umich.edu } 755833Sgblack@eecs.umich.edu else { 765833Sgblack@eecs.umich.edu outs << "0x" << hex << PC << " : "; 775833Sgblack@eecs.umich.edu } 785833Sgblack@eecs.umich.edu 795833Sgblack@eecs.umich.edu // 805833Sgblack@eecs.umich.edu // Print decoded instruction 815833Sgblack@eecs.umich.edu // 826432Sgblack@eecs.umich.edu 836432Sgblack@eecs.umich.edu#if defined(__GNUC__) && (__GNUC__ < 3) 845843Sgblack@eecs.umich.edu // There's a bug in gcc 2.x library that prevents setw() 855843Sgblack@eecs.umich.edu // from working properly on strings 8610359SAli.Saidi@ARM.com string mc(staticInst->disassemble(PC, debugSymbolTable)); 875833Sgblack@eecs.umich.edu while (mc.length() < 26) 888929Snilay@cs.wisc.edu mc += " "; 8914290Sgabeblack@google.com outs << mc; 9014290Sgabeblack@google.com#else 9114290Sgabeblack@google.com outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable); 9214290Sgabeblack@google.com#endif 9314290Sgabeblack@google.com 9414290Sgabeblack@google.com outs << " : "; 9514290Sgabeblack@google.com 9614290Sgabeblack@google.com if (flags[PRINT_OP_CLASS]) { 975827Sgblack@eecs.umich.edu outs << opClassStrings[staticInst->opClass()] << " : "; 985827Sgblack@eecs.umich.edu } 995636SN/A 1005827Sgblack@eecs.umich.edu if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) { 1015636SN/A outs << " D="; 1028839Sandreas.hansson@arm.com#if 0 1038839Sandreas.hansson@arm.com if (data_status == DataDouble) 1048839Sandreas.hansson@arm.com ccprintf(outs, "%f", data.as_double); 1058929Snilay@cs.wisc.edu else 1068929Snilay@cs.wisc.edu ccprintf(outs, "%#018x", data.as_int); 1078839Sandreas.hansson@arm.com#else 1088839Sandreas.hansson@arm.com ccprintf(outs, "%#018x", data.as_int); 1098839Sandreas.hansson@arm.com#endif 1108839Sandreas.hansson@arm.com } 1118839Sandreas.hansson@arm.com 1128839Sandreas.hansson@arm.com if (flags[PRINT_EFF_ADDR] && addr_valid) 1138839Sandreas.hansson@arm.com outs << " A=0x" << hex << addr; 114 115 if (flags[PRINT_INT_REGS] && regs_valid) { 116 for (int i = 0; i < 32;) 117 for (int j = i + 1; i <= j; i++) 118 ccprintf(outs, "r%02d = %#018x%s", i, iregs->regs[i], 119 ((i == j) ? "\n" : " ")); 120 outs << "\n"; 121 } 122 123 if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid) 124 outs << " FetchSeq=" << dec << fetch_seq; 125 126 if (flags[PRINT_CP_SEQ] && cp_seq_valid) 127 outs << " CPSeq=" << dec << cp_seq; 128 129 // 130 // End of line... 131 // 132 outs << endl; 133} 134 135 136vector<bool> Trace::InstRecord::flags(NUM_BITS); 137 138//////////////////////////////////////////////////////////////////////// 139// 140// Parameter space for per-cycle execution address tracing options. 141// Derive from ParamContext so we can override checkParams() function. 142// 143class ExecutionTraceParamContext : public ParamContext 144{ 145 public: 146 ExecutionTraceParamContext(const string &_iniSection) 147 : ParamContext(_iniSection) 148 { 149 } 150 151 void checkParams(); // defined at bottom of file 152}; 153 154ExecutionTraceParamContext exeTraceParams("exetrace"); 155 156Param<bool> exe_trace_spec(&exeTraceParams, "speculative", 157 "capture speculative instructions", true); 158 159Param<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle", 160 "print cycle number", true); 161Param<bool> exe_trace_print_opclass(&exeTraceParams, "print_opclass", 162 "print op class", true); 163Param<bool> exe_trace_print_thread(&exeTraceParams, "print_thread", 164 "print thread number", true); 165Param<bool> exe_trace_print_effaddr(&exeTraceParams, "print_effaddr", 166 "print effective address", true); 167Param<bool> exe_trace_print_data(&exeTraceParams, "print_data", 168 "print result data", true); 169Param<bool> exe_trace_print_iregs(&exeTraceParams, "print_iregs", 170 "print all integer regs", false); 171Param<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq", 172 "print fetch sequence number", false); 173Param<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq", 174 "print correct-path sequence number", false); 175 176// 177// Helper function for ExecutionTraceParamContext::checkParams() just 178// to get us into the InstRecord namespace 179// 180void 181Trace::InstRecord::setParams() 182{ 183 flags[TRACE_MISSPEC] = exe_trace_spec; 184 185 flags[PRINT_CYCLE] = exe_trace_print_cycle; 186 flags[PRINT_OP_CLASS] = exe_trace_print_opclass; 187 flags[PRINT_THREAD_NUM] = exe_trace_print_thread; 188 flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr; 189 flags[PRINT_EFF_ADDR] = exe_trace_print_data; 190 flags[PRINT_INT_REGS] = exe_trace_print_iregs; 191 flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq; 192 flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq; 193} 194 195void 196ExecutionTraceParamContext::checkParams() 197{ 198 Trace::InstRecord::setParams(); 199} 200 201