exec_context.hh revision 8443:530ff1bc8d70
14776Sgblack@eecs.umich.edu/* 26365Sgblack@eecs.umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 34776Sgblack@eecs.umich.edu * All rights reserved. 44776Sgblack@eecs.umich.edu * 54776Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 64776Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 74776Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 84776Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 94776Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 104776Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 114776Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 124776Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 134776Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 144776Sgblack@eecs.umich.edu * this software without specific prior written permission. 154776Sgblack@eecs.umich.edu * 164776Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174776Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184776Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194776Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204776Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214776Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224776Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234776Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244776Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254776Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264776Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274776Sgblack@eecs.umich.edu * 286365Sgblack@eecs.umich.edu * Authors: Kevin Lim 294776Sgblack@eecs.umich.edu */ 304776Sgblack@eecs.umich.edu 3111793Sbrandon.potter@amd.com#error "Cannot include this file" 3211793Sbrandon.potter@amd.com 334776Sgblack@eecs.umich.edu/** 344776Sgblack@eecs.umich.edu * The ExecContext is not a usable class. It is simply here for 358232Snate@binkert.org * documentation purposes. It shows the interface that is used by the 364776Sgblack@eecs.umich.edu * ISA to access and change CPU state. 374776Sgblack@eecs.umich.edu */ 384776Sgblack@eecs.umich.educlass ExecContext { 394776Sgblack@eecs.umich.edu // The register accessor methods provide the index of the 404776Sgblack@eecs.umich.edu // instruction's operand (e.g., 0 or 1), not the architectural 414776Sgblack@eecs.umich.edu // register index, to simplify the implementation of register 425523Snate@binkert.org // renaming. We find the architectural register index by indexing 436409Sgblack@eecs.umich.edu // into the instruction's own operand index table. Note that a 444776Sgblack@eecs.umich.edu // raw pointer to the StaticInst is provided instead of a 455523Snate@binkert.org // ref-counted StaticInstPtr to reduce overhead. This is fine as 465523Snate@binkert.org // long as these methods don't copy the pointer into any long-term 475523Snate@binkert.org // storage (which is pretty hard to imagine they would have reason 484776Sgblack@eecs.umich.edu // to do). 4911321Ssteve.reinhardt@amd.com 504776Sgblack@eecs.umich.edu /** Reads an integer register. */ 514776Sgblack@eecs.umich.edu uint64_t readIntRegOperand(const StaticInst *si, int idx); 524776Sgblack@eecs.umich.edu 534776Sgblack@eecs.umich.edu /** Reads a floating point register of single register width. */ 544776Sgblack@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx); 554776Sgblack@eecs.umich.edu 565049Sgblack@eecs.umich.edu /** Reads a floating point register in its binary format, instead 575049Sgblack@eecs.umich.edu * of by value. */ 584776Sgblack@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx); 594776Sgblack@eecs.umich.edu 604776Sgblack@eecs.umich.edu /** Sets an integer register to a value. */ 614776Sgblack@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val); 624776Sgblack@eecs.umich.edu 636365Sgblack@eecs.umich.edu /** Sets a floating point register of single width to a value. */ 646365Sgblack@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val); 654830Sgblack@eecs.umich.edu 664830Sgblack@eecs.umich.edu /** Sets the bits of a floating point register of single width 677811Ssteve.reinhardt@amd.com * to a binary value. */ 68 void setFloatRegOperandBits(const StaticInst *si, int idx, 69 FloatRegBits val); 70 71 /** Reads the PC. */ 72 uint64_t readPC(); 73 /** Reads the NextPC. */ 74 uint64_t readNextPC(); 75 /** Reads the Next-NextPC. Only for architectures like SPARC or MIPS. */ 76 uint64_t readNextNPC(); 77 78 /** Sets the PC. */ 79 void setPC(uint64_t val); 80 /** Sets the NextPC. */ 81 void setNextPC(uint64_t val); 82 /** Sets the Next-NextPC. Only for architectures like SPARC or MIPS. */ 83 void setNextNPC(uint64_t val); 84 85 /** Reads a miscellaneous register. */ 86 MiscReg readMiscRegNoEffect(int misc_reg); 87 88 /** Reads a miscellaneous register, handling any architectural 89 * side effects due to reading that register. */ 90 MiscReg readMiscReg(int misc_reg); 91 92 /** Sets a miscellaneous register. */ 93 void setMiscRegNoEffect(int misc_reg, const MiscReg &val); 94 95 /** Sets a miscellaneous register, handling any architectural 96 * side effects due to writing that register. */ 97 void setMiscReg(int misc_reg, const MiscReg &val); 98 99 /** Records the effective address of the instruction. Only valid 100 * for memory ops. */ 101 void setEA(Addr EA); 102 /** Returns the effective address of the instruction. Only valid 103 * for memory ops. */ 104 Addr getEA(); 105 106 /** Returns a pointer to the ThreadContext. */ 107 ThreadContext *tcBase(); 108 109 Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags); 110 111 Fault writeBytes(uint8_t *data, unsigned size, 112 Addr addr, unsigned flags, uint64_t *res); 113 114#if FULL_SYSTEM 115 /** Somewhat Alpha-specific function that handles returning from 116 * an error or interrupt. */ 117 Fault hwrei(); 118 119 /** 120 * Check for special simulator handling of specific PAL calls. If 121 * return value is false, actual PAL call will be suppressed. 122 */ 123 bool simPalCheck(int palFunc); 124#else 125 /** Executes a syscall specified by the callnum. */ 126 void syscall(int64_t callnum); 127#endif 128 129 /** Finish a DTB address translation. */ 130 void finishTranslation(WholeTranslationState *state); 131}; 132