exec_context.hh revision 3735
13536SN/A/* 211274Sshingarov@labware.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 310595Sgabeblack@google.com * All rights reserved. 412109SRekai.GonzalezAlberquilla@arm.com * 57752SWilliam.Wang@arm.com * Redistribution and use in source and binary forms, with or without 67752SWilliam.Wang@arm.com * modification, are permitted provided that the following conditions are 77752SWilliam.Wang@arm.com * met: redistributions of source code must retain the above copyright 87752SWilliam.Wang@arm.com * notice, this list of conditions and the following disclaimer; 97752SWilliam.Wang@arm.com * redistributions in binary form must reproduce the above copyright 107752SWilliam.Wang@arm.com * notice, this list of conditions and the following disclaimer in the 117752SWilliam.Wang@arm.com * documentation and/or other materials provided with the distribution; 127752SWilliam.Wang@arm.com * neither the name of the copyright holders nor the names of its 137752SWilliam.Wang@arm.com * contributors may be used to endorse or promote products derived from 147752SWilliam.Wang@arm.com * this software without specific prior written permission. 157752SWilliam.Wang@arm.com * 163536SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173536SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183536SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193536SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203536SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213536SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223536SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233536SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243536SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253536SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263536SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273536SN/A * 283536SN/A * Authors: Kevin Lim 293536SN/A */ 303536SN/A 313536SN/A#error "Cannot include this file" 323536SN/A 333536SN/A/** 343536SN/A * The ExecContext is not a usable class. It is simply here for 353536SN/A * documentation purposes. It shows the interface that is used by the 363536SN/A * ISA to access and change CPU state. 373536SN/A */ 383536SN/Aclass ExecContext { 393536SN/A // The register accessor methods provide the index of the 403536SN/A // instruction's operand (e.g., 0 or 1), not the architectural 413536SN/A // register index, to simplify the implementation of register 423536SN/A // renaming. We find the architectural register index by indexing 437752SWilliam.Wang@arm.com // into the instruction's own operand index table. Note that a 4411274Sshingarov@labware.com // raw pointer to the StaticInst is provided instead of a 453536SN/A // ref-counted StaticInstPtr to reduce overhead. This is fine as 463536SN/A // long as these methods don't copy the pointer into any long-term 473536SN/A // storage (which is pretty hard to imagine they would have reason 488332Snate@binkert.org // to do). 498332Snate@binkert.org 503536SN/A /** Reads an integer register. */ 513536SN/A uint64_t readIntRegOperand(const StaticInst *si, int idx); 523536SN/A 533536SN/A /** Reads a floating point register of a specific width. */ 543536SN/A FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width); 553536SN/A 563536SN/A /** Reads a floating point register of single register width. */ 575543SN/A FloatReg readFloatRegOperand(const StaticInst *si, int idx); 585543SN/A 593536SN/A /** Reads a floating point register of a specific width in its 603536SN/A * binary format, instead of by value. */ 613536SN/A FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, 623536SN/A int width); 633536SN/A 643536SN/A /** Reads a floating point register in its binary format, instead 653536SN/A * of by value. */ 663536SN/A FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx); 673536SN/A 683536SN/A /** Sets an integer register to a value. */ 693536SN/A void setIntRegOperand(const StaticInst *si, int idx, uint64_t val); 705543SN/A 715543SN/A /** Sets a floating point register of a specific width to a value. */ 723536SN/A void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 733536SN/A int width); 743536SN/A 753536SN/A /** Sets a floating point register of single width to a value. */ 763536SN/A void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val); 773536SN/A 783536SN/A /** Sets the bits of a floating point register of a specific width 793536SN/A * to a binary value. */ 803536SN/A void setFloatRegOperandBits(const StaticInst *si, int idx, 813536SN/A FloatRegBits val, int width); 823536SN/A 833536SN/A /** Sets the bits of a floating point register of single width 843536SN/A * to a binary value. */ 853536SN/A void setFloatRegOperandBits(const StaticInst *si, int idx, 863536SN/A FloatRegBits val); 873536SN/A 885543SN/A /** Reads the PC. */ 893536SN/A uint64_t readPC(); 903536SN/A /** Reads the NextPC. */ 913536SN/A uint64_t readNextPC(); 923536SN/A /** Reads the Next-NextPC. Only for architectures like SPARC or MIPS. */ 933536SN/A uint64_t readNextNPC(); 943536SN/A 953536SN/A /** Sets the PC. */ 963536SN/A void setPC(uint64_t val); 973536SN/A /** Sets the NextPC. */ 983536SN/A void setNextPC(uint64_t val); 993536SN/A /** Sets the Next-NextPC. Only for architectures like SPARC or MIPS. */ 1003536SN/A void setNextNPC(uint64_t val); 1013536SN/A 1023536SN/A /** Reads a miscellaneous register. */ 1033536SN/A MiscReg readMiscReg(int misc_reg); 1043536SN/A 1053536SN/A /** Reads a miscellaneous register, handling any architectural 1063536SN/A * side effects due to reading that register. */ 1073536SN/A MiscReg readMiscRegWithEffect(int misc_reg); 1085543SN/A 1095543SN/A /** Sets a miscellaneous register. */ 1103536SN/A void setMiscReg(int misc_reg, const MiscReg &val); 1113536SN/A 1123536SN/A /** Sets a miscellaneous register, handling any architectural 1133536SN/A * side effects due to writing that register. */ 1143536SN/A void setMiscRegWithEffect(int misc_reg, const MiscReg &val); 1153536SN/A 1163536SN/A /** Records the effective address of the instruction. Only valid 1173536SN/A * for memory ops. */ 1183536SN/A void setEA(Addr EA); 1193536SN/A /** Returns the effective address of the instruction. Only valid 1203536SN/A * for memory ops. */ 1213536SN/A Addr getEA(); 1223536SN/A 1233536SN/A /** Returns a pointer to the ThreadContext. */ 1243536SN/A ThreadContext *tcBase(); 1253536SN/A 1263536SN/A /** Reads an address, creating a memory request with the given 1273536SN/A * flags. Stores result of read in data. */ 1283536SN/A template <class T> 1293536SN/A Fault read(Addr addr, T &data, unsigned flags); 1303536SN/A 1313536SN/A /** Writes to an address, creating a memory request with the given 1323536SN/A * flags. Writes data to memory. For store conditionals, returns 1333536SN/A * the result of the store in res. */ 1343536SN/A template <class T> 13511793Sbrandon.potter@amd.com Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 13611793Sbrandon.potter@amd.com 1373536SN/A /** Prefetches an address, creating a memory request with the 1385569SN/A * given flags. */ 1393536SN/A void prefetch(Addr addr, unsigned flags); 1403536SN/A 1413536SN/A /** Hints to the memory system that an address will be written to 1429020Sgblack@eecs.umich.edu * soon, with the given size. Creates a memory request with the 1438229Snate@binkert.org * given flags. */ 1448229Snate@binkert.org void writeHint(Addr addr, int size, unsigned flags); 14510037SARM gem5 Developers 1467752SWilliam.Wang@arm.com#if FULL_SYSTEM 1477752SWilliam.Wang@arm.com /** Somewhat Alpha-specific function that handles returning from 14810707SAndreas.Sandberg@ARM.com * an error or interrupt. */ 1493536SN/A Fault hwrei(); 1503536SN/A 1513536SN/A /** 1523536SN/A * Check for special simulator handling of specific PAL calls. If 1538229Snate@binkert.org * return value is false, actual PAL call will be suppressed. 1543536SN/A */ 1557752SWilliam.Wang@arm.com bool simPalCheck(int palFunc); 1568232Snate@binkert.org#else 1578232Snate@binkert.org /** Executes a syscall specified by the callnum. */ 1588229Snate@binkert.org void syscall(int64_t callnum); 1593536SN/A#endif 1603536SN/A}; 1618782Sgblack@eecs.umich.edu