exec_context.hh revision 13500:6e0a2a7c6d8c 
1/*
2 * Copyright (c) 2014, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2015 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Andreas Sandberg
43 */
44
45#ifndef __CPU_EXEC_CONTEXT_HH__
46#define __CPU_EXEC_CONTEXT_HH__
47
48#include "arch/registers.hh"
49#include "base/types.hh"
50#include "config/the_isa.hh"
51#include "cpu/base.hh"
52#include "cpu/reg_class.hh"
53#include "cpu/static_inst_fwd.hh"
54#include "cpu/translation.hh"
55#include "mem/request.hh"
56
57/**
58 * The ExecContext is an abstract base class the provides the
59 * interface used by the ISA to manipulate the state of the CPU model.
60 *
61 * Register accessor methods in this class typically provide the index
62 * of the instruction's operand (e.g., 0 or 1), not the architectural
63 * register index, to simplify the implementation of register
64 * renaming.  The architectural register index can be found by
65 * indexing into the instruction's own operand index table.
66 *
67 * @note The methods in this class typically take a raw pointer to the
68 * StaticInst is provided instead of a ref-counted StaticInstPtr to
69 * reduce overhead as an argument. This is fine as long as the
70 * implementation doesn't copy the pointer into any long-term storage
71 * (which is pretty hard to imagine they would have reason to do).
72 */
73class ExecContext {
74  public:
75    typedef TheISA::IntReg IntReg;
76    typedef TheISA::PCState PCState;
77    typedef TheISA::FloatReg FloatReg;
78    typedef TheISA::FloatRegBits FloatRegBits;
79    typedef TheISA::MiscReg MiscReg;
80
81    typedef TheISA::CCReg CCReg;
82    using VecRegContainer = TheISA::VecRegContainer;
83    using VecElem = TheISA::VecElem;
84
85  public:
86    /**
87     * @{
88     * @name Integer Register Interfaces
89     *
90     */
91
92    /** Reads an integer register. */
93    virtual IntReg readIntRegOperand(const StaticInst *si, int idx) = 0;
94
95    /** Sets an integer register to a value. */
96    virtual void setIntRegOperand(const StaticInst *si,
97                                  int idx, IntReg val) = 0;
98
99    /** @} */
100
101
102    /**
103     * @{
104     * @name Floating Point Register Interfaces
105     */
106
107    /** Reads a floating point register in its binary format, instead
108     * of by value. */
109    virtual FloatRegBits readFloatRegOperandBits(const StaticInst *si,
110                                                 int idx) = 0;
111
112    /** Sets the bits of a floating point register of single width
113     * to a binary value. */
114    virtual void setFloatRegOperandBits(const StaticInst *si,
115                                        int idx, FloatRegBits val) = 0;
116
117    /** @} */
118
119    /** Vector Register Interfaces. */
120    /** @{ */
121    /** Reads source vector register operand. */
122    virtual const VecRegContainer&
123    readVecRegOperand(const StaticInst *si, int idx) const = 0;
124
125    /** Gets destination vector register operand for modification. */
126    virtual VecRegContainer&
127    getWritableVecRegOperand(const StaticInst *si, int idx) = 0;
128
129    /** Sets a destination vector register operand to a value. */
130    virtual void
131    setVecRegOperand(const StaticInst *si, int idx,
132                     const VecRegContainer& val) = 0;
133    /** @} */
134
135    /** Vector Register Lane Interfaces. */
136    /** @{ */
137    /** Reads source vector 8bit operand. */
138    virtual ConstVecLane8
139    readVec8BitLaneOperand(const StaticInst *si, int idx) const = 0;
140
141    /** Reads source vector 16bit operand. */
142    virtual ConstVecLane16
143    readVec16BitLaneOperand(const StaticInst *si, int idx) const = 0;
144
145    /** Reads source vector 32bit operand. */
146    virtual ConstVecLane32
147    readVec32BitLaneOperand(const StaticInst *si, int idx) const = 0;
148
149    /** Reads source vector 64bit operand. */
150    virtual ConstVecLane64
151    readVec64BitLaneOperand(const StaticInst *si, int idx) const = 0;
152
153    /** Write a lane of the destination vector operand. */
154    /** @{ */
155    virtual void setVecLaneOperand(const StaticInst *si, int idx,
156            const LaneData<LaneSize::Byte>& val) = 0;
157    virtual void setVecLaneOperand(const StaticInst *si, int idx,
158            const LaneData<LaneSize::TwoByte>& val) = 0;
159    virtual void setVecLaneOperand(const StaticInst *si, int idx,
160            const LaneData<LaneSize::FourByte>& val) = 0;
161    virtual void setVecLaneOperand(const StaticInst *si, int idx,
162            const LaneData<LaneSize::EightByte>& val) = 0;
163    /** @} */
164
165    /** Vector Elem Interfaces. */
166    /** @{ */
167    /** Reads an element of a vector register. */
168    virtual VecElem readVecElemOperand(const StaticInst *si,
169                                        int idx) const = 0;
170
171    /** Sets a vector register to a value. */
172    virtual void setVecElemOperand(const StaticInst *si, int idx,
173                                   const VecElem val) = 0;
174    /** @} */
175
176    /**
177     * @{
178     * @name Condition Code Registers
179     */
180    virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0;
181    virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0;
182    /** @} */
183
184    /**
185     * @{
186     * @name Misc Register Interfaces
187     */
188    virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0;
189    virtual void setMiscRegOperand(const StaticInst *si,
190                                   int idx, const MiscReg &val) = 0;
191
192    /**
193     * Reads a miscellaneous register, handling any architectural
194     * side effects due to reading that register.
195     */
196    virtual MiscReg readMiscReg(int misc_reg) = 0;
197
198    /**
199     * Sets a miscellaneous register, handling any architectural
200     * side effects due to writing that register.
201     */
202    virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
203
204    /** @} */
205
206    /**
207     * @{
208     * @name PC Control
209     */
210    virtual PCState pcState() const = 0;
211    virtual void pcState(const PCState &val) = 0;
212    /** @} */
213
214    /**
215     * @{
216     * @name Memory Interface
217     */
218    /**
219     * Perform an atomic memory read operation.  Must be overridden
220     * for exec contexts that support atomic memory mode.  Not pure
221     * virtual since exec contexts that only support timing memory
222     * mode need not override (though in that case this function
223     * should never be called).
224     */
225    virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size,
226                          Request::Flags flags)
227    {
228        panic("ExecContext::readMem() should be overridden\n");
229    }
230
231    /**
232     * Initiate a timing memory read operation.  Must be overridden
233     * for exec contexts that support timing memory mode.  Not pure
234     * virtual since exec contexts that only support atomic memory
235     * mode need not override (though in that case this function
236     * should never be called).
237     */
238    virtual Fault initiateMemRead(Addr addr, unsigned int size,
239                                  Request::Flags flags)
240    {
241        panic("ExecContext::initiateMemRead() should be overridden\n");
242    }
243
244    /**
245     * For atomic-mode contexts, perform an atomic memory write operation.
246     * For timing-mode contexts, initiate a timing memory write operation.
247     */
248    virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
249                           Request::Flags flags, uint64_t *res) = 0;
250
251    /**
252     * Sets the number of consecutive store conditional failures.
253     */
254    virtual void setStCondFailures(unsigned int sc_failures) = 0;
255
256    /**
257     * Returns the number of consecutive store conditional failures.
258     */
259    virtual unsigned int readStCondFailures() const = 0;
260
261    /** @} */
262
263    /**
264     * @{
265     * @name SysCall Emulation Interfaces
266     */
267
268    /**
269     * Executes a syscall specified by the callnum.
270     */
271    virtual void syscall(int64_t callnum, Fault *fault) = 0;
272
273    /** @} */
274
275    /** Returns a pointer to the ThreadContext. */
276    virtual ThreadContext *tcBase() = 0;
277
278    /**
279     * @{
280     * @name Alpha-Specific Interfaces
281     */
282
283    /**
284     * Somewhat Alpha-specific function that handles returning from an
285     * error or interrupt.
286     */
287    virtual Fault hwrei() = 0;
288
289    /**
290     * Check for special simulator handling of specific PAL calls.  If
291     * return value is false, actual PAL call will be suppressed.
292     */
293    virtual bool simPalCheck(int palFunc) = 0;
294
295    /** @} */
296
297    /**
298     * @{
299     * @name ARM-Specific Interfaces
300     */
301
302    virtual bool readPredicate() const = 0;
303    virtual void setPredicate(bool val) = 0;
304
305    /** @} */
306
307    /**
308     * @{
309     * @name X86-Specific Interfaces
310     */
311
312    /**
313     * Invalidate a page in the DTLB <i>and</i> ITLB.
314     */
315    virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
316    virtual void armMonitor(Addr address) = 0;
317    virtual bool mwait(PacketPtr pkt) = 0;
318    virtual void mwaitAtomic(ThreadContext *tc) = 0;
319    virtual AddressMonitor *getAddrMonitor() = 0;
320
321    /** @} */
322
323    /**
324     * @{
325     * @name MIPS-Specific Interfaces
326     */
327
328#if THE_ISA == MIPS_ISA
329    virtual MiscReg readRegOtherThread(const RegId& reg,
330                                       ThreadID tid = InvalidThreadID) = 0;
331    virtual void setRegOtherThread(const RegId& reg, MiscReg val,
332                                   ThreadID tid = InvalidThreadID) = 0;
333#endif
334
335    /** @} */
336};
337
338#endif // __CPU_EXEC_CONTEXT_HH__
339