exec_context.hh revision 8444
12329SN/A/* 22329SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32329SN/A * All rights reserved. 42329SN/A * 52329SN/A * Redistribution and use in source and binary forms, with or without 62329SN/A * modification, are permitted provided that the following conditions are 72329SN/A * met: redistributions of source code must retain the above copyright 82329SN/A * notice, this list of conditions and the following disclaimer; 92329SN/A * redistributions in binary form must reproduce the above copyright 102329SN/A * notice, this list of conditions and the following disclaimer in the 112329SN/A * documentation and/or other materials provided with the distribution; 122329SN/A * neither the name of the copyright holders nor the names of its 132329SN/A * contributors may be used to endorse or promote products derived from 142329SN/A * this software without specific prior written permission. 152329SN/A * 162329SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172329SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182329SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192329SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202329SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212329SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222329SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232329SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242329SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252329SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262329SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292329SN/A */ 302292SN/A 312292SN/A#error "Cannot include this file" 322292SN/A 332292SN/A/** 342362SN/A * The ExecContext is not a usable class. It is simply here for 352362SN/A * documentation purposes. It shows the interface that is used by the 362680Sktlim@umich.edu * ISA to access and change CPU state. 372292SN/A */ 382362SN/Aclass ExecContext { 392292SN/A // The register accessor methods provide the index of the 402292SN/A // instruction's operand (e.g., 0 or 1), not the architectural 412292SN/A // register index, to simplify the implementation of register 422292SN/A // renaming. We find the architectural register index by indexing 432292SN/A // into the instruction's own operand index table. Note that a 442292SN/A // raw pointer to the StaticInst is provided instead of a 452292SN/A // ref-counted StaticInstPtr to reduce overhead. This is fine as 462292SN/A // long as these methods don't copy the pointer into any long-term 472292SN/A // storage (which is pretty hard to imagine they would have reason 482329SN/A // to do). 492292SN/A 502292SN/A /** Reads an integer register. */ 512292SN/A uint64_t readIntRegOperand(const StaticInst *si, int idx); 522329SN/A 532329SN/A /** Reads a floating point register of single register width. */ 542329SN/A FloatReg readFloatRegOperand(const StaticInst *si, int idx); 552680Sktlim@umich.edu 562680Sktlim@umich.edu /** Reads a floating point register in its binary format, instead 572329SN/A * of by value. */ 582329SN/A FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx); 592292SN/A 602292SN/A /** Sets an integer register to a value. */ 612680Sktlim@umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val); 622733Sktlim@umich.edu 632292SN/A /** Sets a floating point register of single width to a value. */ 642292SN/A void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val); 652348SN/A 662733Sktlim@umich.edu /** Sets the bits of a floating point register of single width 672292SN/A * to a binary value. */ 682348SN/A void setFloatRegOperandBits(const StaticInst *si, int idx, 692348SN/A FloatRegBits val); 702348SN/A 712292SN/A /** Reads the PC. */ 722292SN/A uint64_t readPC(); 732348SN/A /** Reads the NextPC. */ 742348SN/A uint64_t readNextPC(); 752348SN/A /** Reads the Next-NextPC. Only for architectures like SPARC or MIPS. */ 762292SN/A uint64_t readNextNPC(); 772292SN/A 782292SN/A /** Sets the PC. */ 792733Sktlim@umich.edu void setPC(uint64_t val); 803402Sktlim@umich.edu /** Sets the NextPC. */ 812362SN/A void setNextPC(uint64_t val); 822362SN/A /** Sets the Next-NextPC. Only for architectures like SPARC or MIPS. */ 835529Snate@binkert.org void setNextNPC(uint64_t val); 845529Snate@binkert.org 852362SN/A /** Reads a miscellaneous register. */ 862362SN/A MiscReg readMiscRegNoEffect(int misc_reg); 872362SN/A 882362SN/A /** Reads a miscellaneous register, handling any architectural 892362SN/A * side effects due to reading that register. */ 902362SN/A MiscReg readMiscReg(int misc_reg); 912362SN/A 922362SN/A /** Sets a miscellaneous register. */ 932362SN/A void setMiscRegNoEffect(int misc_reg, const MiscReg &val); 942362SN/A 952362SN/A /** Sets a miscellaneous register, handling any architectural 962362SN/A * side effects due to writing that register. */ 972292SN/A void setMiscReg(int misc_reg, const MiscReg &val); 983402Sktlim@umich.edu 993402Sktlim@umich.edu /** Records the effective address of the instruction. Only valid 1002292SN/A * for memory ops. */ 1012292SN/A void setEA(Addr EA); 1022292SN/A /** Returns the effective address of the instruction. Only valid 1032292SN/A * for memory ops. */ 1042680Sktlim@umich.edu Addr getEA(); 1052680Sktlim@umich.edu 1062292SN/A /** Returns a pointer to the ThreadContext. */ 1072680Sktlim@umich.edu ThreadContext *tcBase(); 1082680Sktlim@umich.edu 1092292SN/A Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 1102292SN/A 1112348SN/A Fault writeMem(uint8_t *data, unsigned size, 1122680Sktlim@umich.edu Addr addr, unsigned flags, uint64_t *res); 1132292SN/A 1142362SN/A#if FULL_SYSTEM 1152362SN/A /** Somewhat Alpha-specific function that handles returning from 1162362SN/A * an error or interrupt. */ 1172362SN/A Fault hwrei(); 1182362SN/A 1193126Sktlim@umich.edu /** 1202362SN/A * Check for special simulator handling of specific PAL calls. If 1212362SN/A * return value is false, actual PAL call will be suppressed. 1222292SN/A */ 1232292SN/A bool simPalCheck(int palFunc); 1242292SN/A#else 125 /** Executes a syscall specified by the callnum. */ 126 void syscall(int64_t callnum); 127#endif 128 129 /** Finish a DTB address translation. */ 130 void finishTranslation(WholeTranslationState *state); 131}; 132