exec_context.hh revision 6973
12735Sktlim@umich.edu/* 22735Sktlim@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 32735Sktlim@umich.edu * All rights reserved. 42735Sktlim@umich.edu * 52735Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 62735Sktlim@umich.edu * modification, are permitted provided that the following conditions are 72735Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 82735Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 92735Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 102735Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 112735Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 122735Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 132735Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 142735Sktlim@umich.edu * this software without specific prior written permission. 152735Sktlim@umich.edu * 162735Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172735Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182735Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192735Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202735Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212735Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222735Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232735Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242735Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252735Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262735Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272735Sktlim@umich.edu * 282735Sktlim@umich.edu * Authors: Kevin Lim 292735Sktlim@umich.edu */ 302735Sktlim@umich.edu 312735Sktlim@umich.edu#error "Cannot include this file" 322735Sktlim@umich.edu 332735Sktlim@umich.edu/** 342735Sktlim@umich.edu * The ExecContext is not a usable class. It is simply here for 352735Sktlim@umich.edu * documentation purposes. It shows the interface that is used by the 362735Sktlim@umich.edu * ISA to access and change CPU state. 372735Sktlim@umich.edu */ 382735Sktlim@umich.educlass ExecContext { 392735Sktlim@umich.edu // The register accessor methods provide the index of the 402735Sktlim@umich.edu // instruction's operand (e.g., 0 or 1), not the architectural 412735Sktlim@umich.edu // register index, to simplify the implementation of register 422735Sktlim@umich.edu // renaming. We find the architectural register index by indexing 432735Sktlim@umich.edu // into the instruction's own operand index table. Note that a 442735Sktlim@umich.edu // raw pointer to the StaticInst is provided instead of a 452735Sktlim@umich.edu // ref-counted StaticInstPtr to reduce overhead. This is fine as 462735Sktlim@umich.edu // long as these methods don't copy the pointer into any long-term 472735Sktlim@umich.edu // storage (which is pretty hard to imagine they would have reason 482735Sktlim@umich.edu // to do). 492735Sktlim@umich.edu 502735Sktlim@umich.edu /** Reads an integer register. */ 513735Sstever@eecs.umich.edu uint64_t readIntRegOperand(const StaticInst *si, int idx); 522735Sktlim@umich.edu 532735Sktlim@umich.edu /** Reads a floating point register of single register width. */ 543735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx); 552735Sktlim@umich.edu 562735Sktlim@umich.edu /** Reads a floating point register in its binary format, instead 572735Sktlim@umich.edu * of by value. */ 583735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx); 592735Sktlim@umich.edu 602735Sktlim@umich.edu /** Sets an integer register to a value. */ 613735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val); 622735Sktlim@umich.edu 632735Sktlim@umich.edu /** Sets a floating point register of single width to a value. */ 643735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val); 652735Sktlim@umich.edu 662735Sktlim@umich.edu /** Sets the bits of a floating point register of single width 672735Sktlim@umich.edu * to a binary value. */ 683735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 693735Sstever@eecs.umich.edu FloatRegBits val); 702735Sktlim@umich.edu 712735Sktlim@umich.edu /** Reads the PC. */ 722735Sktlim@umich.edu uint64_t readPC(); 732735Sktlim@umich.edu /** Reads the NextPC. */ 742735Sktlim@umich.edu uint64_t readNextPC(); 752735Sktlim@umich.edu /** Reads the Next-NextPC. Only for architectures like SPARC or MIPS. */ 762735Sktlim@umich.edu uint64_t readNextNPC(); 772735Sktlim@umich.edu 782735Sktlim@umich.edu /** Sets the PC. */ 792735Sktlim@umich.edu void setPC(uint64_t val); 802735Sktlim@umich.edu /** Sets the NextPC. */ 812735Sktlim@umich.edu void setNextPC(uint64_t val); 822735Sktlim@umich.edu /** Sets the Next-NextPC. Only for architectures like SPARC or MIPS. */ 832735Sktlim@umich.edu void setNextNPC(uint64_t val); 842735Sktlim@umich.edu 852735Sktlim@umich.edu /** Reads a miscellaneous register. */ 864172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg); 872735Sktlim@umich.edu 882735Sktlim@umich.edu /** Reads a miscellaneous register, handling any architectural 892735Sktlim@umich.edu * side effects due to reading that register. */ 904172Ssaidi@eecs.umich.edu MiscReg readMiscReg(int misc_reg); 912735Sktlim@umich.edu 922735Sktlim@umich.edu /** Sets a miscellaneous register. */ 934172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val); 942735Sktlim@umich.edu 952735Sktlim@umich.edu /** Sets a miscellaneous register, handling any architectural 962735Sktlim@umich.edu * side effects due to writing that register. */ 974172Ssaidi@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val); 982735Sktlim@umich.edu 992735Sktlim@umich.edu /** Records the effective address of the instruction. Only valid 1002735Sktlim@umich.edu * for memory ops. */ 1012735Sktlim@umich.edu void setEA(Addr EA); 1022735Sktlim@umich.edu /** Returns the effective address of the instruction. Only valid 1032735Sktlim@umich.edu * for memory ops. */ 1042735Sktlim@umich.edu Addr getEA(); 1052735Sktlim@umich.edu 1062735Sktlim@umich.edu /** Returns a pointer to the ThreadContext. */ 1072735Sktlim@umich.edu ThreadContext *tcBase(); 1082735Sktlim@umich.edu 1092735Sktlim@umich.edu /** Reads an address, creating a memory request with the given 1102735Sktlim@umich.edu * flags. Stores result of read in data. */ 1112735Sktlim@umich.edu template <class T> 1122735Sktlim@umich.edu Fault read(Addr addr, T &data, unsigned flags); 1132735Sktlim@umich.edu 1142735Sktlim@umich.edu /** Writes to an address, creating a memory request with the given 1152735Sktlim@umich.edu * flags. Writes data to memory. For store conditionals, returns 1162735Sktlim@umich.edu * the result of the store in res. */ 1172735Sktlim@umich.edu template <class T> 1182735Sktlim@umich.edu Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1192735Sktlim@umich.edu 1202735Sktlim@umich.edu /** Prefetches an address, creating a memory request with the 1212735Sktlim@umich.edu * given flags. */ 1222735Sktlim@umich.edu void prefetch(Addr addr, unsigned flags); 1232735Sktlim@umich.edu 1242735Sktlim@umich.edu /** Hints to the memory system that an address will be written to 1252735Sktlim@umich.edu * soon, with the given size. Creates a memory request with the 1262735Sktlim@umich.edu * given flags. */ 1272735Sktlim@umich.edu void writeHint(Addr addr, int size, unsigned flags); 1282735Sktlim@umich.edu 1295702Ssaidi@eecs.umich.edu#if FULL_SYSTEM 1305702Ssaidi@eecs.umich.edu /** Somewhat Alpha-specific function that handles returning from 1315702Ssaidi@eecs.umich.edu * an error or interrupt. */ 1325702Ssaidi@eecs.umich.edu Fault hwrei(); 1335702Ssaidi@eecs.umich.edu 1345702Ssaidi@eecs.umich.edu /** 1355702Ssaidi@eecs.umich.edu * Check for special simulator handling of specific PAL calls. If 1365702Ssaidi@eecs.umich.edu * return value is false, actual PAL call will be suppressed. 1375702Ssaidi@eecs.umich.edu */ 1385702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 1395702Ssaidi@eecs.umich.edu#else 1402735Sktlim@umich.edu /** Executes a syscall specified by the callnum. */ 1412735Sktlim@umich.edu void syscall(int64_t callnum); 1422735Sktlim@umich.edu#endif 1436973Stjones1@inf.ed.ac.uk 1446973Stjones1@inf.ed.ac.uk /** Finish a DTB address translation. */ 1456973Stjones1@inf.ed.ac.uk void finishTranslation(WholeTranslationState *state); 1462735Sktlim@umich.edu}; 147