exec_context.hh revision 2735
12330SN/A/* 22330SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32330SN/A * All rights reserved. 42330SN/A * 52330SN/A * Redistribution and use in source and binary forms, with or without 62330SN/A * modification, are permitted provided that the following conditions are 72330SN/A * met: redistributions of source code must retain the above copyright 82330SN/A * notice, this list of conditions and the following disclaimer; 92330SN/A * redistributions in binary form must reproduce the above copyright 102330SN/A * notice, this list of conditions and the following disclaimer in the 112330SN/A * documentation and/or other materials provided with the distribution; 122330SN/A * neither the name of the copyright holders nor the names of its 132330SN/A * contributors may be used to endorse or promote products derived from 142330SN/A * this software without specific prior written permission. 152330SN/A * 162330SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172330SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182330SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192330SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202330SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212330SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222330SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232330SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242330SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252330SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262330SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292330SN/A */ 302292SN/A 312292SN/A#error "Cannot include this file" 322292SN/A 332292SN/A/** 342980Sgblack@eecs.umich.edu * The ExecContext is not a usable class. It is simply here for 356658Snate@binkert.org * documentation purposes. It shows the interface that is used by the 368229Snate@binkert.org * ISA to access and change CPU state. 372362SN/A */ 382680Sktlim@umich.educlass ExecContext { 392292SN/A // The register accessor methods provide the index of the 402678Sktlim@umich.edu // instruction's operand (e.g., 0 or 1), not the architectural 412683Sktlim@umich.edu // register index, to simplify the implementation of register 422683Sktlim@umich.edu // renaming. We find the architectural register index by indexing 432678Sktlim@umich.edu // into the instruction's own operand index table. Note that a 442678Sktlim@umich.edu // raw pointer to the StaticInst is provided instead of a 452292SN/A // ref-counted StaticInstPtr to reduce overhead. This is fine as 462292SN/A // long as these methods don't copy the pointer into any long-term 472292SN/A // storage (which is pretty hard to imagine they would have reason 482292SN/A // to do). 493548Sgblack@eecs.umich.edu 503548Sgblack@eecs.umich.edu /** Reads an integer register. */ 513548Sgblack@eecs.umich.edu uint64_t readIntReg(const StaticInst *si, int idx); 523548Sgblack@eecs.umich.edu 532330SN/A /** Reads a floating point register of a specific width. */ 542292SN/A FloatReg readFloatReg(const StaticInst *si, int idx, int width); 552292SN/A 562862Sktlim@umich.edu /** Reads a floating point register of single register width. */ 573486Sktlim@umich.edu FloatReg readFloatReg(const StaticInst *si, int idx); 583402Sktlim@umich.edu 592862Sktlim@umich.edu /** Reads a floating point register of a specific width in its 602330SN/A * binary format, instead of by value. */ 612330SN/A FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width); 622330SN/A 632330SN/A /** Reads a floating point register in its binary format, instead 642330SN/A * of by value. */ 652330SN/A FloatRegBits readFloatRegBits(const StaticInst *si, int idx); 662292SN/A 672683Sktlim@umich.edu /** Sets an integer register to a value. */ 682683Sktlim@umich.edu void setIntReg(const StaticInst *si, int idx, uint64_t val); 692292SN/A 706221Snate@binkert.org /** Sets a floating point register of a specific width to a value. */ 712292SN/A void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width); 726331Sgblack@eecs.umich.edu 732292SN/A /** Sets a floating point register of single width to a value. */ 742683Sktlim@umich.edu void setFloatReg(const StaticInst *si, int idx, FloatReg val); 753486Sktlim@umich.edu 763486Sktlim@umich.edu /** Sets the bits of a floating point register of a specific width 772862Sktlim@umich.edu * to a binary value. */ 782862Sktlim@umich.edu void setFloatRegBits(const StaticInst *si, int idx, 792862Sktlim@umich.edu FloatRegBits val, int width); 802862Sktlim@umich.edu 815712Shsul@eecs.umich.edu /** Sets the bits of a floating point register of single width 822683Sktlim@umich.edu * to a binary value. */ 835714Shsul@eecs.umich.edu void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val); 845714Shsul@eecs.umich.edu 855714Shsul@eecs.umich.edu /** Reads the PC. */ 865714Shsul@eecs.umich.edu uint64_t readPC(); 876221Snate@binkert.org /** Reads the NextPC. */ 882683Sktlim@umich.edu uint64_t readNextPC(); 896221Snate@binkert.org /** Reads the Next-NextPC. Only for architectures like SPARC or MIPS. */ 902683Sktlim@umich.edu uint64_t readNextNPC(); 912683Sktlim@umich.edu 922683Sktlim@umich.edu /** Sets the PC. */ 932683Sktlim@umich.edu void setPC(uint64_t val); 942683Sktlim@umich.edu /** Sets the NextPC. */ 952683Sktlim@umich.edu void setNextPC(uint64_t val); 965497Ssaidi@eecs.umich.edu /** Sets the Next-NextPC. Only for architectures like SPARC or MIPS. */ 973675Sktlim@umich.edu void setNextNPC(uint64_t val); 983686Sktlim@umich.edu 993675Sktlim@umich.edu /** Reads a miscellaneous register. */ 1005497Ssaidi@eecs.umich.edu MiscReg readMiscReg(int misc_reg); 1013675Sktlim@umich.edu 1022683Sktlim@umich.edu /** Reads a miscellaneous register, handling any architectural 1032683Sktlim@umich.edu * side effects due to reading that register. */ 1042683Sktlim@umich.edu MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault); 1052683Sktlim@umich.edu 1062683Sktlim@umich.edu /** Sets a miscellaneous register. */ 1072683Sktlim@umich.edu Fault setMiscReg(int misc_reg, const MiscReg &val); 1082683Sktlim@umich.edu 1092683Sktlim@umich.edu /** Sets a miscellaneous register, handling any architectural 1103548Sgblack@eecs.umich.edu * side effects due to writing that register. */ 1112683Sktlim@umich.edu Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val); 1122690Sktlim@umich.edu 1132690Sktlim@umich.edu /** Records the effective address of the instruction. Only valid 1142683Sktlim@umich.edu * for memory ops. */ 1152683Sktlim@umich.edu void setEA(Addr EA); 1165499Ssaidi@eecs.umich.edu /** Returns the effective address of the instruction. Only valid 1172683Sktlim@umich.edu * for memory ops. */ 1182683Sktlim@umich.edu Addr getEA(); 1192683Sktlim@umich.edu 1203402Sktlim@umich.edu /** Returns a pointer to the ThreadContext. */ 1212683Sktlim@umich.edu ThreadContext *tcBase(); 1222683Sktlim@umich.edu 1232678Sktlim@umich.edu /** Reads an address, creating a memory request with the given 1242292SN/A * flags. Stores result of read in data. */ 1252683Sktlim@umich.edu template <class T> 1262683Sktlim@umich.edu Fault read(Addr addr, T &data, unsigned flags); 1272683Sktlim@umich.edu 1282683Sktlim@umich.edu /** Writes to an address, creating a memory request with the given 1292683Sktlim@umich.edu * flags. Writes data to memory. For store conditionals, returns 1302683Sktlim@umich.edu * the result of the store in res. */ 1312683Sktlim@umich.edu template <class T> 1322683Sktlim@umich.edu Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1332683Sktlim@umich.edu 1342683Sktlim@umich.edu /** Prefetches an address, creating a memory request with the 1352683Sktlim@umich.edu * given flags. */ 1362683Sktlim@umich.edu void prefetch(Addr addr, unsigned flags); 1372683Sktlim@umich.edu 1382683Sktlim@umich.edu /** Hints to the memory system that an address will be written to 1392683Sktlim@umich.edu * soon, with the given size. Creates a memory request with the 1402683Sktlim@umich.edu * given flags. */ 1413673Srdreslin@umich.edu void writeHint(Addr addr, int size, unsigned flags); 1423675Sktlim@umich.edu 1433675Sktlim@umich.edu#if FULL_SYSTEM 1443675Sktlim@umich.edu /** Somewhat Alpha-specific function that handles returning from 1453486Sktlim@umich.edu * an error or interrupt. */ 1462683Sktlim@umich.edu Fault hwrei(); 1472683Sktlim@umich.edu /** Reads the interrupt flags. */ 1482683Sktlim@umich.edu int readIntrFlag(); 1495999Snate@binkert.org /** Sets the interrupt flags to a value. */ 1502683Sktlim@umich.edu void setIntrFlag(int val); 1515999Snate@binkert.org 1522683Sktlim@umich.edu /** 1532683Sktlim@umich.edu * Check for special simulator handling of specific PAL calls. If 1542683Sktlim@umich.edu * return value is false, actual PAL call will be suppressed. 1552683Sktlim@umich.edu */ 1562683Sktlim@umich.edu bool simPalCheck(int palFunc); 1572683Sktlim@umich.edu#else 1582683Sktlim@umich.edu /** Executes a syscall specified by the callnum. */ 1592683Sktlim@umich.edu void syscall(int64_t callnum); 1602683Sktlim@umich.edu#endif 1612683Sktlim@umich.edu}; 1622683Sktlim@umich.edu