exec_context.hh revision 13954
12735Sktlim@umich.edu/* 213953Sgiacomo.gabrielli@arm.com * Copyright (c) 2014, 2016-2018 ARM Limited 310319SAndreas.Sandberg@ARM.com * All rights reserved 410319SAndreas.Sandberg@ARM.com * 510319SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 610319SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 710319SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 810319SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 910319SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 1010319SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 1110319SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 1210319SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 1310319SAndreas.Sandberg@ARM.com * 142735Sktlim@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511303Ssteve.reinhardt@amd.com * Copyright (c) 2015 Advanced Micro Devices, Inc. 162735Sktlim@umich.edu * All rights reserved. 172735Sktlim@umich.edu * 182735Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 192735Sktlim@umich.edu * modification, are permitted provided that the following conditions are 202735Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 212735Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 222735Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 232735Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 242735Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 252735Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 262735Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 272735Sktlim@umich.edu * this software without specific prior written permission. 282735Sktlim@umich.edu * 292735Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302735Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312735Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322735Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332735Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342735Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352735Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362735Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372735Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382735Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392735Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402735Sktlim@umich.edu * 412735Sktlim@umich.edu * Authors: Kevin Lim 4210319SAndreas.Sandberg@ARM.com * Andreas Sandberg 432735Sktlim@umich.edu */ 442735Sktlim@umich.edu 4510319SAndreas.Sandberg@ARM.com#ifndef __CPU_EXEC_CONTEXT_HH__ 4610319SAndreas.Sandberg@ARM.com#define __CPU_EXEC_CONTEXT_HH__ 4710319SAndreas.Sandberg@ARM.com 4810319SAndreas.Sandberg@ARM.com#include "arch/registers.hh" 4910319SAndreas.Sandberg@ARM.com#include "base/types.hh" 5010319SAndreas.Sandberg@ARM.com#include "config/the_isa.hh" 5110529Smorr@cs.wisc.edu#include "cpu/base.hh" 5212104Snathanael.premillieu@arm.com#include "cpu/reg_class.hh" 5310319SAndreas.Sandberg@ARM.com#include "cpu/static_inst_fwd.hh" 5410319SAndreas.Sandberg@ARM.com#include "cpu/translation.hh" 5511608Snikos.nikoleris@arm.com#include "mem/request.hh" 562735Sktlim@umich.edu 572735Sktlim@umich.edu/** 5810319SAndreas.Sandberg@ARM.com * The ExecContext is an abstract base class the provides the 5910319SAndreas.Sandberg@ARM.com * interface used by the ISA to manipulate the state of the CPU model. 6010319SAndreas.Sandberg@ARM.com * 6110319SAndreas.Sandberg@ARM.com * Register accessor methods in this class typically provide the index 6210319SAndreas.Sandberg@ARM.com * of the instruction's operand (e.g., 0 or 1), not the architectural 6310319SAndreas.Sandberg@ARM.com * register index, to simplify the implementation of register 6410319SAndreas.Sandberg@ARM.com * renaming. The architectural register index can be found by 6510319SAndreas.Sandberg@ARM.com * indexing into the instruction's own operand index table. 6610319SAndreas.Sandberg@ARM.com * 6710319SAndreas.Sandberg@ARM.com * @note The methods in this class typically take a raw pointer to the 6810319SAndreas.Sandberg@ARM.com * StaticInst is provided instead of a ref-counted StaticInstPtr to 6910319SAndreas.Sandberg@ARM.com * reduce overhead as an argument. This is fine as long as the 7010319SAndreas.Sandberg@ARM.com * implementation doesn't copy the pointer into any long-term storage 7110319SAndreas.Sandberg@ARM.com * (which is pretty hard to imagine they would have reason to do). 722735Sktlim@umich.edu */ 732735Sktlim@umich.educlass ExecContext { 7410319SAndreas.Sandberg@ARM.com public: 7510319SAndreas.Sandberg@ARM.com typedef TheISA::PCState PCState; 7610319SAndreas.Sandberg@ARM.com 7712109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 7812109SRekai.GonzalezAlberquilla@arm.com using VecElem = TheISA::VecElem; 7913610Sgiacomo.gabrielli@arm.com using VecPredRegContainer = TheISA::VecPredRegContainer; 8010319SAndreas.Sandberg@ARM.com 8110319SAndreas.Sandberg@ARM.com public: 8210319SAndreas.Sandberg@ARM.com /** 8310319SAndreas.Sandberg@ARM.com * @{ 8410319SAndreas.Sandberg@ARM.com * @name Integer Register Interfaces 8510319SAndreas.Sandberg@ARM.com * 8610319SAndreas.Sandberg@ARM.com */ 872735Sktlim@umich.edu 882735Sktlim@umich.edu /** Reads an integer register. */ 8913557Sgabeblack@google.com virtual RegVal readIntRegOperand(const StaticInst *si, int idx) = 0; 9010319SAndreas.Sandberg@ARM.com 9110319SAndreas.Sandberg@ARM.com /** Sets an integer register to a value. */ 9210319SAndreas.Sandberg@ARM.com virtual void setIntRegOperand(const StaticInst *si, 9313557Sgabeblack@google.com int idx, RegVal val) = 0; 9410319SAndreas.Sandberg@ARM.com 9510319SAndreas.Sandberg@ARM.com /** @} */ 9610319SAndreas.Sandberg@ARM.com 9710319SAndreas.Sandberg@ARM.com 9810319SAndreas.Sandberg@ARM.com /** 9910319SAndreas.Sandberg@ARM.com * @{ 10010319SAndreas.Sandberg@ARM.com * @name Floating Point Register Interfaces 10110319SAndreas.Sandberg@ARM.com */ 1022735Sktlim@umich.edu 1032735Sktlim@umich.edu /** Reads a floating point register in its binary format, instead 1042735Sktlim@umich.edu * of by value. */ 10513557Sgabeblack@google.com virtual RegVal readFloatRegOperandBits(const StaticInst *si, int idx) = 0; 1062735Sktlim@umich.edu 1072735Sktlim@umich.edu /** Sets the bits of a floating point register of single width 1082735Sktlim@umich.edu * to a binary value. */ 10910319SAndreas.Sandberg@ARM.com virtual void setFloatRegOperandBits(const StaticInst *si, 11013557Sgabeblack@google.com int idx, RegVal val) = 0; 1112735Sktlim@umich.edu 11210319SAndreas.Sandberg@ARM.com /** @} */ 1132735Sktlim@umich.edu 11412109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Interfaces. */ 11512109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 11612109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector register operand. */ 11712109SRekai.GonzalezAlberquilla@arm.com virtual const VecRegContainer& 11812109SRekai.GonzalezAlberquilla@arm.com readVecRegOperand(const StaticInst *si, int idx) const = 0; 11912109SRekai.GonzalezAlberquilla@arm.com 12012109SRekai.GonzalezAlberquilla@arm.com /** Gets destination vector register operand for modification. */ 12112109SRekai.GonzalezAlberquilla@arm.com virtual VecRegContainer& 12212109SRekai.GonzalezAlberquilla@arm.com getWritableVecRegOperand(const StaticInst *si, int idx) = 0; 12312109SRekai.GonzalezAlberquilla@arm.com 12412109SRekai.GonzalezAlberquilla@arm.com /** Sets a destination vector register operand to a value. */ 12512109SRekai.GonzalezAlberquilla@arm.com virtual void 12612109SRekai.GonzalezAlberquilla@arm.com setVecRegOperand(const StaticInst *si, int idx, 12712109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& val) = 0; 12812109SRekai.GonzalezAlberquilla@arm.com /** @} */ 12912109SRekai.GonzalezAlberquilla@arm.com 13012109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 13112109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 13212109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 13312109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane8 13412109SRekai.GonzalezAlberquilla@arm.com readVec8BitLaneOperand(const StaticInst *si, int idx) const = 0; 13512109SRekai.GonzalezAlberquilla@arm.com 13612109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 13712109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane16 13812109SRekai.GonzalezAlberquilla@arm.com readVec16BitLaneOperand(const StaticInst *si, int idx) const = 0; 13912109SRekai.GonzalezAlberquilla@arm.com 14012109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 14112109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane32 14212109SRekai.GonzalezAlberquilla@arm.com readVec32BitLaneOperand(const StaticInst *si, int idx) const = 0; 14312109SRekai.GonzalezAlberquilla@arm.com 14412109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 14512109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane64 14612109SRekai.GonzalezAlberquilla@arm.com readVec64BitLaneOperand(const StaticInst *si, int idx) const = 0; 14712109SRekai.GonzalezAlberquilla@arm.com 14812109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector operand. */ 14912109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 15012109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLaneOperand(const StaticInst *si, int idx, 15112109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) = 0; 15212109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLaneOperand(const StaticInst *si, int idx, 15312109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) = 0; 15412109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLaneOperand(const StaticInst *si, int idx, 15512109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) = 0; 15612109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLaneOperand(const StaticInst *si, int idx, 15712109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) = 0; 15812109SRekai.GonzalezAlberquilla@arm.com /** @} */ 15912109SRekai.GonzalezAlberquilla@arm.com 16012109SRekai.GonzalezAlberquilla@arm.com /** Vector Elem Interfaces. */ 16112109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 16212109SRekai.GonzalezAlberquilla@arm.com /** Reads an element of a vector register. */ 16312109SRekai.GonzalezAlberquilla@arm.com virtual VecElem readVecElemOperand(const StaticInst *si, 16412109SRekai.GonzalezAlberquilla@arm.com int idx) const = 0; 16512109SRekai.GonzalezAlberquilla@arm.com 16612109SRekai.GonzalezAlberquilla@arm.com /** Sets a vector register to a value. */ 16712109SRekai.GonzalezAlberquilla@arm.com virtual void setVecElemOperand(const StaticInst *si, int idx, 16812109SRekai.GonzalezAlberquilla@arm.com const VecElem val) = 0; 16912109SRekai.GonzalezAlberquilla@arm.com /** @} */ 17012109SRekai.GonzalezAlberquilla@arm.com 17113610Sgiacomo.gabrielli@arm.com /** Predicate registers interface. */ 17213610Sgiacomo.gabrielli@arm.com /** @{ */ 17313610Sgiacomo.gabrielli@arm.com /** Reads source predicate register operand. */ 17413610Sgiacomo.gabrielli@arm.com virtual const VecPredRegContainer& 17513610Sgiacomo.gabrielli@arm.com readVecPredRegOperand(const StaticInst *si, int idx) const = 0; 17613610Sgiacomo.gabrielli@arm.com 17713610Sgiacomo.gabrielli@arm.com /** Gets destination predicate register operand for modification. */ 17813610Sgiacomo.gabrielli@arm.com virtual VecPredRegContainer& 17913610Sgiacomo.gabrielli@arm.com getWritableVecPredRegOperand(const StaticInst *si, int idx) = 0; 18013610Sgiacomo.gabrielli@arm.com 18113610Sgiacomo.gabrielli@arm.com /** Sets a destination predicate register operand to a value. */ 18213610Sgiacomo.gabrielli@arm.com virtual void 18313610Sgiacomo.gabrielli@arm.com setVecPredRegOperand(const StaticInst *si, int idx, 18413610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& val) = 0; 18513610Sgiacomo.gabrielli@arm.com /** @} */ 18613610Sgiacomo.gabrielli@arm.com 18710319SAndreas.Sandberg@ARM.com /** 18810319SAndreas.Sandberg@ARM.com * @{ 18910319SAndreas.Sandberg@ARM.com * @name Condition Code Registers 19010319SAndreas.Sandberg@ARM.com */ 19113622Sgabeblack@google.com virtual RegVal readCCRegOperand(const StaticInst *si, int idx) = 0; 19213622Sgabeblack@google.com virtual void setCCRegOperand( 19313622Sgabeblack@google.com const StaticInst *si, int idx, RegVal val) = 0; 19410319SAndreas.Sandberg@ARM.com /** @} */ 1952735Sktlim@umich.edu 19610319SAndreas.Sandberg@ARM.com /** 19710319SAndreas.Sandberg@ARM.com * @{ 19810319SAndreas.Sandberg@ARM.com * @name Misc Register Interfaces 19910319SAndreas.Sandberg@ARM.com */ 20013557Sgabeblack@google.com virtual RegVal readMiscRegOperand(const StaticInst *si, int idx) = 0; 20110319SAndreas.Sandberg@ARM.com virtual void setMiscRegOperand(const StaticInst *si, 20213582Sgabeblack@google.com int idx, RegVal val) = 0; 2032735Sktlim@umich.edu 20410319SAndreas.Sandberg@ARM.com /** 20510319SAndreas.Sandberg@ARM.com * Reads a miscellaneous register, handling any architectural 20610319SAndreas.Sandberg@ARM.com * side effects due to reading that register. 20710319SAndreas.Sandberg@ARM.com */ 20813557Sgabeblack@google.com virtual RegVal readMiscReg(int misc_reg) = 0; 2092735Sktlim@umich.edu 21010319SAndreas.Sandberg@ARM.com /** 21110319SAndreas.Sandberg@ARM.com * Sets a miscellaneous register, handling any architectural 21210319SAndreas.Sandberg@ARM.com * side effects due to writing that register. 21310319SAndreas.Sandberg@ARM.com */ 21413582Sgabeblack@google.com virtual void setMiscReg(int misc_reg, RegVal val) = 0; 2152735Sktlim@umich.edu 21610319SAndreas.Sandberg@ARM.com /** @} */ 2172735Sktlim@umich.edu 21810319SAndreas.Sandberg@ARM.com /** 21910319SAndreas.Sandberg@ARM.com * @{ 22010319SAndreas.Sandberg@ARM.com * @name PC Control 22110319SAndreas.Sandberg@ARM.com */ 22210319SAndreas.Sandberg@ARM.com virtual PCState pcState() const = 0; 22310319SAndreas.Sandberg@ARM.com virtual void pcState(const PCState &val) = 0; 22410319SAndreas.Sandberg@ARM.com /** @} */ 22510319SAndreas.Sandberg@ARM.com 22610319SAndreas.Sandberg@ARM.com /** 22710319SAndreas.Sandberg@ARM.com * @{ 22810319SAndreas.Sandberg@ARM.com * @name Memory Interface 22910319SAndreas.Sandberg@ARM.com */ 23010319SAndreas.Sandberg@ARM.com /** 23111303Ssteve.reinhardt@amd.com * Perform an atomic memory read operation. Must be overridden 23211303Ssteve.reinhardt@amd.com * for exec contexts that support atomic memory mode. Not pure 23311303Ssteve.reinhardt@amd.com * virtual since exec contexts that only support timing memory 23411303Ssteve.reinhardt@amd.com * mode need not override (though in that case this function 23511303Ssteve.reinhardt@amd.com * should never be called). 23611303Ssteve.reinhardt@amd.com */ 23710319SAndreas.Sandberg@ARM.com virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size, 23813954Sgiacomo.gabrielli@arm.com Request::Flags flags, 23913954Sgiacomo.gabrielli@arm.com const std::vector<bool>& byteEnable = std::vector<bool>()) 24011303Ssteve.reinhardt@amd.com { 24111303Ssteve.reinhardt@amd.com panic("ExecContext::readMem() should be overridden\n"); 24211303Ssteve.reinhardt@amd.com } 24310319SAndreas.Sandberg@ARM.com 24411303Ssteve.reinhardt@amd.com /** 24511303Ssteve.reinhardt@amd.com * Initiate a timing memory read operation. Must be overridden 24611303Ssteve.reinhardt@amd.com * for exec contexts that support timing memory mode. Not pure 24711303Ssteve.reinhardt@amd.com * virtual since exec contexts that only support atomic memory 24811303Ssteve.reinhardt@amd.com * mode need not override (though in that case this function 24911303Ssteve.reinhardt@amd.com * should never be called). 25011303Ssteve.reinhardt@amd.com */ 25111303Ssteve.reinhardt@amd.com virtual Fault initiateMemRead(Addr addr, unsigned int size, 25213954Sgiacomo.gabrielli@arm.com Request::Flags flags, 25313954Sgiacomo.gabrielli@arm.com const std::vector<bool>& byteEnable = std::vector<bool>()) 25411303Ssteve.reinhardt@amd.com { 25511303Ssteve.reinhardt@amd.com panic("ExecContext::initiateMemRead() should be overridden\n"); 25611303Ssteve.reinhardt@amd.com } 25711303Ssteve.reinhardt@amd.com 25811303Ssteve.reinhardt@amd.com /** 25911303Ssteve.reinhardt@amd.com * For atomic-mode contexts, perform an atomic memory write operation. 26011303Ssteve.reinhardt@amd.com * For timing-mode contexts, initiate a timing memory write operation. 26111303Ssteve.reinhardt@amd.com */ 26210319SAndreas.Sandberg@ARM.com virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr, 26313954Sgiacomo.gabrielli@arm.com Request::Flags flags, uint64_t *res, 26413954Sgiacomo.gabrielli@arm.com const std::vector<bool>& byteEnable = 26513954Sgiacomo.gabrielli@arm.com std::vector<bool>()) = 0; 26610319SAndreas.Sandberg@ARM.com 26710319SAndreas.Sandberg@ARM.com /** 26813652Sqtt2@cornell.edu * For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic 26913652Sqtt2@cornell.edu * Read-Modify-Write Memory Operation) 27013652Sqtt2@cornell.edu */ 27113652Sqtt2@cornell.edu virtual Fault amoMem(Addr addr, uint8_t *data, unsigned int size, 27213652Sqtt2@cornell.edu Request::Flags flags, 27313652Sqtt2@cornell.edu AtomicOpFunctor *amo_op) 27413652Sqtt2@cornell.edu { 27513652Sqtt2@cornell.edu panic("ExecContext::amoMem() should be overridden\n"); 27613652Sqtt2@cornell.edu } 27713652Sqtt2@cornell.edu 27813652Sqtt2@cornell.edu /** 27913652Sqtt2@cornell.edu * For timing-mode contexts, initiate an atomic AMO (atomic 28013652Sqtt2@cornell.edu * read-modify-write memory operation) 28113652Sqtt2@cornell.edu */ 28213652Sqtt2@cornell.edu virtual Fault initiateMemAMO(Addr addr, unsigned int size, 28313652Sqtt2@cornell.edu Request::Flags flags, 28413652Sqtt2@cornell.edu AtomicOpFunctor *amo_op) 28513652Sqtt2@cornell.edu { 28613652Sqtt2@cornell.edu panic("ExecContext::initiateMemAMO() should be overridden\n"); 28713652Sqtt2@cornell.edu } 28813652Sqtt2@cornell.edu 28913652Sqtt2@cornell.edu /** 29010319SAndreas.Sandberg@ARM.com * Sets the number of consecutive store conditional failures. 29110319SAndreas.Sandberg@ARM.com */ 29210319SAndreas.Sandberg@ARM.com virtual void setStCondFailures(unsigned int sc_failures) = 0; 29310319SAndreas.Sandberg@ARM.com 29410319SAndreas.Sandberg@ARM.com /** 29510319SAndreas.Sandberg@ARM.com * Returns the number of consecutive store conditional failures. 29610319SAndreas.Sandberg@ARM.com */ 29710319SAndreas.Sandberg@ARM.com virtual unsigned int readStCondFailures() const = 0; 29810319SAndreas.Sandberg@ARM.com 29910319SAndreas.Sandberg@ARM.com /** @} */ 30010319SAndreas.Sandberg@ARM.com 30110319SAndreas.Sandberg@ARM.com /** 30210319SAndreas.Sandberg@ARM.com * @{ 30310319SAndreas.Sandberg@ARM.com * @name SysCall Emulation Interfaces 30410319SAndreas.Sandberg@ARM.com */ 30510319SAndreas.Sandberg@ARM.com 30610319SAndreas.Sandberg@ARM.com /** 30710319SAndreas.Sandberg@ARM.com * Executes a syscall specified by the callnum. 30810319SAndreas.Sandberg@ARM.com */ 30911877Sbrandon.potter@amd.com virtual void syscall(int64_t callnum, Fault *fault) = 0; 31010319SAndreas.Sandberg@ARM.com 31110319SAndreas.Sandberg@ARM.com /** @} */ 3122735Sktlim@umich.edu 3132735Sktlim@umich.edu /** Returns a pointer to the ThreadContext. */ 31410319SAndreas.Sandberg@ARM.com virtual ThreadContext *tcBase() = 0; 3152735Sktlim@umich.edu 31610319SAndreas.Sandberg@ARM.com /** 31710319SAndreas.Sandberg@ARM.com * @{ 31810319SAndreas.Sandberg@ARM.com * @name ARM-Specific Interfaces 31910319SAndreas.Sandberg@ARM.com */ 32010319SAndreas.Sandberg@ARM.com 32113429Srekai.gonzalezalberquilla@arm.com virtual bool readPredicate() const = 0; 32210319SAndreas.Sandberg@ARM.com virtual void setPredicate(bool val) = 0; 32313953Sgiacomo.gabrielli@arm.com virtual bool readMemAccPredicate() const = 0; 32413953Sgiacomo.gabrielli@arm.com virtual void setMemAccPredicate(bool val) = 0; 32510319SAndreas.Sandberg@ARM.com 32610319SAndreas.Sandberg@ARM.com /** @} */ 32710319SAndreas.Sandberg@ARM.com 32810319SAndreas.Sandberg@ARM.com /** 32910319SAndreas.Sandberg@ARM.com * @{ 33010319SAndreas.Sandberg@ARM.com * @name X86-Specific Interfaces 33110319SAndreas.Sandberg@ARM.com */ 33210319SAndreas.Sandberg@ARM.com 33310319SAndreas.Sandberg@ARM.com /** 33410319SAndreas.Sandberg@ARM.com * Invalidate a page in the DTLB <i>and</i> ITLB. 33510319SAndreas.Sandberg@ARM.com */ 33610319SAndreas.Sandberg@ARM.com virtual void demapPage(Addr vaddr, uint64_t asn) = 0; 33710529Smorr@cs.wisc.edu virtual void armMonitor(Addr address) = 0; 33810529Smorr@cs.wisc.edu virtual bool mwait(PacketPtr pkt) = 0; 33910529Smorr@cs.wisc.edu virtual void mwaitAtomic(ThreadContext *tc) = 0; 34010529Smorr@cs.wisc.edu virtual AddressMonitor *getAddrMonitor() = 0; 34110319SAndreas.Sandberg@ARM.com 34210319SAndreas.Sandberg@ARM.com /** @} */ 3432735Sktlim@umich.edu}; 34410319SAndreas.Sandberg@ARM.com 34510319SAndreas.Sandberg@ARM.com#endif // __CPU_EXEC_CONTEXT_HH__ 346