exec_context.hh revision 13429
12036SN/A/* 22036SN/A * Copyright (c) 2014, 2016 ARM Limited 32036SN/A * All rights reserved 42036SN/A * 52036SN/A * The license below extends only to copyright in the software and shall 62036SN/A * not be construed as granting a license to any other intellectual 72036SN/A * property including but not limited to intellectual property relating 82036SN/A * to a hardware implementation of the functionality of the software 92036SN/A * licensed hereunder. You may use the software subject to the license 102036SN/A * terms below provided that you ensure that this notice is replicated 112036SN/A * unmodified and in its entirety in all distributions of the software, 122036SN/A * modified or unmodified, in source code or in binary form. 132036SN/A * 142036SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152036SN/A * Copyright (c) 2015 Advanced Micro Devices, Inc. 162036SN/A * All rights reserved. 172036SN/A * 182036SN/A * Redistribution and use in source and binary forms, with or without 192036SN/A * modification, are permitted provided that the following conditions are 202036SN/A * met: redistributions of source code must retain the above copyright 212036SN/A * notice, this list of conditions and the following disclaimer; 222036SN/A * redistributions in binary form must reproduce the above copyright 232036SN/A * notice, this list of conditions and the following disclaimer in the 242036SN/A * documentation and/or other materials provided with the distribution; 252036SN/A * neither the name of the copyright holders nor the names of its 262036SN/A * contributors may be used to endorse or promote products derived from 272665Ssaidi@eecs.umich.edu * this software without specific prior written permission. 282956Sgblack@eecs.umich.edu * 292956Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302772Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312036SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322036SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332036SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342036SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352036SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362036SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372036SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382036SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392036SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402779Sbinkertn@umich.edu * 412036SN/A * Authors: Kevin Lim 422036SN/A * Andreas Sandberg 432036SN/A */ 442036SN/A 452036SN/A#ifndef __CPU_EXEC_CONTEXT_HH__ 462565SN/A#define __CPU_EXEC_CONTEXT_HH__ 472565SN/A 482565SN/A#include "arch/registers.hh" 492565SN/A#include "base/types.hh" 502036SN/A#include "config/the_isa.hh" 512036SN/A#include "cpu/base.hh" 522036SN/A#include "cpu/reg_class.hh" 532036SN/A#include "cpu/static_inst_fwd.hh" 542778Ssaidi@eecs.umich.edu#include "cpu/translation.hh" 552778Ssaidi@eecs.umich.edu#include "mem/request.hh" 562778Ssaidi@eecs.umich.edu 572778Ssaidi@eecs.umich.edu/** 582036SN/A * The ExecContext is an abstract base class the provides the 592036SN/A * interface used by the ISA to manipulate the state of the CPU model. 602036SN/A * 612036SN/A * Register accessor methods in this class typically provide the index 622036SN/A * of the instruction's operand (e.g., 0 or 1), not the architectural 632565SN/A * register index, to simplify the implementation of register 642565SN/A * renaming. The architectural register index can be found by 652778Ssaidi@eecs.umich.edu * indexing into the instruction's own operand index table. 662778Ssaidi@eecs.umich.edu * 672565SN/A * @note The methods in this class typically take a raw pointer to the 682036SN/A * StaticInst is provided instead of a ref-counted StaticInstPtr to 692036SN/A * reduce overhead as an argument. This is fine as long as the 702036SN/A * implementation doesn't copy the pointer into any long-term storage 712036SN/A * (which is pretty hard to imagine they would have reason to do). 722036SN/A */ 732036SN/Aclass ExecContext { 742036SN/A public: 752036SN/A typedef TheISA::IntReg IntReg; 762565SN/A typedef TheISA::PCState PCState; 772036SN/A typedef TheISA::FloatReg FloatReg; 782036SN/A typedef TheISA::FloatRegBits FloatRegBits; 792036SN/A typedef TheISA::MiscReg MiscReg; 802036SN/A 812036SN/A typedef TheISA::CCReg CCReg; 822565SN/A using VecRegContainer = TheISA::VecRegContainer; 832565SN/A using VecElem = TheISA::VecElem; 842778Ssaidi@eecs.umich.edu 852778Ssaidi@eecs.umich.edu public: 862565SN/A /** 872036SN/A * @{ 882036SN/A * @name Integer Register Interfaces 892036SN/A * 902565SN/A */ 912036SN/A 922036SN/A /** Reads an integer register. */ 932036SN/A virtual IntReg readIntRegOperand(const StaticInst *si, int idx) = 0; 942036SN/A 952036SN/A /** Sets an integer register to a value. */ 962565SN/A virtual void setIntRegOperand(const StaticInst *si, 972565SN/A int idx, IntReg val) = 0; 982778Ssaidi@eecs.umich.edu 992778Ssaidi@eecs.umich.edu /** @} */ 1002565SN/A 1012036SN/A 1022036SN/A /** 1032565SN/A * @{ 1042036SN/A * @name Floating Point Register Interfaces 1052036SN/A */ 1062764Sstever@eecs.umich.edu 1072764Sstever@eecs.umich.edu /** Reads a floating point register of single register width. */ 1082764Sstever@eecs.umich.edu virtual FloatReg readFloatRegOperand(const StaticInst *si, int idx) = 0; 1092764Sstever@eecs.umich.edu 1102764Sstever@eecs.umich.edu /** Reads a floating point register in its binary format, instead 1112764Sstever@eecs.umich.edu * of by value. */ 1122764Sstever@eecs.umich.edu virtual FloatRegBits readFloatRegOperandBits(const StaticInst *si, 1132764Sstever@eecs.umich.edu int idx) = 0; 1142764Sstever@eecs.umich.edu 1152764Sstever@eecs.umich.edu /** Sets a floating point register of single width to a value. */ 1162764Sstever@eecs.umich.edu virtual void setFloatRegOperand(const StaticInst *si, 1172764Sstever@eecs.umich.edu int idx, FloatReg val) = 0; 1182764Sstever@eecs.umich.edu 1192764Sstever@eecs.umich.edu /** Sets the bits of a floating point register of single width 1202764Sstever@eecs.umich.edu * to a binary value. */ 1212764Sstever@eecs.umich.edu virtual void setFloatRegOperandBits(const StaticInst *si, 1222764Sstever@eecs.umich.edu int idx, FloatRegBits val) = 0; 1232036SN/A 1242036SN/A /** @} */ 1252036SN/A 1262036SN/A /** Vector Register Interfaces. */ 1272036SN/A /** @{ */ 1282036SN/A /** Reads source vector register operand. */ 1292036SN/A virtual const VecRegContainer& 1302036SN/A readVecRegOperand(const StaticInst *si, int idx) const = 0; 1312036SN/A 1322036SN/A /** Gets destination vector register operand for modification. */ 1332036SN/A virtual VecRegContainer& 1342036SN/A getWritableVecRegOperand(const StaticInst *si, int idx) = 0; 1352036SN/A 1362036SN/A /** Sets a destination vector register operand to a value. */ 1372036SN/A virtual void 1382036SN/A setVecRegOperand(const StaticInst *si, int idx, 1392036SN/A const VecRegContainer& val) = 0; 1402036SN/A /** @} */ 1412036SN/A 1422036SN/A /** Vector Register Lane Interfaces. */ 1432036SN/A /** @{ */ 1442036SN/A /** Reads source vector 8bit operand. */ 1452036SN/A virtual ConstVecLane8 1462036SN/A readVec8BitLaneOperand(const StaticInst *si, int idx) const = 0; 1472036SN/A 1482036SN/A /** Reads source vector 16bit operand. */ 1492036SN/A virtual ConstVecLane16 1502036SN/A readVec16BitLaneOperand(const StaticInst *si, int idx) const = 0; 1512036SN/A 1522036SN/A /** Reads source vector 32bit operand. */ 1532036SN/A virtual ConstVecLane32 1542036SN/A readVec32BitLaneOperand(const StaticInst *si, int idx) const = 0; 1552036SN/A 1562036SN/A /** Reads source vector 64bit operand. */ 1572036SN/A virtual ConstVecLane64 1582036SN/A readVec64BitLaneOperand(const StaticInst *si, int idx) const = 0; 1592036SN/A 1602036SN/A /** Write a lane of the destination vector operand. */ 1612036SN/A /** @{ */ 1622036SN/A virtual void setVecLaneOperand(const StaticInst *si, int idx, 1632036SN/A const LaneData<LaneSize::Byte>& val) = 0; 1642036SN/A virtual void setVecLaneOperand(const StaticInst *si, int idx, 1652036SN/A const LaneData<LaneSize::TwoByte>& val) = 0; 1662036SN/A virtual void setVecLaneOperand(const StaticInst *si, int idx, 1672036SN/A const LaneData<LaneSize::FourByte>& val) = 0; 1682036SN/A virtual void setVecLaneOperand(const StaticInst *si, int idx, 1692036SN/A const LaneData<LaneSize::EightByte>& val) = 0; 1702036SN/A /** @} */ 1712036SN/A 1722036SN/A /** Vector Elem Interfaces. */ 1732036SN/A /** @{ */ 1742036SN/A /** Reads an element of a vector register. */ 1752036SN/A virtual VecElem readVecElemOperand(const StaticInst *si, 1762036SN/A int idx) const = 0; 177 178 /** Sets a vector register to a value. */ 179 virtual void setVecElemOperand(const StaticInst *si, int idx, 180 const VecElem val) = 0; 181 /** @} */ 182 183 /** 184 * @{ 185 * @name Condition Code Registers 186 */ 187 virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0; 188 virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0; 189 /** @} */ 190 191 /** 192 * @{ 193 * @name Misc Register Interfaces 194 */ 195 virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0; 196 virtual void setMiscRegOperand(const StaticInst *si, 197 int idx, const MiscReg &val) = 0; 198 199 /** 200 * Reads a miscellaneous register, handling any architectural 201 * side effects due to reading that register. 202 */ 203 virtual MiscReg readMiscReg(int misc_reg) = 0; 204 205 /** 206 * Sets a miscellaneous register, handling any architectural 207 * side effects due to writing that register. 208 */ 209 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 210 211 /** @} */ 212 213 /** 214 * @{ 215 * @name PC Control 216 */ 217 virtual PCState pcState() const = 0; 218 virtual void pcState(const PCState &val) = 0; 219 /** @} */ 220 221 /** 222 * @{ 223 * @name Memory Interface 224 */ 225 /** 226 * Perform an atomic memory read operation. Must be overridden 227 * for exec contexts that support atomic memory mode. Not pure 228 * virtual since exec contexts that only support timing memory 229 * mode need not override (though in that case this function 230 * should never be called). 231 */ 232 virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size, 233 Request::Flags flags) 234 { 235 panic("ExecContext::readMem() should be overridden\n"); 236 } 237 238 /** 239 * Initiate a timing memory read operation. Must be overridden 240 * for exec contexts that support timing memory mode. Not pure 241 * virtual since exec contexts that only support atomic memory 242 * mode need not override (though in that case this function 243 * should never be called). 244 */ 245 virtual Fault initiateMemRead(Addr addr, unsigned int size, 246 Request::Flags flags) 247 { 248 panic("ExecContext::initiateMemRead() should be overridden\n"); 249 } 250 251 /** 252 * For atomic-mode contexts, perform an atomic memory write operation. 253 * For timing-mode contexts, initiate a timing memory write operation. 254 */ 255 virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr, 256 Request::Flags flags, uint64_t *res) = 0; 257 258 /** 259 * Sets the number of consecutive store conditional failures. 260 */ 261 virtual void setStCondFailures(unsigned int sc_failures) = 0; 262 263 /** 264 * Returns the number of consecutive store conditional failures. 265 */ 266 virtual unsigned int readStCondFailures() const = 0; 267 268 /** @} */ 269 270 /** 271 * @{ 272 * @name SysCall Emulation Interfaces 273 */ 274 275 /** 276 * Executes a syscall specified by the callnum. 277 */ 278 virtual void syscall(int64_t callnum, Fault *fault) = 0; 279 280 /** @} */ 281 282 /** Returns a pointer to the ThreadContext. */ 283 virtual ThreadContext *tcBase() = 0; 284 285 /** 286 * @{ 287 * @name Alpha-Specific Interfaces 288 */ 289 290 /** 291 * Somewhat Alpha-specific function that handles returning from an 292 * error or interrupt. 293 */ 294 virtual Fault hwrei() = 0; 295 296 /** 297 * Check for special simulator handling of specific PAL calls. If 298 * return value is false, actual PAL call will be suppressed. 299 */ 300 virtual bool simPalCheck(int palFunc) = 0; 301 302 /** @} */ 303 304 /** 305 * @{ 306 * @name ARM-Specific Interfaces 307 */ 308 309 virtual bool readPredicate() const = 0; 310 virtual void setPredicate(bool val) = 0; 311 312 /** @} */ 313 314 /** 315 * @{ 316 * @name X86-Specific Interfaces 317 */ 318 319 /** 320 * Invalidate a page in the DTLB <i>and</i> ITLB. 321 */ 322 virtual void demapPage(Addr vaddr, uint64_t asn) = 0; 323 virtual void armMonitor(Addr address) = 0; 324 virtual bool mwait(PacketPtr pkt) = 0; 325 virtual void mwaitAtomic(ThreadContext *tc) = 0; 326 virtual AddressMonitor *getAddrMonitor() = 0; 327 328 /** @} */ 329 330 /** 331 * @{ 332 * @name MIPS-Specific Interfaces 333 */ 334 335#if THE_ISA == MIPS_ISA 336 virtual MiscReg readRegOtherThread(const RegId& reg, 337 ThreadID tid = InvalidThreadID) = 0; 338 virtual void setRegOtherThread(const RegId& reg, MiscReg val, 339 ThreadID tid = InvalidThreadID) = 0; 340#endif 341 342 /** @} */ 343}; 344 345#endif // __CPU_EXEC_CONTEXT_HH__ 346