exec_context.hh revision 12104
12735Sktlim@umich.edu/* 210319SAndreas.Sandberg@ARM.com * Copyright (c) 2014 ARM Limited 310319SAndreas.Sandberg@ARM.com * All rights reserved 410319SAndreas.Sandberg@ARM.com * 510319SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 610319SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 710319SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 810319SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 910319SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 1010319SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 1110319SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 1210319SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 1310319SAndreas.Sandberg@ARM.com * 142735Sktlim@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511303Ssteve.reinhardt@amd.com * Copyright (c) 2015 Advanced Micro Devices, Inc. 162735Sktlim@umich.edu * All rights reserved. 172735Sktlim@umich.edu * 182735Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 192735Sktlim@umich.edu * modification, are permitted provided that the following conditions are 202735Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 212735Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 222735Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 232735Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 242735Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 252735Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 262735Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 272735Sktlim@umich.edu * this software without specific prior written permission. 282735Sktlim@umich.edu * 292735Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302735Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312735Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322735Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332735Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342735Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352735Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362735Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372735Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382735Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392735Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402735Sktlim@umich.edu * 412735Sktlim@umich.edu * Authors: Kevin Lim 4210319SAndreas.Sandberg@ARM.com * Andreas Sandberg 432735Sktlim@umich.edu */ 442735Sktlim@umich.edu 4510319SAndreas.Sandberg@ARM.com#ifndef __CPU_EXEC_CONTEXT_HH__ 4610319SAndreas.Sandberg@ARM.com#define __CPU_EXEC_CONTEXT_HH__ 4710319SAndreas.Sandberg@ARM.com 4810319SAndreas.Sandberg@ARM.com#include "arch/registers.hh" 4910319SAndreas.Sandberg@ARM.com#include "base/types.hh" 5010319SAndreas.Sandberg@ARM.com#include "config/the_isa.hh" 5110529Smorr@cs.wisc.edu#include "cpu/base.hh" 5212104Snathanael.premillieu@arm.com#include "cpu/reg_class.hh" 5310319SAndreas.Sandberg@ARM.com#include "cpu/static_inst_fwd.hh" 5410319SAndreas.Sandberg@ARM.com#include "cpu/translation.hh" 5511608Snikos.nikoleris@arm.com#include "mem/request.hh" 562735Sktlim@umich.edu 572735Sktlim@umich.edu/** 5810319SAndreas.Sandberg@ARM.com * The ExecContext is an abstract base class the provides the 5910319SAndreas.Sandberg@ARM.com * interface used by the ISA to manipulate the state of the CPU model. 6010319SAndreas.Sandberg@ARM.com * 6110319SAndreas.Sandberg@ARM.com * Register accessor methods in this class typically provide the index 6210319SAndreas.Sandberg@ARM.com * of the instruction's operand (e.g., 0 or 1), not the architectural 6310319SAndreas.Sandberg@ARM.com * register index, to simplify the implementation of register 6410319SAndreas.Sandberg@ARM.com * renaming. The architectural register index can be found by 6510319SAndreas.Sandberg@ARM.com * indexing into the instruction's own operand index table. 6610319SAndreas.Sandberg@ARM.com * 6710319SAndreas.Sandberg@ARM.com * @note The methods in this class typically take a raw pointer to the 6810319SAndreas.Sandberg@ARM.com * StaticInst is provided instead of a ref-counted StaticInstPtr to 6910319SAndreas.Sandberg@ARM.com * reduce overhead as an argument. This is fine as long as the 7010319SAndreas.Sandberg@ARM.com * implementation doesn't copy the pointer into any long-term storage 7110319SAndreas.Sandberg@ARM.com * (which is pretty hard to imagine they would have reason to do). 722735Sktlim@umich.edu */ 732735Sktlim@umich.educlass ExecContext { 7410319SAndreas.Sandberg@ARM.com public: 7510319SAndreas.Sandberg@ARM.com typedef TheISA::IntReg IntReg; 7610319SAndreas.Sandberg@ARM.com typedef TheISA::PCState PCState; 7710319SAndreas.Sandberg@ARM.com typedef TheISA::FloatReg FloatReg; 7810319SAndreas.Sandberg@ARM.com typedef TheISA::FloatRegBits FloatRegBits; 7910319SAndreas.Sandberg@ARM.com typedef TheISA::MiscReg MiscReg; 8010319SAndreas.Sandberg@ARM.com 8110319SAndreas.Sandberg@ARM.com typedef TheISA::CCReg CCReg; 8210319SAndreas.Sandberg@ARM.com 8310319SAndreas.Sandberg@ARM.com public: 8410319SAndreas.Sandberg@ARM.com /** 8510319SAndreas.Sandberg@ARM.com * @{ 8610319SAndreas.Sandberg@ARM.com * @name Integer Register Interfaces 8710319SAndreas.Sandberg@ARM.com * 8810319SAndreas.Sandberg@ARM.com */ 892735Sktlim@umich.edu 902735Sktlim@umich.edu /** Reads an integer register. */ 9110319SAndreas.Sandberg@ARM.com virtual IntReg readIntRegOperand(const StaticInst *si, int idx) = 0; 9210319SAndreas.Sandberg@ARM.com 9310319SAndreas.Sandberg@ARM.com /** Sets an integer register to a value. */ 9410319SAndreas.Sandberg@ARM.com virtual void setIntRegOperand(const StaticInst *si, 9510319SAndreas.Sandberg@ARM.com int idx, IntReg val) = 0; 9610319SAndreas.Sandberg@ARM.com 9710319SAndreas.Sandberg@ARM.com /** @} */ 9810319SAndreas.Sandberg@ARM.com 9910319SAndreas.Sandberg@ARM.com 10010319SAndreas.Sandberg@ARM.com /** 10110319SAndreas.Sandberg@ARM.com * @{ 10210319SAndreas.Sandberg@ARM.com * @name Floating Point Register Interfaces 10310319SAndreas.Sandberg@ARM.com */ 1042735Sktlim@umich.edu 1052735Sktlim@umich.edu /** Reads a floating point register of single register width. */ 10610319SAndreas.Sandberg@ARM.com virtual FloatReg readFloatRegOperand(const StaticInst *si, int idx) = 0; 1072735Sktlim@umich.edu 1082735Sktlim@umich.edu /** Reads a floating point register in its binary format, instead 1092735Sktlim@umich.edu * of by value. */ 11010319SAndreas.Sandberg@ARM.com virtual FloatRegBits readFloatRegOperandBits(const StaticInst *si, 11110319SAndreas.Sandberg@ARM.com int idx) = 0; 1122735Sktlim@umich.edu 1132735Sktlim@umich.edu /** Sets a floating point register of single width to a value. */ 11410319SAndreas.Sandberg@ARM.com virtual void setFloatRegOperand(const StaticInst *si, 11510319SAndreas.Sandberg@ARM.com int idx, FloatReg val) = 0; 1162735Sktlim@umich.edu 1172735Sktlim@umich.edu /** Sets the bits of a floating point register of single width 1182735Sktlim@umich.edu * to a binary value. */ 11910319SAndreas.Sandberg@ARM.com virtual void setFloatRegOperandBits(const StaticInst *si, 12010319SAndreas.Sandberg@ARM.com int idx, FloatRegBits val) = 0; 1212735Sktlim@umich.edu 12210319SAndreas.Sandberg@ARM.com /** @} */ 1232735Sktlim@umich.edu 12410319SAndreas.Sandberg@ARM.com /** 12510319SAndreas.Sandberg@ARM.com * @{ 12610319SAndreas.Sandberg@ARM.com * @name Condition Code Registers 12710319SAndreas.Sandberg@ARM.com */ 12810319SAndreas.Sandberg@ARM.com virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0; 12910319SAndreas.Sandberg@ARM.com virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0; 13010319SAndreas.Sandberg@ARM.com /** @} */ 1312735Sktlim@umich.edu 13210319SAndreas.Sandberg@ARM.com /** 13310319SAndreas.Sandberg@ARM.com * @{ 13410319SAndreas.Sandberg@ARM.com * @name Misc Register Interfaces 13510319SAndreas.Sandberg@ARM.com */ 13610319SAndreas.Sandberg@ARM.com virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0; 13710319SAndreas.Sandberg@ARM.com virtual void setMiscRegOperand(const StaticInst *si, 13810319SAndreas.Sandberg@ARM.com int idx, const MiscReg &val) = 0; 1392735Sktlim@umich.edu 14010319SAndreas.Sandberg@ARM.com /** 14110319SAndreas.Sandberg@ARM.com * Reads a miscellaneous register, handling any architectural 14210319SAndreas.Sandberg@ARM.com * side effects due to reading that register. 14310319SAndreas.Sandberg@ARM.com */ 14410319SAndreas.Sandberg@ARM.com virtual MiscReg readMiscReg(int misc_reg) = 0; 1452735Sktlim@umich.edu 14610319SAndreas.Sandberg@ARM.com /** 14710319SAndreas.Sandberg@ARM.com * Sets a miscellaneous register, handling any architectural 14810319SAndreas.Sandberg@ARM.com * side effects due to writing that register. 14910319SAndreas.Sandberg@ARM.com */ 15010319SAndreas.Sandberg@ARM.com virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 1512735Sktlim@umich.edu 15210319SAndreas.Sandberg@ARM.com /** @} */ 1532735Sktlim@umich.edu 15410319SAndreas.Sandberg@ARM.com /** 15510319SAndreas.Sandberg@ARM.com * @{ 15610319SAndreas.Sandberg@ARM.com * @name PC Control 15710319SAndreas.Sandberg@ARM.com */ 15810319SAndreas.Sandberg@ARM.com virtual PCState pcState() const = 0; 15910319SAndreas.Sandberg@ARM.com virtual void pcState(const PCState &val) = 0; 16010319SAndreas.Sandberg@ARM.com /** @} */ 16110319SAndreas.Sandberg@ARM.com 16210319SAndreas.Sandberg@ARM.com /** 16310319SAndreas.Sandberg@ARM.com * @{ 16410319SAndreas.Sandberg@ARM.com * @name Memory Interface 16510319SAndreas.Sandberg@ARM.com */ 16610319SAndreas.Sandberg@ARM.com /** 16710319SAndreas.Sandberg@ARM.com * Record the effective address of the instruction. 16810319SAndreas.Sandberg@ARM.com * 16910319SAndreas.Sandberg@ARM.com * @note Only valid for memory ops. 17010319SAndreas.Sandberg@ARM.com */ 17110319SAndreas.Sandberg@ARM.com virtual void setEA(Addr EA) = 0; 17210319SAndreas.Sandberg@ARM.com /** 17310319SAndreas.Sandberg@ARM.com * Get the effective address of the instruction. 17410319SAndreas.Sandberg@ARM.com * 17510319SAndreas.Sandberg@ARM.com * @note Only valid for memory ops. 17610319SAndreas.Sandberg@ARM.com */ 17710319SAndreas.Sandberg@ARM.com virtual Addr getEA() const = 0; 17810319SAndreas.Sandberg@ARM.com 17911303Ssteve.reinhardt@amd.com /** 18011303Ssteve.reinhardt@amd.com * Perform an atomic memory read operation. Must be overridden 18111303Ssteve.reinhardt@amd.com * for exec contexts that support atomic memory mode. Not pure 18211303Ssteve.reinhardt@amd.com * virtual since exec contexts that only support timing memory 18311303Ssteve.reinhardt@amd.com * mode need not override (though in that case this function 18411303Ssteve.reinhardt@amd.com * should never be called). 18511303Ssteve.reinhardt@amd.com */ 18610319SAndreas.Sandberg@ARM.com virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size, 18711608Snikos.nikoleris@arm.com Request::Flags flags) 18811303Ssteve.reinhardt@amd.com { 18911303Ssteve.reinhardt@amd.com panic("ExecContext::readMem() should be overridden\n"); 19011303Ssteve.reinhardt@amd.com } 19110319SAndreas.Sandberg@ARM.com 19211303Ssteve.reinhardt@amd.com /** 19311303Ssteve.reinhardt@amd.com * Initiate a timing memory read operation. Must be overridden 19411303Ssteve.reinhardt@amd.com * for exec contexts that support timing memory mode. Not pure 19511303Ssteve.reinhardt@amd.com * virtual since exec contexts that only support atomic memory 19611303Ssteve.reinhardt@amd.com * mode need not override (though in that case this function 19711303Ssteve.reinhardt@amd.com * should never be called). 19811303Ssteve.reinhardt@amd.com */ 19911303Ssteve.reinhardt@amd.com virtual Fault initiateMemRead(Addr addr, unsigned int size, 20011608Snikos.nikoleris@arm.com Request::Flags flags) 20111303Ssteve.reinhardt@amd.com { 20211303Ssteve.reinhardt@amd.com panic("ExecContext::initiateMemRead() should be overridden\n"); 20311303Ssteve.reinhardt@amd.com } 20411303Ssteve.reinhardt@amd.com 20511303Ssteve.reinhardt@amd.com /** 20611303Ssteve.reinhardt@amd.com * For atomic-mode contexts, perform an atomic memory write operation. 20711303Ssteve.reinhardt@amd.com * For timing-mode contexts, initiate a timing memory write operation. 20811303Ssteve.reinhardt@amd.com */ 20910319SAndreas.Sandberg@ARM.com virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr, 21011608Snikos.nikoleris@arm.com Request::Flags flags, uint64_t *res) = 0; 21110319SAndreas.Sandberg@ARM.com 21210319SAndreas.Sandberg@ARM.com /** 21310319SAndreas.Sandberg@ARM.com * Sets the number of consecutive store conditional failures. 21410319SAndreas.Sandberg@ARM.com */ 21510319SAndreas.Sandberg@ARM.com virtual void setStCondFailures(unsigned int sc_failures) = 0; 21610319SAndreas.Sandberg@ARM.com 21710319SAndreas.Sandberg@ARM.com /** 21810319SAndreas.Sandberg@ARM.com * Returns the number of consecutive store conditional failures. 21910319SAndreas.Sandberg@ARM.com */ 22010319SAndreas.Sandberg@ARM.com virtual unsigned int readStCondFailures() const = 0; 22110319SAndreas.Sandberg@ARM.com 22210319SAndreas.Sandberg@ARM.com /** @} */ 22310319SAndreas.Sandberg@ARM.com 22410319SAndreas.Sandberg@ARM.com /** 22510319SAndreas.Sandberg@ARM.com * @{ 22610319SAndreas.Sandberg@ARM.com * @name SysCall Emulation Interfaces 22710319SAndreas.Sandberg@ARM.com */ 22810319SAndreas.Sandberg@ARM.com 22910319SAndreas.Sandberg@ARM.com /** 23010319SAndreas.Sandberg@ARM.com * Executes a syscall specified by the callnum. 23110319SAndreas.Sandberg@ARM.com */ 23211877Sbrandon.potter@amd.com virtual void syscall(int64_t callnum, Fault *fault) = 0; 23310319SAndreas.Sandberg@ARM.com 23410319SAndreas.Sandberg@ARM.com /** @} */ 2352735Sktlim@umich.edu 2362735Sktlim@umich.edu /** Returns a pointer to the ThreadContext. */ 23710319SAndreas.Sandberg@ARM.com virtual ThreadContext *tcBase() = 0; 2382735Sktlim@umich.edu 23910319SAndreas.Sandberg@ARM.com /** 24010319SAndreas.Sandberg@ARM.com * @{ 24110319SAndreas.Sandberg@ARM.com * @name Alpha-Specific Interfaces 24210319SAndreas.Sandberg@ARM.com */ 2437520Sgblack@eecs.umich.edu 24410319SAndreas.Sandberg@ARM.com /** 24510319SAndreas.Sandberg@ARM.com * Somewhat Alpha-specific function that handles returning from an 24610319SAndreas.Sandberg@ARM.com * error or interrupt. 24710319SAndreas.Sandberg@ARM.com */ 24810319SAndreas.Sandberg@ARM.com virtual Fault hwrei() = 0; 2495702Ssaidi@eecs.umich.edu 2505702Ssaidi@eecs.umich.edu /** 2515702Ssaidi@eecs.umich.edu * Check for special simulator handling of specific PAL calls. If 2525702Ssaidi@eecs.umich.edu * return value is false, actual PAL call will be suppressed. 2535702Ssaidi@eecs.umich.edu */ 25410319SAndreas.Sandberg@ARM.com virtual bool simPalCheck(int palFunc) = 0; 2558779Sgblack@eecs.umich.edu 25610319SAndreas.Sandberg@ARM.com /** @} */ 2576973Stjones1@inf.ed.ac.uk 25810319SAndreas.Sandberg@ARM.com /** 25910319SAndreas.Sandberg@ARM.com * @{ 26010319SAndreas.Sandberg@ARM.com * @name ARM-Specific Interfaces 26110319SAndreas.Sandberg@ARM.com */ 26210319SAndreas.Sandberg@ARM.com 26310319SAndreas.Sandberg@ARM.com virtual bool readPredicate() = 0; 26410319SAndreas.Sandberg@ARM.com virtual void setPredicate(bool val) = 0; 26510319SAndreas.Sandberg@ARM.com 26610319SAndreas.Sandberg@ARM.com /** @} */ 26710319SAndreas.Sandberg@ARM.com 26810319SAndreas.Sandberg@ARM.com /** 26910319SAndreas.Sandberg@ARM.com * @{ 27010319SAndreas.Sandberg@ARM.com * @name X86-Specific Interfaces 27110319SAndreas.Sandberg@ARM.com */ 27210319SAndreas.Sandberg@ARM.com 27310319SAndreas.Sandberg@ARM.com /** 27410319SAndreas.Sandberg@ARM.com * Invalidate a page in the DTLB <i>and</i> ITLB. 27510319SAndreas.Sandberg@ARM.com */ 27610319SAndreas.Sandberg@ARM.com virtual void demapPage(Addr vaddr, uint64_t asn) = 0; 27710529Smorr@cs.wisc.edu virtual void armMonitor(Addr address) = 0; 27810529Smorr@cs.wisc.edu virtual bool mwait(PacketPtr pkt) = 0; 27910529Smorr@cs.wisc.edu virtual void mwaitAtomic(ThreadContext *tc) = 0; 28010529Smorr@cs.wisc.edu virtual AddressMonitor *getAddrMonitor() = 0; 28110319SAndreas.Sandberg@ARM.com 28210319SAndreas.Sandberg@ARM.com /** @} */ 28310319SAndreas.Sandberg@ARM.com 28410319SAndreas.Sandberg@ARM.com /** 28510319SAndreas.Sandberg@ARM.com * @{ 28610319SAndreas.Sandberg@ARM.com * @name MIPS-Specific Interfaces 28710319SAndreas.Sandberg@ARM.com */ 28810319SAndreas.Sandberg@ARM.com 28910319SAndreas.Sandberg@ARM.com#if THE_ISA == MIPS_ISA 29012104Snathanael.premillieu@arm.com virtual MiscReg readRegOtherThread(RegId reg, 29110319SAndreas.Sandberg@ARM.com ThreadID tid = InvalidThreadID) = 0; 29212104Snathanael.premillieu@arm.com virtual void setRegOtherThread(RegId reg, MiscReg val, 29310319SAndreas.Sandberg@ARM.com ThreadID tid = InvalidThreadID) = 0; 29410319SAndreas.Sandberg@ARM.com#endif 29510319SAndreas.Sandberg@ARM.com 29610319SAndreas.Sandberg@ARM.com /** @} */ 2972735Sktlim@umich.edu}; 29810319SAndreas.Sandberg@ARM.com 29910319SAndreas.Sandberg@ARM.com#endif // __CPU_EXEC_CONTEXT_HH__ 300