exec_context.hh revision 11877
12735Sktlim@umich.edu/* 22735Sktlim@umich.edu * Copyright (c) 2014 ARM Limited 32735Sktlim@umich.edu * All rights reserved 42735Sktlim@umich.edu * 52735Sktlim@umich.edu * The license below extends only to copyright in the software and shall 62735Sktlim@umich.edu * not be construed as granting a license to any other intellectual 72735Sktlim@umich.edu * property including but not limited to intellectual property relating 82735Sktlim@umich.edu * to a hardware implementation of the functionality of the software 92735Sktlim@umich.edu * licensed hereunder. You may use the software subject to the license 102735Sktlim@umich.edu * terms below provided that you ensure that this notice is replicated 112735Sktlim@umich.edu * unmodified and in its entirety in all distributions of the software, 122735Sktlim@umich.edu * modified or unmodified, in source code or in binary form. 132735Sktlim@umich.edu * 142735Sktlim@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 152735Sktlim@umich.edu * Copyright (c) 2015 Advanced Micro Devices, Inc. 162735Sktlim@umich.edu * All rights reserved. 172735Sktlim@umich.edu * 182735Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 192735Sktlim@umich.edu * modification, are permitted provided that the following conditions are 202735Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 212735Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 222735Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 232735Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 242735Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 252735Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 262735Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 272735Sktlim@umich.edu * this software without specific prior written permission. 282735Sktlim@umich.edu * 292735Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302735Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312735Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322735Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332735Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342735Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352735Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362735Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372735Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382735Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392735Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402735Sktlim@umich.edu * 412735Sktlim@umich.edu * Authors: Kevin Lim 422735Sktlim@umich.edu * Andreas Sandberg 432735Sktlim@umich.edu */ 442735Sktlim@umich.edu 452735Sktlim@umich.edu#ifndef __CPU_EXEC_CONTEXT_HH__ 462735Sktlim@umich.edu#define __CPU_EXEC_CONTEXT_HH__ 472735Sktlim@umich.edu 482735Sktlim@umich.edu#include "arch/registers.hh" 492735Sktlim@umich.edu#include "base/types.hh" 502735Sktlim@umich.edu#include "config/the_isa.hh" 512735Sktlim@umich.edu#include "cpu/base.hh" 522735Sktlim@umich.edu#include "cpu/static_inst_fwd.hh" 532735Sktlim@umich.edu#include "cpu/translation.hh" 542735Sktlim@umich.edu#include "mem/request.hh" 552735Sktlim@umich.edu 562735Sktlim@umich.edu/** 572735Sktlim@umich.edu * The ExecContext is an abstract base class the provides the 582735Sktlim@umich.edu * interface used by the ISA to manipulate the state of the CPU model. 592735Sktlim@umich.edu * 602735Sktlim@umich.edu * Register accessor methods in this class typically provide the index 612735Sktlim@umich.edu * of the instruction's operand (e.g., 0 or 1), not the architectural 622735Sktlim@umich.edu * register index, to simplify the implementation of register 632735Sktlim@umich.edu * renaming. The architectural register index can be found by 642735Sktlim@umich.edu * indexing into the instruction's own operand index table. 652735Sktlim@umich.edu * 662735Sktlim@umich.edu * @note The methods in this class typically take a raw pointer to the 672735Sktlim@umich.edu * StaticInst is provided instead of a ref-counted StaticInstPtr to 682735Sktlim@umich.edu * reduce overhead as an argument. This is fine as long as the 692735Sktlim@umich.edu * implementation doesn't copy the pointer into any long-term storage 702735Sktlim@umich.edu * (which is pretty hard to imagine they would have reason to do). 712735Sktlim@umich.edu */ 722735Sktlim@umich.educlass ExecContext { 732735Sktlim@umich.edu public: 742735Sktlim@umich.edu typedef TheISA::IntReg IntReg; 752735Sktlim@umich.edu typedef TheISA::PCState PCState; 762735Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 772735Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 782735Sktlim@umich.edu typedef TheISA::MiscReg MiscReg; 792735Sktlim@umich.edu 802735Sktlim@umich.edu typedef TheISA::CCReg CCReg; 812735Sktlim@umich.edu 822735Sktlim@umich.edu public: 832735Sktlim@umich.edu /** 842735Sktlim@umich.edu * @{ 852735Sktlim@umich.edu * @name Integer Register Interfaces 862735Sktlim@umich.edu * 872735Sktlim@umich.edu */ 882735Sktlim@umich.edu 892735Sktlim@umich.edu /** Reads an integer register. */ 902735Sktlim@umich.edu virtual IntReg readIntRegOperand(const StaticInst *si, int idx) = 0; 912735Sktlim@umich.edu 922735Sktlim@umich.edu /** Sets an integer register to a value. */ 932735Sktlim@umich.edu virtual void setIntRegOperand(const StaticInst *si, 942735Sktlim@umich.edu int idx, IntReg val) = 0; 952735Sktlim@umich.edu 962735Sktlim@umich.edu /** @} */ 972735Sktlim@umich.edu 982735Sktlim@umich.edu 992735Sktlim@umich.edu /** 1002735Sktlim@umich.edu * @{ 1012735Sktlim@umich.edu * @name Floating Point Register Interfaces 1022735Sktlim@umich.edu */ 1032735Sktlim@umich.edu 1042735Sktlim@umich.edu /** Reads a floating point register of single register width. */ 1052735Sktlim@umich.edu virtual FloatReg readFloatRegOperand(const StaticInst *si, int idx) = 0; 1062735Sktlim@umich.edu 1072735Sktlim@umich.edu /** Reads a floating point register in its binary format, instead 1082735Sktlim@umich.edu * of by value. */ 1092735Sktlim@umich.edu virtual FloatRegBits readFloatRegOperandBits(const StaticInst *si, 1102735Sktlim@umich.edu int idx) = 0; 1112735Sktlim@umich.edu 1122735Sktlim@umich.edu /** Sets a floating point register of single width to a value. */ 1132735Sktlim@umich.edu virtual void setFloatRegOperand(const StaticInst *si, 1142735Sktlim@umich.edu int idx, FloatReg val) = 0; 1152735Sktlim@umich.edu 1162735Sktlim@umich.edu /** Sets the bits of a floating point register of single width 1172735Sktlim@umich.edu * to a binary value. */ 1182735Sktlim@umich.edu virtual void setFloatRegOperandBits(const StaticInst *si, 1192735Sktlim@umich.edu int idx, FloatRegBits val) = 0; 1202735Sktlim@umich.edu 1212735Sktlim@umich.edu /** @} */ 1222735Sktlim@umich.edu 1232735Sktlim@umich.edu /** 1242735Sktlim@umich.edu * @{ 1252735Sktlim@umich.edu * @name Condition Code Registers 1262735Sktlim@umich.edu */ 1272735Sktlim@umich.edu virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0; 1282735Sktlim@umich.edu virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0; 1292735Sktlim@umich.edu /** @} */ 1302735Sktlim@umich.edu 1312735Sktlim@umich.edu /** 1322735Sktlim@umich.edu * @{ 1332735Sktlim@umich.edu * @name Misc Register Interfaces 1342735Sktlim@umich.edu */ 1352735Sktlim@umich.edu virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0; 1362735Sktlim@umich.edu virtual void setMiscRegOperand(const StaticInst *si, 1372735Sktlim@umich.edu int idx, const MiscReg &val) = 0; 1382735Sktlim@umich.edu 1392735Sktlim@umich.edu /** 1402735Sktlim@umich.edu * Reads a miscellaneous register, handling any architectural 1412735Sktlim@umich.edu * side effects due to reading that register. 1422735Sktlim@umich.edu */ 1432735Sktlim@umich.edu virtual MiscReg readMiscReg(int misc_reg) = 0; 1442735Sktlim@umich.edu 1452735Sktlim@umich.edu /** 1462735Sktlim@umich.edu * Sets a miscellaneous register, handling any architectural 1472735Sktlim@umich.edu * side effects due to writing that register. 1482735Sktlim@umich.edu */ 1492735Sktlim@umich.edu virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 1502735Sktlim@umich.edu 1512735Sktlim@umich.edu /** @} */ 1522735Sktlim@umich.edu 1532735Sktlim@umich.edu /** 1542735Sktlim@umich.edu * @{ 1552735Sktlim@umich.edu * @name PC Control 1562735Sktlim@umich.edu */ 1572735Sktlim@umich.edu virtual PCState pcState() const = 0; 1582735Sktlim@umich.edu virtual void pcState(const PCState &val) = 0; 1592735Sktlim@umich.edu /** @} */ 1602735Sktlim@umich.edu 1612735Sktlim@umich.edu /** 162 * @{ 163 * @name Memory Interface 164 */ 165 /** 166 * Record the effective address of the instruction. 167 * 168 * @note Only valid for memory ops. 169 */ 170 virtual void setEA(Addr EA) = 0; 171 /** 172 * Get the effective address of the instruction. 173 * 174 * @note Only valid for memory ops. 175 */ 176 virtual Addr getEA() const = 0; 177 178 /** 179 * Perform an atomic memory read operation. Must be overridden 180 * for exec contexts that support atomic memory mode. Not pure 181 * virtual since exec contexts that only support timing memory 182 * mode need not override (though in that case this function 183 * should never be called). 184 */ 185 virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size, 186 Request::Flags flags) 187 { 188 panic("ExecContext::readMem() should be overridden\n"); 189 } 190 191 /** 192 * Initiate a timing memory read operation. Must be overridden 193 * for exec contexts that support timing memory mode. Not pure 194 * virtual since exec contexts that only support atomic memory 195 * mode need not override (though in that case this function 196 * should never be called). 197 */ 198 virtual Fault initiateMemRead(Addr addr, unsigned int size, 199 Request::Flags flags) 200 { 201 panic("ExecContext::initiateMemRead() should be overridden\n"); 202 } 203 204 /** 205 * For atomic-mode contexts, perform an atomic memory write operation. 206 * For timing-mode contexts, initiate a timing memory write operation. 207 */ 208 virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr, 209 Request::Flags flags, uint64_t *res) = 0; 210 211 /** 212 * Sets the number of consecutive store conditional failures. 213 */ 214 virtual void setStCondFailures(unsigned int sc_failures) = 0; 215 216 /** 217 * Returns the number of consecutive store conditional failures. 218 */ 219 virtual unsigned int readStCondFailures() const = 0; 220 221 /** @} */ 222 223 /** 224 * @{ 225 * @name SysCall Emulation Interfaces 226 */ 227 228 /** 229 * Executes a syscall specified by the callnum. 230 */ 231 virtual void syscall(int64_t callnum, Fault *fault) = 0; 232 233 /** @} */ 234 235 /** Returns a pointer to the ThreadContext. */ 236 virtual ThreadContext *tcBase() = 0; 237 238 /** 239 * @{ 240 * @name Alpha-Specific Interfaces 241 */ 242 243 /** 244 * Somewhat Alpha-specific function that handles returning from an 245 * error or interrupt. 246 */ 247 virtual Fault hwrei() = 0; 248 249 /** 250 * Check for special simulator handling of specific PAL calls. If 251 * return value is false, actual PAL call will be suppressed. 252 */ 253 virtual bool simPalCheck(int palFunc) = 0; 254 255 /** @} */ 256 257 /** 258 * @{ 259 * @name ARM-Specific Interfaces 260 */ 261 262 virtual bool readPredicate() = 0; 263 virtual void setPredicate(bool val) = 0; 264 265 /** @} */ 266 267 /** 268 * @{ 269 * @name X86-Specific Interfaces 270 */ 271 272 /** 273 * Invalidate a page in the DTLB <i>and</i> ITLB. 274 */ 275 virtual void demapPage(Addr vaddr, uint64_t asn) = 0; 276 virtual void armMonitor(Addr address) = 0; 277 virtual bool mwait(PacketPtr pkt) = 0; 278 virtual void mwaitAtomic(ThreadContext *tc) = 0; 279 virtual AddressMonitor *getAddrMonitor() = 0; 280 281 /** @} */ 282 283 /** 284 * @{ 285 * @name MIPS-Specific Interfaces 286 */ 287 288#if THE_ISA == MIPS_ISA 289 virtual MiscReg readRegOtherThread(int regIdx, 290 ThreadID tid = InvalidThreadID) = 0; 291 virtual void setRegOtherThread(int regIdx, MiscReg val, 292 ThreadID tid = InvalidThreadID) = 0; 293#endif 294 295 /** @} */ 296}; 297 298#endif // __CPU_EXEC_CONTEXT_HH__ 299