exec_context.hh revision 11608
18541Sgblack@eecs.umich.edu/* 28541Sgblack@eecs.umich.edu * Copyright (c) 2014 ARM Limited 38541Sgblack@eecs.umich.edu * All rights reserved 48541Sgblack@eecs.umich.edu * 58541Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 68541Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 78541Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 88541Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 98541Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 108541Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 118541Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 128541Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 138541Sgblack@eecs.umich.edu * 148541Sgblack@eecs.umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 158541Sgblack@eecs.umich.edu * Copyright (c) 2015 Advanced Micro Devices, Inc. 168541Sgblack@eecs.umich.edu * All rights reserved. 178541Sgblack@eecs.umich.edu * 188541Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 198541Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 208541Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 218541Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 228541Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 238541Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 248541Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 258541Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 268541Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 278541Sgblack@eecs.umich.edu * this software without specific prior written permission. 288541Sgblack@eecs.umich.edu * 298541Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 308541Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 318541Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 328541Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 338541Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3411168Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3511168Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 368541Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 378541Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 388541Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 399024Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 408541Sgblack@eecs.umich.edu * 419022Sgblack@eecs.umich.edu * Authors: Kevin Lim 429022Sgblack@eecs.umich.edu * Andreas Sandberg 439022Sgblack@eecs.umich.edu */ 449022Sgblack@eecs.umich.edu 458541Sgblack@eecs.umich.edu#ifndef __CPU_EXEC_CONTEXT_HH__ 469024Sgblack@eecs.umich.edu#define __CPU_EXEC_CONTEXT_HH__ 478541Sgblack@eecs.umich.edu 488541Sgblack@eecs.umich.edu#include "arch/registers.hh" 499024Sgblack@eecs.umich.edu#include "base/types.hh" 5012621Sgabeblack@google.com#include "config/the_isa.hh" 5112621Sgabeblack@google.com#include "cpu/base.hh" 529024Sgblack@eecs.umich.edu#include "cpu/static_inst_fwd.hh" 539024Sgblack@eecs.umich.edu#include "cpu/translation.hh" 549024Sgblack@eecs.umich.edu#include "mem/request.hh" 559024Sgblack@eecs.umich.edu 569024Sgblack@eecs.umich.edu/** 579024Sgblack@eecs.umich.edu * The ExecContext is an abstract base class the provides the 589024Sgblack@eecs.umich.edu * interface used by the ISA to manipulate the state of the CPU model. 599024Sgblack@eecs.umich.edu * 609024Sgblack@eecs.umich.edu * Register accessor methods in this class typically provide the index 618541Sgblack@eecs.umich.edu * of the instruction's operand (e.g., 0 or 1), not the architectural 629024Sgblack@eecs.umich.edu * register index, to simplify the implementation of register 6311168Sandreas.hansson@arm.com * renaming. The architectural register index can be found by 649024Sgblack@eecs.umich.edu * indexing into the instruction's own operand index table. 659024Sgblack@eecs.umich.edu * 669024Sgblack@eecs.umich.edu * @note The methods in this class typically take a raw pointer to the 679024Sgblack@eecs.umich.edu * StaticInst is provided instead of a ref-counted StaticInstPtr to 688541Sgblack@eecs.umich.edu * reduce overhead as an argument. This is fine as long as the 699024Sgblack@eecs.umich.edu * implementation doesn't copy the pointer into any long-term storage 709024Sgblack@eecs.umich.edu * (which is pretty hard to imagine they would have reason to do). 719024Sgblack@eecs.umich.edu */ 729024Sgblack@eecs.umich.educlass ExecContext { 738541Sgblack@eecs.umich.edu public: 749024Sgblack@eecs.umich.edu typedef TheISA::IntReg IntReg; 759024Sgblack@eecs.umich.edu typedef TheISA::PCState PCState; 769024Sgblack@eecs.umich.edu typedef TheISA::FloatReg FloatReg; 778541Sgblack@eecs.umich.edu typedef TheISA::FloatRegBits FloatRegBits; 789024Sgblack@eecs.umich.edu typedef TheISA::MiscReg MiscReg; 799024Sgblack@eecs.umich.edu 8011168Sandreas.hansson@arm.com typedef TheISA::CCReg CCReg; 819024Sgblack@eecs.umich.edu 829024Sgblack@eecs.umich.edu public: 839024Sgblack@eecs.umich.edu /** 849024Sgblack@eecs.umich.edu * @{ 859024Sgblack@eecs.umich.edu * @name Integer Register Interfaces 869021Sgblack@eecs.umich.edu * 879024Sgblack@eecs.umich.edu */ 889024Sgblack@eecs.umich.edu 899024Sgblack@eecs.umich.edu /** Reads an integer register. */ 909024Sgblack@eecs.umich.edu virtual IntReg readIntRegOperand(const StaticInst *si, int idx) = 0; 919024Sgblack@eecs.umich.edu 929024Sgblack@eecs.umich.edu /** Sets an integer register to a value. */ 939024Sgblack@eecs.umich.edu virtual void setIntRegOperand(const StaticInst *si, 949024Sgblack@eecs.umich.edu int idx, IntReg val) = 0; 959024Sgblack@eecs.umich.edu 969024Sgblack@eecs.umich.edu /** @} */ 979024Sgblack@eecs.umich.edu 988541Sgblack@eecs.umich.edu 999024Sgblack@eecs.umich.edu /** 1009024Sgblack@eecs.umich.edu * @{ 1019024Sgblack@eecs.umich.edu * @name Floating Point Register Interfaces 1029024Sgblack@eecs.umich.edu */ 1039024Sgblack@eecs.umich.edu 1049024Sgblack@eecs.umich.edu /** Reads a floating point register of single register width. */ 1059024Sgblack@eecs.umich.edu virtual FloatReg readFloatRegOperand(const StaticInst *si, int idx) = 0; 1069024Sgblack@eecs.umich.edu 1079024Sgblack@eecs.umich.edu /** Reads a floating point register in its binary format, instead 1089024Sgblack@eecs.umich.edu * of by value. */ 1099024Sgblack@eecs.umich.edu virtual FloatRegBits readFloatRegOperandBits(const StaticInst *si, 1109024Sgblack@eecs.umich.edu int idx) = 0; 1119024Sgblack@eecs.umich.edu 1129024Sgblack@eecs.umich.edu /** Sets a floating point register of single width to a value. */ 1138541Sgblack@eecs.umich.edu virtual void setFloatRegOperand(const StaticInst *si, 1148541Sgblack@eecs.umich.edu int idx, FloatReg val) = 0; 1159024Sgblack@eecs.umich.edu 1169024Sgblack@eecs.umich.edu /** Sets the bits of a floating point register of single width 1179024Sgblack@eecs.umich.edu * to a binary value. */ 1189024Sgblack@eecs.umich.edu virtual void setFloatRegOperandBits(const StaticInst *si, 1199024Sgblack@eecs.umich.edu int idx, FloatRegBits val) = 0; 1209024Sgblack@eecs.umich.edu 1219024Sgblack@eecs.umich.edu /** @} */ 1229024Sgblack@eecs.umich.edu 1239024Sgblack@eecs.umich.edu /** 1249024Sgblack@eecs.umich.edu * @{ 1259024Sgblack@eecs.umich.edu * @name Condition Code Registers 1269024Sgblack@eecs.umich.edu */ 1278541Sgblack@eecs.umich.edu virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0; 1288541Sgblack@eecs.umich.edu virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0; 1299024Sgblack@eecs.umich.edu /** @} */ 1309024Sgblack@eecs.umich.edu 1318541Sgblack@eecs.umich.edu /** 132 * @{ 133 * @name Misc Register Interfaces 134 */ 135 virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0; 136 virtual void setMiscRegOperand(const StaticInst *si, 137 int idx, const MiscReg &val) = 0; 138 139 /** 140 * Reads a miscellaneous register, handling any architectural 141 * side effects due to reading that register. 142 */ 143 virtual MiscReg readMiscReg(int misc_reg) = 0; 144 145 /** 146 * Sets a miscellaneous register, handling any architectural 147 * side effects due to writing that register. 148 */ 149 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 150 151 /** @} */ 152 153 /** 154 * @{ 155 * @name PC Control 156 */ 157 virtual PCState pcState() const = 0; 158 virtual void pcState(const PCState &val) = 0; 159 /** @} */ 160 161 /** 162 * @{ 163 * @name Memory Interface 164 */ 165 /** 166 * Record the effective address of the instruction. 167 * 168 * @note Only valid for memory ops. 169 */ 170 virtual void setEA(Addr EA) = 0; 171 /** 172 * Get the effective address of the instruction. 173 * 174 * @note Only valid for memory ops. 175 */ 176 virtual Addr getEA() const = 0; 177 178 /** 179 * Perform an atomic memory read operation. Must be overridden 180 * for exec contexts that support atomic memory mode. Not pure 181 * virtual since exec contexts that only support timing memory 182 * mode need not override (though in that case this function 183 * should never be called). 184 */ 185 virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size, 186 Request::Flags flags) 187 { 188 panic("ExecContext::readMem() should be overridden\n"); 189 } 190 191 /** 192 * Initiate a timing memory read operation. Must be overridden 193 * for exec contexts that support timing memory mode. Not pure 194 * virtual since exec contexts that only support atomic memory 195 * mode need not override (though in that case this function 196 * should never be called). 197 */ 198 virtual Fault initiateMemRead(Addr addr, unsigned int size, 199 Request::Flags flags) 200 { 201 panic("ExecContext::initiateMemRead() should be overridden\n"); 202 } 203 204 /** 205 * For atomic-mode contexts, perform an atomic memory write operation. 206 * For timing-mode contexts, initiate a timing memory write operation. 207 */ 208 virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr, 209 Request::Flags flags, uint64_t *res) = 0; 210 211 /** 212 * Sets the number of consecutive store conditional failures. 213 */ 214 virtual void setStCondFailures(unsigned int sc_failures) = 0; 215 216 /** 217 * Returns the number of consecutive store conditional failures. 218 */ 219 virtual unsigned int readStCondFailures() const = 0; 220 221 /** @} */ 222 223 /** 224 * @{ 225 * @name SysCall Emulation Interfaces 226 */ 227 228 /** 229 * Executes a syscall specified by the callnum. 230 */ 231 virtual void syscall(int64_t callnum) = 0; 232 233 /** @} */ 234 235 /** Returns a pointer to the ThreadContext. */ 236 virtual ThreadContext *tcBase() = 0; 237 238 /** 239 * @{ 240 * @name Alpha-Specific Interfaces 241 */ 242 243 /** 244 * Somewhat Alpha-specific function that handles returning from an 245 * error or interrupt. 246 */ 247 virtual Fault hwrei() = 0; 248 249 /** 250 * Check for special simulator handling of specific PAL calls. If 251 * return value is false, actual PAL call will be suppressed. 252 */ 253 virtual bool simPalCheck(int palFunc) = 0; 254 255 /** @} */ 256 257 /** 258 * @{ 259 * @name ARM-Specific Interfaces 260 */ 261 262 virtual bool readPredicate() = 0; 263 virtual void setPredicate(bool val) = 0; 264 265 /** @} */ 266 267 /** 268 * @{ 269 * @name X86-Specific Interfaces 270 */ 271 272 /** 273 * Invalidate a page in the DTLB <i>and</i> ITLB. 274 */ 275 virtual void demapPage(Addr vaddr, uint64_t asn) = 0; 276 virtual void armMonitor(Addr address) = 0; 277 virtual bool mwait(PacketPtr pkt) = 0; 278 virtual void mwaitAtomic(ThreadContext *tc) = 0; 279 virtual AddressMonitor *getAddrMonitor() = 0; 280 281 /** @} */ 282 283 /** 284 * @{ 285 * @name MIPS-Specific Interfaces 286 */ 287 288#if THE_ISA == MIPS_ISA 289 virtual MiscReg readRegOtherThread(int regIdx, 290 ThreadID tid = InvalidThreadID) = 0; 291 virtual void setRegOtherThread(int regIdx, MiscReg val, 292 ThreadID tid = InvalidThreadID) = 0; 293#endif 294 295 /** @} */ 296}; 297 298#endif // __CPU_EXEC_CONTEXT_HH__ 299