exec_context.hh revision 11303
12131SN/A/* 25222Sksewell@umich.edu * Copyright (c) 2014 ARM Limited 32131SN/A * All rights reserved 45222Sksewell@umich.edu * 52131SN/A * The license below extends only to copyright in the software and shall 65222Sksewell@umich.edu * not be construed as granting a license to any other intellectual 75222Sksewell@umich.edu * property including but not limited to intellectual property relating 85222Sksewell@umich.edu * to a hardware implementation of the functionality of the software 92665Ssaidi@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 105222Sksewell@umich.edu * terms below provided that you ensure that this notice is replicated 115222Sksewell@umich.edu * unmodified and in its entirety in all distributions of the software, 125222Sksewell@umich.edu * modified or unmodified, in source code or in binary form. 135222Sksewell@umich.edu * 145222Sksewell@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 155222Sksewell@umich.edu * Copyright (c) 2015 Advanced Micro Devices, Inc. 165222Sksewell@umich.edu * All rights reserved. 175222Sksewell@umich.edu * 185222Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 195222Sksewell@umich.edu * modification, are permitted provided that the following conditions are 205222Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 215222Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 225222Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 235222Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 245222Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 255222Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 265222Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 275222Sksewell@umich.edu * this software without specific prior written permission. 285222Sksewell@umich.edu * 295222Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 305222Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 315222Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 325222Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 335222Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 345222Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 355222Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 365222Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372131SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382131SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392239SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402680Sktlim@umich.edu * 412447SN/A * Authors: Kevin Lim 422447SN/A * Andreas Sandberg 435222Sksewell@umich.edu */ 442800Ssaidi@eecs.umich.edu 452800Ssaidi@eecs.umich.edu#ifndef __CPU_EXEC_CONTEXT_HH__ 462800Ssaidi@eecs.umich.edu#define __CPU_EXEC_CONTEXT_HH__ 472800Ssaidi@eecs.umich.edu 482131SN/A#include "arch/registers.hh" 492447SN/A#include "base/types.hh" 502447SN/A#include "config/the_isa.hh" 512131SN/A#include "cpu/base.hh" 522479SN/A#include "cpu/static_inst_fwd.hh" 532447SN/A#include "cpu/translation.hh" 542447SN/A 552131SN/A/** 562479SN/A * The ExecContext is an abstract base class the provides the 572447SN/A * interface used by the ISA to manipulate the state of the CPU model. 582447SN/A * 592447SN/A * Register accessor methods in this class typically provide the index 605224Sksewell@umich.edu * of the instruction's operand (e.g., 0 or 1), not the architectural 615222Sksewell@umich.edu * register index, to simplify the implementation of register 625222Sksewell@umich.edu * renaming. The architectural register index can be found by 635222Sksewell@umich.edu * indexing into the instruction's own operand index table. 645222Sksewell@umich.edu * 655222Sksewell@umich.edu * @note The methods in this class typically take a raw pointer to the 662447SN/A * StaticInst is provided instead of a ref-counted StaticInstPtr to 672447SN/A * reduce overhead as an argument. This is fine as long as the 685222Sksewell@umich.edu * implementation doesn't copy the pointer into any long-term storage 695222Sksewell@umich.edu * (which is pretty hard to imagine they would have reason to do). 705222Sksewell@umich.edu */ 715222Sksewell@umich.educlass ExecContext { 725222Sksewell@umich.edu public: 735222Sksewell@umich.edu typedef TheISA::IntReg IntReg; 745222Sksewell@umich.edu typedef TheISA::PCState PCState; 755222Sksewell@umich.edu typedef TheISA::FloatReg FloatReg; 765222Sksewell@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 775222Sksewell@umich.edu typedef TheISA::MiscReg MiscReg; 785222Sksewell@umich.edu 795222Sksewell@umich.edu typedef TheISA::CCReg CCReg; 805222Sksewell@umich.edu 815224Sksewell@umich.edu public: 825222Sksewell@umich.edu /** 834661Sksewell@umich.edu * @{ 844661Sksewell@umich.edu * @name Integer Register Interfaces 855224Sksewell@umich.edu * 865222Sksewell@umich.edu */ 874661Sksewell@umich.edu 884661Sksewell@umich.edu /** Reads an integer register. */ 895224Sksewell@umich.edu virtual IntReg readIntRegOperand(const StaticInst *si, int idx) = 0; 904661Sksewell@umich.edu 914661Sksewell@umich.edu /** Sets an integer register to a value. */ 924661Sksewell@umich.edu virtual void setIntRegOperand(const StaticInst *si, 934661Sksewell@umich.edu int idx, IntReg val) = 0; 945222Sksewell@umich.edu 955222Sksewell@umich.edu /** @} */ 962447SN/A 972447SN/A 984661Sksewell@umich.edu /** 994661Sksewell@umich.edu * @{ 1004661Sksewell@umich.edu * @name Floating Point Register Interfaces 1014661Sksewell@umich.edu */ 1022447SN/A 1035222Sksewell@umich.edu /** Reads a floating point register of single register width. */ 1042447SN/A virtual FloatReg readFloatRegOperand(const StaticInst *si, int idx) = 0; 1052447SN/A 1065222Sksewell@umich.edu /** Reads a floating point register in its binary format, instead 1075222Sksewell@umich.edu * of by value. */ 1085222Sksewell@umich.edu virtual FloatRegBits readFloatRegOperandBits(const StaticInst *si, 1095222Sksewell@umich.edu int idx) = 0; 1105222Sksewell@umich.edu 1115222Sksewell@umich.edu /** Sets a floating point register of single width to a value. */ 1125222Sksewell@umich.edu virtual void setFloatRegOperand(const StaticInst *si, 1135222Sksewell@umich.edu int idx, FloatReg val) = 0; 1145222Sksewell@umich.edu 1155222Sksewell@umich.edu /** Sets the bits of a floating point register of single width 1165222Sksewell@umich.edu * to a binary value. */ 1175222Sksewell@umich.edu virtual void setFloatRegOperandBits(const StaticInst *si, 1185222Sksewell@umich.edu int idx, FloatRegBits val) = 0; 1195222Sksewell@umich.edu 1205222Sksewell@umich.edu /** @} */ 1215222Sksewell@umich.edu 1225222Sksewell@umich.edu /** 1235222Sksewell@umich.edu * @{ 1245222Sksewell@umich.edu * @name Condition Code Registers 1255222Sksewell@umich.edu */ 1265222Sksewell@umich.edu virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0; 1275222Sksewell@umich.edu virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0; 1285222Sksewell@umich.edu /** @} */ 1295222Sksewell@umich.edu 1305222Sksewell@umich.edu /** 1315222Sksewell@umich.edu * @{ 1325222Sksewell@umich.edu * @name Misc Register Interfaces 1335222Sksewell@umich.edu */ 1345222Sksewell@umich.edu virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0; 1352447SN/A virtual void setMiscRegOperand(const StaticInst *si, 1362447SN/A int idx, const MiscReg &val) = 0; 1372447SN/A 1382447SN/A /** 1392447SN/A * Reads a miscellaneous register, handling any architectural 1402447SN/A * side effects due to reading that register. 1412447SN/A */ 1422447SN/A virtual MiscReg readMiscReg(int misc_reg) = 0; 1432447SN/A 1442447SN/A /** 1452447SN/A * Sets a miscellaneous register, handling any architectural 1462447SN/A * side effects due to writing that register. 1472447SN/A */ 1482447SN/A virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 1492447SN/A 1502447SN/A /** @} */ 1515222Sksewell@umich.edu 1525222Sksewell@umich.edu /** 1535222Sksewell@umich.edu * @{ 1542447SN/A * @name PC Control 1555222Sksewell@umich.edu */ 1565222Sksewell@umich.edu virtual PCState pcState() const = 0; 1575222Sksewell@umich.edu virtual void pcState(const PCState &val) = 0; 1582447SN/A /** @} */ 1595222Sksewell@umich.edu 1605222Sksewell@umich.edu /** 1615222Sksewell@umich.edu * @{ 1622447SN/A * @name Memory Interface 1635222Sksewell@umich.edu */ 1642447SN/A /** 1652447SN/A * Record the effective address of the instruction. 1662447SN/A * 1675222Sksewell@umich.edu * @note Only valid for memory ops. 1682447SN/A */ 1692447SN/A virtual void setEA(Addr EA) = 0; 1702447SN/A /** 1715222Sksewell@umich.edu * Get the effective address of the instruction. 1724661Sksewell@umich.edu * 1734661Sksewell@umich.edu * @note Only valid for memory ops. 1744661Sksewell@umich.edu */ 1755222Sksewell@umich.edu virtual Addr getEA() const = 0; 1765222Sksewell@umich.edu 1775222Sksewell@umich.edu /** 1785222Sksewell@umich.edu * Perform an atomic memory read operation. Must be overridden 1795222Sksewell@umich.edu * for exec contexts that support atomic memory mode. Not pure 1805222Sksewell@umich.edu * virtual since exec contexts that only support timing memory 1815222Sksewell@umich.edu * mode need not override (though in that case this function 1825222Sksewell@umich.edu * should never be called). 1835222Sksewell@umich.edu */ 1845222Sksewell@umich.edu virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size, 1855222Sksewell@umich.edu unsigned int flags) 1865222Sksewell@umich.edu { 1875222Sksewell@umich.edu panic("ExecContext::readMem() should be overridden\n"); 1885222Sksewell@umich.edu } 1895222Sksewell@umich.edu 1905222Sksewell@umich.edu /** 1915222Sksewell@umich.edu * Initiate a timing memory read operation. Must be overridden 1925222Sksewell@umich.edu * for exec contexts that support timing memory mode. Not pure 1935222Sksewell@umich.edu * virtual since exec contexts that only support atomic memory 1945222Sksewell@umich.edu * mode need not override (though in that case this function 1955222Sksewell@umich.edu * should never be called). 1965222Sksewell@umich.edu */ 1975222Sksewell@umich.edu virtual Fault initiateMemRead(Addr addr, unsigned int size, 1985222Sksewell@umich.edu unsigned int flags) 1995222Sksewell@umich.edu { 2005222Sksewell@umich.edu panic("ExecContext::initiateMemRead() should be overridden\n"); 2015222Sksewell@umich.edu } 2025222Sksewell@umich.edu 2035222Sksewell@umich.edu /** 2045222Sksewell@umich.edu * For atomic-mode contexts, perform an atomic memory write operation. 2055222Sksewell@umich.edu * For timing-mode contexts, initiate a timing memory write operation. 2065222Sksewell@umich.edu */ 2075222Sksewell@umich.edu virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr, 2085222Sksewell@umich.edu unsigned int flags, uint64_t *res) = 0; 2095222Sksewell@umich.edu 2105222Sksewell@umich.edu /** 2115222Sksewell@umich.edu * Sets the number of consecutive store conditional failures. 2125222Sksewell@umich.edu */ 2135222Sksewell@umich.edu virtual void setStCondFailures(unsigned int sc_failures) = 0; 2145222Sksewell@umich.edu 2155222Sksewell@umich.edu /** 2165222Sksewell@umich.edu * Returns the number of consecutive store conditional failures. 2175222Sksewell@umich.edu */ 2185222Sksewell@umich.edu virtual unsigned int readStCondFailures() const = 0; 2195222Sksewell@umich.edu 2205222Sksewell@umich.edu /** @} */ 2215222Sksewell@umich.edu 2225222Sksewell@umich.edu /** 2235222Sksewell@umich.edu * @{ 2245222Sksewell@umich.edu * @name SysCall Emulation Interfaces 2255222Sksewell@umich.edu */ 2265222Sksewell@umich.edu 2275222Sksewell@umich.edu /** 2285222Sksewell@umich.edu * Executes a syscall specified by the callnum. 2295222Sksewell@umich.edu */ 2305222Sksewell@umich.edu virtual void syscall(int64_t callnum) = 0; 2315222Sksewell@umich.edu 2325222Sksewell@umich.edu /** @} */ 2335222Sksewell@umich.edu 2345222Sksewell@umich.edu /** Returns a pointer to the ThreadContext. */ 2355222Sksewell@umich.edu virtual ThreadContext *tcBase() = 0; 2365222Sksewell@umich.edu 2375222Sksewell@umich.edu /** 2385222Sksewell@umich.edu * @{ 2395222Sksewell@umich.edu * @name Alpha-Specific Interfaces 2405222Sksewell@umich.edu */ 2415222Sksewell@umich.edu 2425222Sksewell@umich.edu /** 2435222Sksewell@umich.edu * Somewhat Alpha-specific function that handles returning from an 2445222Sksewell@umich.edu * error or interrupt. 2455222Sksewell@umich.edu */ 2465222Sksewell@umich.edu virtual Fault hwrei() = 0; 2475222Sksewell@umich.edu 2485222Sksewell@umich.edu /** 2495222Sksewell@umich.edu * Check for special simulator handling of specific PAL calls. If 2505222Sksewell@umich.edu * return value is false, actual PAL call will be suppressed. 2515222Sksewell@umich.edu */ 2525222Sksewell@umich.edu virtual bool simPalCheck(int palFunc) = 0; 2535222Sksewell@umich.edu 2545222Sksewell@umich.edu /** @} */ 2555222Sksewell@umich.edu 2565222Sksewell@umich.edu /** 2575222Sksewell@umich.edu * @{ 2585222Sksewell@umich.edu * @name ARM-Specific Interfaces 2595222Sksewell@umich.edu */ 2605222Sksewell@umich.edu 2615222Sksewell@umich.edu virtual bool readPredicate() = 0; 2625222Sksewell@umich.edu virtual void setPredicate(bool val) = 0; 2635222Sksewell@umich.edu 2645222Sksewell@umich.edu /** @} */ 2655222Sksewell@umich.edu 2665222Sksewell@umich.edu /** 2675222Sksewell@umich.edu * @{ 2685222Sksewell@umich.edu * @name X86-Specific Interfaces 2695222Sksewell@umich.edu */ 2705222Sksewell@umich.edu 2715222Sksewell@umich.edu /** 2725222Sksewell@umich.edu * Invalidate a page in the DTLB <i>and</i> ITLB. 2735222Sksewell@umich.edu */ 2745222Sksewell@umich.edu virtual void demapPage(Addr vaddr, uint64_t asn) = 0; 2755222Sksewell@umich.edu virtual void armMonitor(Addr address) = 0; 2765222Sksewell@umich.edu virtual bool mwait(PacketPtr pkt) = 0; 2775222Sksewell@umich.edu virtual void mwaitAtomic(ThreadContext *tc) = 0; 2785222Sksewell@umich.edu virtual AddressMonitor *getAddrMonitor() = 0; 2795222Sksewell@umich.edu 2805222Sksewell@umich.edu /** @} */ 2815222Sksewell@umich.edu 2825222Sksewell@umich.edu /** 2835222Sksewell@umich.edu * @{ 2845222Sksewell@umich.edu * @name MIPS-Specific Interfaces 2855222Sksewell@umich.edu */ 2865222Sksewell@umich.edu 2875222Sksewell@umich.edu#if THE_ISA == MIPS_ISA 2885222Sksewell@umich.edu virtual MiscReg readRegOtherThread(int regIdx, 2895222Sksewell@umich.edu ThreadID tid = InvalidThreadID) = 0; 2905222Sksewell@umich.edu virtual void setRegOtherThread(int regIdx, MiscReg val, 2915222Sksewell@umich.edu ThreadID tid = InvalidThreadID) = 0; 2925222Sksewell@umich.edu#endif 2935222Sksewell@umich.edu 2945222Sksewell@umich.edu /** @} */ 2955222Sksewell@umich.edu}; 2965222Sksewell@umich.edu 2975222Sksewell@umich.edu#endif // __CPU_EXEC_CONTEXT_HH__ 2985222Sksewell@umich.edu