exec_context.hh revision 10529
12735Sktlim@umich.edu/* 210319SAndreas.Sandberg@ARM.com * Copyright (c) 2014 ARM Limited 310319SAndreas.Sandberg@ARM.com * All rights reserved 410319SAndreas.Sandberg@ARM.com * 510319SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 610319SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 710319SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 810319SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 910319SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 1010319SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 1110319SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 1210319SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 1310319SAndreas.Sandberg@ARM.com * 142735Sktlim@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 152735Sktlim@umich.edu * All rights reserved. 162735Sktlim@umich.edu * 172735Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 182735Sktlim@umich.edu * modification, are permitted provided that the following conditions are 192735Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 202735Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 212735Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 222735Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 232735Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 242735Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 252735Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 262735Sktlim@umich.edu * this software without specific prior written permission. 272735Sktlim@umich.edu * 282735Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292735Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302735Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312735Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322735Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332735Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342735Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352735Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362735Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372735Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382735Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392735Sktlim@umich.edu * 402735Sktlim@umich.edu * Authors: Kevin Lim 4110319SAndreas.Sandberg@ARM.com * Andreas Sandberg 422735Sktlim@umich.edu */ 432735Sktlim@umich.edu 4410319SAndreas.Sandberg@ARM.com#ifndef __CPU_EXEC_CONTEXT_HH__ 4510319SAndreas.Sandberg@ARM.com#define __CPU_EXEC_CONTEXT_HH__ 4610319SAndreas.Sandberg@ARM.com 4710319SAndreas.Sandberg@ARM.com#include "arch/registers.hh" 4810319SAndreas.Sandberg@ARM.com#include "base/types.hh" 4910319SAndreas.Sandberg@ARM.com#include "config/the_isa.hh" 5010529Smorr@cs.wisc.edu#include "cpu/base.hh" 5110319SAndreas.Sandberg@ARM.com#include "cpu/static_inst_fwd.hh" 5210319SAndreas.Sandberg@ARM.com#include "cpu/translation.hh" 532735Sktlim@umich.edu 542735Sktlim@umich.edu/** 5510319SAndreas.Sandberg@ARM.com * The ExecContext is an abstract base class the provides the 5610319SAndreas.Sandberg@ARM.com * interface used by the ISA to manipulate the state of the CPU model. 5710319SAndreas.Sandberg@ARM.com * 5810319SAndreas.Sandberg@ARM.com * Register accessor methods in this class typically provide the index 5910319SAndreas.Sandberg@ARM.com * of the instruction's operand (e.g., 0 or 1), not the architectural 6010319SAndreas.Sandberg@ARM.com * register index, to simplify the implementation of register 6110319SAndreas.Sandberg@ARM.com * renaming. The architectural register index can be found by 6210319SAndreas.Sandberg@ARM.com * indexing into the instruction's own operand index table. 6310319SAndreas.Sandberg@ARM.com * 6410319SAndreas.Sandberg@ARM.com * @note The methods in this class typically take a raw pointer to the 6510319SAndreas.Sandberg@ARM.com * StaticInst is provided instead of a ref-counted StaticInstPtr to 6610319SAndreas.Sandberg@ARM.com * reduce overhead as an argument. This is fine as long as the 6710319SAndreas.Sandberg@ARM.com * implementation doesn't copy the pointer into any long-term storage 6810319SAndreas.Sandberg@ARM.com * (which is pretty hard to imagine they would have reason to do). 692735Sktlim@umich.edu */ 702735Sktlim@umich.educlass ExecContext { 7110319SAndreas.Sandberg@ARM.com public: 7210319SAndreas.Sandberg@ARM.com typedef TheISA::IntReg IntReg; 7310319SAndreas.Sandberg@ARM.com typedef TheISA::PCState PCState; 7410319SAndreas.Sandberg@ARM.com typedef TheISA::FloatReg FloatReg; 7510319SAndreas.Sandberg@ARM.com typedef TheISA::FloatRegBits FloatRegBits; 7610319SAndreas.Sandberg@ARM.com typedef TheISA::MiscReg MiscReg; 7710319SAndreas.Sandberg@ARM.com 7810319SAndreas.Sandberg@ARM.com typedef TheISA::CCReg CCReg; 7910319SAndreas.Sandberg@ARM.com 8010319SAndreas.Sandberg@ARM.com public: 8110319SAndreas.Sandberg@ARM.com /** 8210319SAndreas.Sandberg@ARM.com * @{ 8310319SAndreas.Sandberg@ARM.com * @name Integer Register Interfaces 8410319SAndreas.Sandberg@ARM.com * 8510319SAndreas.Sandberg@ARM.com */ 862735Sktlim@umich.edu 872735Sktlim@umich.edu /** Reads an integer register. */ 8810319SAndreas.Sandberg@ARM.com virtual IntReg readIntRegOperand(const StaticInst *si, int idx) = 0; 8910319SAndreas.Sandberg@ARM.com 9010319SAndreas.Sandberg@ARM.com /** Sets an integer register to a value. */ 9110319SAndreas.Sandberg@ARM.com virtual void setIntRegOperand(const StaticInst *si, 9210319SAndreas.Sandberg@ARM.com int idx, IntReg val) = 0; 9310319SAndreas.Sandberg@ARM.com 9410319SAndreas.Sandberg@ARM.com /** @} */ 9510319SAndreas.Sandberg@ARM.com 9610319SAndreas.Sandberg@ARM.com 9710319SAndreas.Sandberg@ARM.com /** 9810319SAndreas.Sandberg@ARM.com * @{ 9910319SAndreas.Sandberg@ARM.com * @name Floating Point Register Interfaces 10010319SAndreas.Sandberg@ARM.com */ 1012735Sktlim@umich.edu 1022735Sktlim@umich.edu /** Reads a floating point register of single register width. */ 10310319SAndreas.Sandberg@ARM.com virtual FloatReg readFloatRegOperand(const StaticInst *si, int idx) = 0; 1042735Sktlim@umich.edu 1052735Sktlim@umich.edu /** Reads a floating point register in its binary format, instead 1062735Sktlim@umich.edu * of by value. */ 10710319SAndreas.Sandberg@ARM.com virtual FloatRegBits readFloatRegOperandBits(const StaticInst *si, 10810319SAndreas.Sandberg@ARM.com int idx) = 0; 1092735Sktlim@umich.edu 1102735Sktlim@umich.edu /** Sets a floating point register of single width to a value. */ 11110319SAndreas.Sandberg@ARM.com virtual void setFloatRegOperand(const StaticInst *si, 11210319SAndreas.Sandberg@ARM.com int idx, FloatReg val) = 0; 1132735Sktlim@umich.edu 1142735Sktlim@umich.edu /** Sets the bits of a floating point register of single width 1152735Sktlim@umich.edu * to a binary value. */ 11610319SAndreas.Sandberg@ARM.com virtual void setFloatRegOperandBits(const StaticInst *si, 11710319SAndreas.Sandberg@ARM.com int idx, FloatRegBits val) = 0; 1182735Sktlim@umich.edu 11910319SAndreas.Sandberg@ARM.com /** @} */ 1202735Sktlim@umich.edu 12110319SAndreas.Sandberg@ARM.com /** 12210319SAndreas.Sandberg@ARM.com * @{ 12310319SAndreas.Sandberg@ARM.com * @name Condition Code Registers 12410319SAndreas.Sandberg@ARM.com */ 12510319SAndreas.Sandberg@ARM.com virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0; 12610319SAndreas.Sandberg@ARM.com virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0; 12710319SAndreas.Sandberg@ARM.com /** @} */ 1282735Sktlim@umich.edu 12910319SAndreas.Sandberg@ARM.com /** 13010319SAndreas.Sandberg@ARM.com * @{ 13110319SAndreas.Sandberg@ARM.com * @name Misc Register Interfaces 13210319SAndreas.Sandberg@ARM.com */ 13310319SAndreas.Sandberg@ARM.com virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0; 13410319SAndreas.Sandberg@ARM.com virtual void setMiscRegOperand(const StaticInst *si, 13510319SAndreas.Sandberg@ARM.com int idx, const MiscReg &val) = 0; 1362735Sktlim@umich.edu 13710319SAndreas.Sandberg@ARM.com /** 13810319SAndreas.Sandberg@ARM.com * Reads a miscellaneous register, handling any architectural 13910319SAndreas.Sandberg@ARM.com * side effects due to reading that register. 14010319SAndreas.Sandberg@ARM.com */ 14110319SAndreas.Sandberg@ARM.com virtual MiscReg readMiscReg(int misc_reg) = 0; 1422735Sktlim@umich.edu 14310319SAndreas.Sandberg@ARM.com /** 14410319SAndreas.Sandberg@ARM.com * Sets a miscellaneous register, handling any architectural 14510319SAndreas.Sandberg@ARM.com * side effects due to writing that register. 14610319SAndreas.Sandberg@ARM.com */ 14710319SAndreas.Sandberg@ARM.com virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 1482735Sktlim@umich.edu 14910319SAndreas.Sandberg@ARM.com /** @} */ 1502735Sktlim@umich.edu 15110319SAndreas.Sandberg@ARM.com /** 15210319SAndreas.Sandberg@ARM.com * @{ 15310319SAndreas.Sandberg@ARM.com * @name PC Control 15410319SAndreas.Sandberg@ARM.com */ 15510319SAndreas.Sandberg@ARM.com virtual PCState pcState() const = 0; 15610319SAndreas.Sandberg@ARM.com virtual void pcState(const PCState &val) = 0; 15710319SAndreas.Sandberg@ARM.com /** @} */ 15810319SAndreas.Sandberg@ARM.com 15910319SAndreas.Sandberg@ARM.com /** 16010319SAndreas.Sandberg@ARM.com * @{ 16110319SAndreas.Sandberg@ARM.com * @name Memory Interface 16210319SAndreas.Sandberg@ARM.com */ 16310319SAndreas.Sandberg@ARM.com /** 16410319SAndreas.Sandberg@ARM.com * Record the effective address of the instruction. 16510319SAndreas.Sandberg@ARM.com * 16610319SAndreas.Sandberg@ARM.com * @note Only valid for memory ops. 16710319SAndreas.Sandberg@ARM.com */ 16810319SAndreas.Sandberg@ARM.com virtual void setEA(Addr EA) = 0; 16910319SAndreas.Sandberg@ARM.com /** 17010319SAndreas.Sandberg@ARM.com * Get the effective address of the instruction. 17110319SAndreas.Sandberg@ARM.com * 17210319SAndreas.Sandberg@ARM.com * @note Only valid for memory ops. 17310319SAndreas.Sandberg@ARM.com */ 17410319SAndreas.Sandberg@ARM.com virtual Addr getEA() const = 0; 17510319SAndreas.Sandberg@ARM.com 17610319SAndreas.Sandberg@ARM.com virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size, 17710319SAndreas.Sandberg@ARM.com unsigned int flags) = 0; 17810319SAndreas.Sandberg@ARM.com 17910319SAndreas.Sandberg@ARM.com virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr, 18010319SAndreas.Sandberg@ARM.com unsigned int flags, uint64_t *res) = 0; 18110319SAndreas.Sandberg@ARM.com 18210319SAndreas.Sandberg@ARM.com /** 18310319SAndreas.Sandberg@ARM.com * Sets the number of consecutive store conditional failures. 18410319SAndreas.Sandberg@ARM.com */ 18510319SAndreas.Sandberg@ARM.com virtual void setStCondFailures(unsigned int sc_failures) = 0; 18610319SAndreas.Sandberg@ARM.com 18710319SAndreas.Sandberg@ARM.com /** 18810319SAndreas.Sandberg@ARM.com * Returns the number of consecutive store conditional failures. 18910319SAndreas.Sandberg@ARM.com */ 19010319SAndreas.Sandberg@ARM.com virtual unsigned int readStCondFailures() const = 0; 19110319SAndreas.Sandberg@ARM.com 19210319SAndreas.Sandberg@ARM.com /** @} */ 19310319SAndreas.Sandberg@ARM.com 19410319SAndreas.Sandberg@ARM.com /** 19510319SAndreas.Sandberg@ARM.com * @{ 19610319SAndreas.Sandberg@ARM.com * @name SysCall Emulation Interfaces 19710319SAndreas.Sandberg@ARM.com */ 19810319SAndreas.Sandberg@ARM.com 19910319SAndreas.Sandberg@ARM.com /** 20010319SAndreas.Sandberg@ARM.com * Executes a syscall specified by the callnum. 20110319SAndreas.Sandberg@ARM.com */ 20210319SAndreas.Sandberg@ARM.com virtual void syscall(int64_t callnum) = 0; 20310319SAndreas.Sandberg@ARM.com 20410319SAndreas.Sandberg@ARM.com /** @} */ 2052735Sktlim@umich.edu 2062735Sktlim@umich.edu /** Returns a pointer to the ThreadContext. */ 20710319SAndreas.Sandberg@ARM.com virtual ThreadContext *tcBase() = 0; 2082735Sktlim@umich.edu 20910319SAndreas.Sandberg@ARM.com /** 21010319SAndreas.Sandberg@ARM.com * @{ 21110319SAndreas.Sandberg@ARM.com * @name Alpha-Specific Interfaces 21210319SAndreas.Sandberg@ARM.com */ 2137520Sgblack@eecs.umich.edu 21410319SAndreas.Sandberg@ARM.com /** 21510319SAndreas.Sandberg@ARM.com * Somewhat Alpha-specific function that handles returning from an 21610319SAndreas.Sandberg@ARM.com * error or interrupt. 21710319SAndreas.Sandberg@ARM.com */ 21810319SAndreas.Sandberg@ARM.com virtual Fault hwrei() = 0; 2195702Ssaidi@eecs.umich.edu 2205702Ssaidi@eecs.umich.edu /** 2215702Ssaidi@eecs.umich.edu * Check for special simulator handling of specific PAL calls. If 2225702Ssaidi@eecs.umich.edu * return value is false, actual PAL call will be suppressed. 2235702Ssaidi@eecs.umich.edu */ 22410319SAndreas.Sandberg@ARM.com virtual bool simPalCheck(int palFunc) = 0; 2258779Sgblack@eecs.umich.edu 22610319SAndreas.Sandberg@ARM.com /** @} */ 2276973Stjones1@inf.ed.ac.uk 22810319SAndreas.Sandberg@ARM.com /** 22910319SAndreas.Sandberg@ARM.com * @{ 23010319SAndreas.Sandberg@ARM.com * @name ARM-Specific Interfaces 23110319SAndreas.Sandberg@ARM.com */ 23210319SAndreas.Sandberg@ARM.com 23310319SAndreas.Sandberg@ARM.com virtual bool readPredicate() = 0; 23410319SAndreas.Sandberg@ARM.com virtual void setPredicate(bool val) = 0; 23510319SAndreas.Sandberg@ARM.com 23610319SAndreas.Sandberg@ARM.com /** @} */ 23710319SAndreas.Sandberg@ARM.com 23810319SAndreas.Sandberg@ARM.com /** 23910319SAndreas.Sandberg@ARM.com * @{ 24010319SAndreas.Sandberg@ARM.com * @name X86-Specific Interfaces 24110319SAndreas.Sandberg@ARM.com */ 24210319SAndreas.Sandberg@ARM.com 24310319SAndreas.Sandberg@ARM.com /** 24410319SAndreas.Sandberg@ARM.com * Invalidate a page in the DTLB <i>and</i> ITLB. 24510319SAndreas.Sandberg@ARM.com */ 24610319SAndreas.Sandberg@ARM.com virtual void demapPage(Addr vaddr, uint64_t asn) = 0; 24710529Smorr@cs.wisc.edu virtual void armMonitor(Addr address) = 0; 24810529Smorr@cs.wisc.edu virtual bool mwait(PacketPtr pkt) = 0; 24910529Smorr@cs.wisc.edu virtual void mwaitAtomic(ThreadContext *tc) = 0; 25010529Smorr@cs.wisc.edu virtual AddressMonitor *getAddrMonitor() = 0; 25110319SAndreas.Sandberg@ARM.com 25210319SAndreas.Sandberg@ARM.com /** @} */ 25310319SAndreas.Sandberg@ARM.com 25410319SAndreas.Sandberg@ARM.com /** 25510319SAndreas.Sandberg@ARM.com * @{ 25610319SAndreas.Sandberg@ARM.com * @name MIPS-Specific Interfaces 25710319SAndreas.Sandberg@ARM.com */ 25810319SAndreas.Sandberg@ARM.com 25910319SAndreas.Sandberg@ARM.com#if THE_ISA == MIPS_ISA 26010319SAndreas.Sandberg@ARM.com virtual MiscReg readRegOtherThread(int regIdx, 26110319SAndreas.Sandberg@ARM.com ThreadID tid = InvalidThreadID) = 0; 26210319SAndreas.Sandberg@ARM.com virtual void setRegOtherThread(int regIdx, MiscReg val, 26310319SAndreas.Sandberg@ARM.com ThreadID tid = InvalidThreadID) = 0; 26410319SAndreas.Sandberg@ARM.com#endif 26510319SAndreas.Sandberg@ARM.com 26610319SAndreas.Sandberg@ARM.com /** @} */ 2672735Sktlim@umich.edu}; 26810319SAndreas.Sandberg@ARM.com 26910319SAndreas.Sandberg@ARM.com#endif // __CPU_EXEC_CONTEXT_HH__ 270