thread_context.hh revision 9020
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__ 44#define __CPU_CHECKER_THREAD_CONTEXT_HH__ 45 46#include "arch/types.hh" 47#include "config/the_isa.hh" 48#include "cpu/checker/cpu.hh" 49#include "cpu/simple_thread.hh" 50#include "cpu/thread_context.hh" 51#include "debug/Checker.hh" 52 53class EndQuiesceEvent; 54namespace TheISA { 55 namespace Kernel { 56 class Statistics; 57 }; 58 class Decoder; 59}; 60 61/** 62 * Derived ThreadContext class for use with the Checker. The template 63 * parameter is the ThreadContext class used by the specific CPU being 64 * verified. This CheckerThreadContext is then used by the main CPU 65 * in place of its usual ThreadContext class. It handles updating the 66 * checker's state any time state is updated externally through the 67 * ThreadContext. 68 */ 69template <class TC> 70class CheckerThreadContext : public ThreadContext 71{ 72 public: 73 CheckerThreadContext(TC *actual_tc, 74 CheckerCPU *checker_cpu) 75 : actualTC(actual_tc), checkerTC(checker_cpu->thread), 76 checkerCPU(checker_cpu) 77 { } 78 79 private: 80 /** The main CPU's ThreadContext, or class that implements the 81 * ThreadContext interface. */ 82 TC *actualTC; 83 /** The checker's own SimpleThread. Will be updated any time 84 * anything uses this ThreadContext to externally update a 85 * thread's state. */ 86 SimpleThread *checkerTC; 87 /** Pointer to the checker CPU. */ 88 CheckerCPU *checkerCPU; 89 90 public: 91 92 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 93 94 int cpuId() { return actualTC->cpuId(); } 95 96 int contextId() { return actualTC->contextId(); } 97 98 void setContextId(int id) 99 { 100 actualTC->setContextId(id); 101 checkerTC->setContextId(id); 102 } 103 104 /** Returns this thread's ID number. */ 105 int threadId() { return actualTC->threadId(); } 106 void setThreadId(int id) 107 { 108 checkerTC->setThreadId(id); 109 actualTC->setThreadId(id); 110 } 111 112 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 113 114 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 115 116 CheckerCPU *getCheckerCpuPtr() 117 { 118 return checkerCPU; 119 } 120 121 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 122 123 System *getSystemPtr() { return actualTC->getSystemPtr(); } 124 125 TheISA::Kernel::Statistics *getKernelStats() 126 { return actualTC->getKernelStats(); } 127 128 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 129 130 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); } 131 132 FSTranslatingPortProxy &getVirtProxy() 133 { return actualTC->getVirtProxy(); } 134 135 void initMemProxies(ThreadContext *tc) 136 { actualTC->initMemProxies(tc); } 137 138 void connectMemPorts(ThreadContext *tc) 139 { 140 actualTC->connectMemPorts(tc); 141 } 142 143 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); } 144 145 /** Executes a syscall in SE mode. */ 146 void syscall(int64_t callnum) 147 { return actualTC->syscall(callnum); } 148 149 Status status() const { return actualTC->status(); } 150 151 void setStatus(Status new_status) 152 { 153 actualTC->setStatus(new_status); 154 checkerTC->setStatus(new_status); 155 } 156 157 /// Set the status to Active. Optional delay indicates number of 158 /// cycles to wait before beginning execution. 159 void activate(int delay = 1) { actualTC->activate(delay); } 160 161 /// Set the status to Suspended. 162 void suspend(int delay) { actualTC->suspend(delay); } 163 164 /// Set the status to Halted. 165 void halt(int delay) { actualTC->halt(delay); } 166 167 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 168 169 void takeOverFrom(ThreadContext *oldContext) 170 { 171 actualTC->takeOverFrom(oldContext); 172 checkerTC->copyState(oldContext); 173 } 174 175 void regStats(const std::string &name) 176 { 177 actualTC->regStats(name); 178 checkerTC->regStats(name); 179 } 180 181 void serialize(std::ostream &os) { actualTC->serialize(os); } 182 void unserialize(Checkpoint *cp, const std::string §ion) 183 { actualTC->unserialize(cp, section); } 184 185 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 186 187 Tick readLastActivate() { return actualTC->readLastActivate(); } 188 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 189 190 void profileClear() { return actualTC->profileClear(); } 191 void profileSample() { return actualTC->profileSample(); } 192 193 // @todo: Do I need this? 194 void copyArchRegs(ThreadContext *tc) 195 { 196 actualTC->copyArchRegs(tc); 197 checkerTC->copyArchRegs(tc); 198 } 199 200 void clearArchRegs() 201 { 202 actualTC->clearArchRegs(); 203 checkerTC->clearArchRegs(); 204 } 205 206 // 207 // New accessors for new decoder. 208 // 209 uint64_t readIntReg(int reg_idx) 210 { return actualTC->readIntReg(reg_idx); } 211 212 FloatReg readFloatReg(int reg_idx) 213 { return actualTC->readFloatReg(reg_idx); } 214 215 FloatRegBits readFloatRegBits(int reg_idx) 216 { return actualTC->readFloatRegBits(reg_idx); } 217 218 void setIntReg(int reg_idx, uint64_t val) 219 { 220 actualTC->setIntReg(reg_idx, val); 221 checkerTC->setIntReg(reg_idx, val); 222 } 223 224 void setFloatReg(int reg_idx, FloatReg val) 225 { 226 actualTC->setFloatReg(reg_idx, val); 227 checkerTC->setFloatReg(reg_idx, val); 228 } 229 230 void setFloatRegBits(int reg_idx, FloatRegBits val) 231 { 232 actualTC->setFloatRegBits(reg_idx, val); 233 checkerTC->setFloatRegBits(reg_idx, val); 234 } 235 236 /** Reads this thread's PC state. */ 237 TheISA::PCState pcState() 238 { return actualTC->pcState(); } 239 240 /** Sets this thread's PC state. */ 241 void pcState(const TheISA::PCState &val) 242 { 243 DPRINTF(Checker, "Changing PC to %s, old PC %s\n", 244 val, checkerTC->pcState()); 245 checkerTC->pcState(val); 246 checkerCPU->recordPCChange(val); 247 return actualTC->pcState(val); 248 } 249 250 void pcStateNoRecord(const TheISA::PCState &val) 251 { 252 return actualTC->pcState(val); 253 } 254 255 /** Reads this thread's PC. */ 256 Addr instAddr() 257 { return actualTC->instAddr(); } 258 259 /** Reads this thread's next PC. */ 260 Addr nextInstAddr() 261 { return actualTC->nextInstAddr(); } 262 263 /** Reads this thread's next PC. */ 264 MicroPC microPC() 265 { return actualTC->microPC(); } 266 267 MiscReg readMiscRegNoEffect(int misc_reg) 268 { return actualTC->readMiscRegNoEffect(misc_reg); } 269 270 MiscReg readMiscReg(int misc_reg) 271 { return actualTC->readMiscReg(misc_reg); } 272 273 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 274 { 275 DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker" 276 " and O3..\n", misc_reg); 277 checkerTC->setMiscRegNoEffect(misc_reg, val); 278 actualTC->setMiscRegNoEffect(misc_reg, val); 279 } 280 281 void setMiscReg(int misc_reg, const MiscReg &val) 282 { 283 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker" 284 " and O3..\n", misc_reg); 285 checkerTC->setMiscReg(misc_reg, val); 286 actualTC->setMiscReg(misc_reg, val); 287 } 288 289 int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); } 290 int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); } 291 292 unsigned readStCondFailures() 293 { return actualTC->readStCondFailures(); } 294 295 void setStCondFailures(unsigned sc_failures) 296 { 297 actualTC->setStCondFailures(sc_failures); 298 } 299 300 // @todo: Fix this! 301 bool misspeculating() { return actualTC->misspeculating(); } 302 303 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 304}; 305 306#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ 307