thread_context.hh revision 5712
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__ 32#define __CPU_CHECKER_THREAD_CONTEXT_HH__ 33 34#include "arch/types.hh" 35#include "cpu/checker/cpu.hh" 36#include "cpu/simple_thread.hh" 37#include "cpu/thread_context.hh" 38 39class EndQuiesceEvent; 40namespace TheISA { 41 namespace Kernel { 42 class Statistics; 43 }; 44}; 45 46/** 47 * Derived ThreadContext class for use with the Checker. The template 48 * parameter is the ThreadContext class used by the specific CPU being 49 * verified. This CheckerThreadContext is then used by the main CPU 50 * in place of its usual ThreadContext class. It handles updating the 51 * checker's state any time state is updated externally through the 52 * ThreadContext. 53 */ 54template <class TC> 55class CheckerThreadContext : public ThreadContext 56{ 57 public: 58 CheckerThreadContext(TC *actual_tc, 59 CheckerCPU *checker_cpu) 60 : actualTC(actual_tc), checkerTC(checker_cpu->thread), 61 checkerCPU(checker_cpu) 62 { } 63 64 private: 65 /** The main CPU's ThreadContext, or class that implements the 66 * ThreadContext interface. */ 67 TC *actualTC; 68 /** The checker's own SimpleThread. Will be updated any time 69 * anything uses this ThreadContext to externally update a 70 * thread's state. */ 71 SimpleThread *checkerTC; 72 /** Pointer to the checker CPU. */ 73 CheckerCPU *checkerCPU; 74 75 public: 76 77 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 78 79 void setCpuId(int id) 80 { 81 actualTC->setCpuId(id); 82 checkerTC->setCpuId(id); 83 } 84 85 int cpuId() { return actualTC->cpuId(); } 86 87 TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); } 88 89 TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); } 90 91#if FULL_SYSTEM 92 System *getSystemPtr() { return actualTC->getSystemPtr(); } 93 94 PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); } 95 96 TheISA::Kernel::Statistics *getKernelStats() 97 { return actualTC->getKernelStats(); } 98 99 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 100 101 VirtualPort *getVirtPort() 102 { return actualTC->getVirtPort(); } 103#else 104 TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 105 106 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 107#endif 108 109 Status status() const { return actualTC->status(); } 110 111 void setStatus(Status new_status) 112 { 113 actualTC->setStatus(new_status); 114 checkerTC->setStatus(new_status); 115 } 116 117 /// Set the status to Active. Optional delay indicates number of 118 /// cycles to wait before beginning execution. 119 void activate(int delay = 1) { actualTC->activate(delay); } 120 121 /// Set the status to Suspended. 122 void suspend() { actualTC->suspend(); } 123 124 /// Set the status to Unallocated. 125 void deallocate(int delay = 0) { actualTC->deallocate(delay); } 126 127 /// Set the status to Halted. 128 void halt() { actualTC->halt(); } 129 130#if FULL_SYSTEM 131 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 132#endif 133 134 void takeOverFrom(ThreadContext *oldContext) 135 { 136 actualTC->takeOverFrom(oldContext); 137 checkerTC->copyState(oldContext); 138 } 139 140 void regStats(const std::string &name) { actualTC->regStats(name); } 141 142 void serialize(std::ostream &os) { actualTC->serialize(os); } 143 void unserialize(Checkpoint *cp, const std::string §ion) 144 { actualTC->unserialize(cp, section); } 145 146#if FULL_SYSTEM 147 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 148 149 Tick readLastActivate() { return actualTC->readLastActivate(); } 150 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 151 152 void profileClear() { return actualTC->profileClear(); } 153 void profileSample() { return actualTC->profileSample(); } 154#endif 155 156 int getThreadNum() { return actualTC->getThreadNum(); } 157 158 // @todo: Do I need this? 159 MachInst getInst() { return actualTC->getInst(); } 160 161 // @todo: Do I need this? 162 void copyArchRegs(ThreadContext *tc) 163 { 164 actualTC->copyArchRegs(tc); 165 checkerTC->copyArchRegs(tc); 166 } 167 168 void clearArchRegs() 169 { 170 actualTC->clearArchRegs(); 171 checkerTC->clearArchRegs(); 172 } 173 174 // 175 // New accessors for new decoder. 176 // 177 uint64_t readIntReg(int reg_idx) 178 { return actualTC->readIntReg(reg_idx); } 179 180 FloatReg readFloatReg(int reg_idx, int width) 181 { return actualTC->readFloatReg(reg_idx, width); } 182 183 FloatReg readFloatReg(int reg_idx) 184 { return actualTC->readFloatReg(reg_idx); } 185 186 FloatRegBits readFloatRegBits(int reg_idx, int width) 187 { return actualTC->readFloatRegBits(reg_idx, width); } 188 189 FloatRegBits readFloatRegBits(int reg_idx) 190 { return actualTC->readFloatRegBits(reg_idx); } 191 192 void setIntReg(int reg_idx, uint64_t val) 193 { 194 actualTC->setIntReg(reg_idx, val); 195 checkerTC->setIntReg(reg_idx, val); 196 } 197 198 void setFloatReg(int reg_idx, FloatReg val, int width) 199 { 200 actualTC->setFloatReg(reg_idx, val, width); 201 checkerTC->setFloatReg(reg_idx, val, width); 202 } 203 204 void setFloatReg(int reg_idx, FloatReg val) 205 { 206 actualTC->setFloatReg(reg_idx, val); 207 checkerTC->setFloatReg(reg_idx, val); 208 } 209 210 void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 211 { 212 actualTC->setFloatRegBits(reg_idx, val, width); 213 checkerTC->setFloatRegBits(reg_idx, val, width); 214 } 215 216 void setFloatRegBits(int reg_idx, FloatRegBits val) 217 { 218 actualTC->setFloatRegBits(reg_idx, val); 219 checkerTC->setFloatRegBits(reg_idx, val); 220 } 221 222 uint64_t readPC() { return actualTC->readPC(); } 223 224 void setPC(uint64_t val) 225 { 226 actualTC->setPC(val); 227 checkerTC->setPC(val); 228 checkerCPU->recordPCChange(val); 229 } 230 231 uint64_t readNextPC() { return actualTC->readNextPC(); } 232 233 void setNextPC(uint64_t val) 234 { 235 actualTC->setNextPC(val); 236 checkerTC->setNextPC(val); 237 checkerCPU->recordNextPCChange(val); 238 } 239 240 uint64_t readNextNPC() { return actualTC->readNextNPC(); } 241 242 void setNextNPC(uint64_t val) 243 { 244 actualTC->setNextNPC(val); 245 checkerTC->setNextNPC(val); 246 checkerCPU->recordNextPCChange(val); 247 } 248 249 MiscReg readMiscRegNoEffect(int misc_reg) 250 { return actualTC->readMiscRegNoEffect(misc_reg); } 251 252 MiscReg readMiscReg(int misc_reg) 253 { return actualTC->readMiscReg(misc_reg); } 254 255 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 256 { 257 checkerTC->setMiscRegNoEffect(misc_reg, val); 258 actualTC->setMiscRegNoEffect(misc_reg, val); 259 } 260 261 void setMiscReg(int misc_reg, const MiscReg &val) 262 { 263 checkerTC->setMiscReg(misc_reg, val); 264 actualTC->setMiscReg(misc_reg, val); 265 } 266 267 unsigned readStCondFailures() 268 { return actualTC->readStCondFailures(); } 269 270 void setStCondFailures(unsigned sc_failures) 271 { 272 checkerTC->setStCondFailures(sc_failures); 273 actualTC->setStCondFailures(sc_failures); 274 } 275 276 // @todo: Fix this! 277 bool misspeculating() { return actualTC->misspeculating(); } 278 279#if !FULL_SYSTEM 280 IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); } 281 282 // used to shift args for indirect syscall 283 void setSyscallArg(int i, IntReg val) 284 { 285 checkerTC->setSyscallArg(i, val); 286 actualTC->setSyscallArg(i, val); 287 } 288 289 void setSyscallReturn(SyscallReturn return_value) 290 { 291 checkerTC->setSyscallReturn(return_value); 292 actualTC->setSyscallReturn(return_value); 293 } 294 295 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 296#endif 297}; 298 299#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ 300