thread_context.hh revision 12406
1/* 2 * Copyright (c) 2011-2012, 2016 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 */ 43 44#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__ 45#define __CPU_CHECKER_THREAD_CONTEXT_HH__ 46 47#include "arch/types.hh" 48#include "config/the_isa.hh" 49#include "cpu/checker/cpu.hh" 50#include "cpu/simple_thread.hh" 51#include "cpu/thread_context.hh" 52#include "debug/Checker.hh" 53 54class EndQuiesceEvent; 55namespace TheISA { 56 namespace Kernel { 57 class Statistics; 58 }; 59 class Decoder; 60}; 61 62/** 63 * Derived ThreadContext class for use with the Checker. The template 64 * parameter is the ThreadContext class used by the specific CPU being 65 * verified. This CheckerThreadContext is then used by the main CPU 66 * in place of its usual ThreadContext class. It handles updating the 67 * checker's state any time state is updated externally through the 68 * ThreadContext. 69 */ 70template <class TC> 71class CheckerThreadContext : public ThreadContext 72{ 73 public: 74 CheckerThreadContext(TC *actual_tc, 75 CheckerCPU *checker_cpu) 76 : actualTC(actual_tc), checkerTC(checker_cpu->thread), 77 checkerCPU(checker_cpu) 78 { } 79 80 private: 81 /** The main CPU's ThreadContext, or class that implements the 82 * ThreadContext interface. */ 83 TC *actualTC; 84 /** The checker's own SimpleThread. Will be updated any time 85 * anything uses this ThreadContext to externally update a 86 * thread's state. */ 87 SimpleThread *checkerTC; 88 /** Pointer to the checker CPU. */ 89 CheckerCPU *checkerCPU; 90 91 public: 92 93 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 94 95 uint32_t socketId() const { return actualTC->socketId(); } 96 97 int cpuId() const { return actualTC->cpuId(); } 98 99 ContextID contextId() const { return actualTC->contextId(); } 100 101 void setContextId(ContextID id) 102 { 103 actualTC->setContextId(id); 104 checkerTC->setContextId(id); 105 } 106 107 /** Returns this thread's ID number. */ 108 int threadId() const { return actualTC->threadId(); } 109 void setThreadId(int id) 110 { 111 checkerTC->setThreadId(id); 112 actualTC->setThreadId(id); 113 } 114 115 BaseTLB *getITBPtr() { return actualTC->getITBPtr(); } 116 117 BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); } 118 119 CheckerCPU *getCheckerCpuPtr() 120 { 121 return checkerCPU; 122 } 123 124 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 125 126 System *getSystemPtr() { return actualTC->getSystemPtr(); } 127 128 TheISA::Kernel::Statistics *getKernelStats() 129 { return actualTC->getKernelStats(); } 130 131 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 132 133 void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); } 134 135 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); } 136 137 FSTranslatingPortProxy &getVirtProxy() 138 { return actualTC->getVirtProxy(); } 139 140 void initMemProxies(ThreadContext *tc) 141 { actualTC->initMemProxies(tc); } 142 143 void connectMemPorts(ThreadContext *tc) 144 { 145 actualTC->connectMemPorts(tc); 146 } 147 148 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); } 149 150 /** Executes a syscall in SE mode. */ 151 void syscall(int64_t callnum, Fault *fault) 152 { return actualTC->syscall(callnum, fault); } 153 154 Status status() const { return actualTC->status(); } 155 156 void setStatus(Status new_status) 157 { 158 actualTC->setStatus(new_status); 159 checkerTC->setStatus(new_status); 160 } 161 162 /// Set the status to Active. 163 void activate() { actualTC->activate(); } 164 165 /// Set the status to Suspended. 166 void suspend() { actualTC->suspend(); } 167 168 /// Set the status to Halted. 169 void halt() { actualTC->halt(); } 170 171 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 172 173 void takeOverFrom(ThreadContext *oldContext) 174 { 175 actualTC->takeOverFrom(oldContext); 176 checkerTC->copyState(oldContext); 177 } 178 179 void regStats(const std::string &name) 180 { 181 actualTC->regStats(name); 182 checkerTC->regStats(name); 183 } 184 185 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 186 187 Tick readLastActivate() { return actualTC->readLastActivate(); } 188 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 189 190 void profileClear() { return actualTC->profileClear(); } 191 void profileSample() { return actualTC->profileSample(); } 192 193 // @todo: Do I need this? 194 void copyArchRegs(ThreadContext *tc) 195 { 196 actualTC->copyArchRegs(tc); 197 checkerTC->copyArchRegs(tc); 198 } 199 200 void clearArchRegs() 201 { 202 actualTC->clearArchRegs(); 203 checkerTC->clearArchRegs(); 204 } 205 206 // 207 // New accessors for new decoder. 208 // 209 uint64_t readIntReg(int reg_idx) 210 { return actualTC->readIntReg(reg_idx); } 211 212 FloatReg readFloatReg(int reg_idx) 213 { return actualTC->readFloatReg(reg_idx); } 214 215 FloatRegBits readFloatRegBits(int reg_idx) 216 { return actualTC->readFloatRegBits(reg_idx); } 217 218 const VecRegContainer& readVecReg(const RegId& reg) const 219 { return actualTC->readVecReg(reg); } 220 221 /** 222 * Read vector register for modification, hierarchical indexing. 223 */ 224 VecRegContainer& getWritableVecReg(const RegId& reg) 225 { return actualTC->getWritableVecReg(reg); } 226 227 /** Vector Register Lane Interfaces. */ 228 /** @{ */ 229 /** Reads source vector 8bit operand. */ 230 ConstVecLane8 231 readVec8BitLaneReg(const RegId& reg) const 232 { return actualTC->readVec8BitLaneReg(reg); } 233 234 /** Reads source vector 16bit operand. */ 235 ConstVecLane16 236 readVec16BitLaneReg(const RegId& reg) const 237 { return actualTC->readVec16BitLaneReg(reg); } 238 239 /** Reads source vector 32bit operand. */ 240 ConstVecLane32 241 readVec32BitLaneReg(const RegId& reg) const 242 { return actualTC->readVec32BitLaneReg(reg); } 243 244 /** Reads source vector 64bit operand. */ 245 ConstVecLane64 246 readVec64BitLaneReg(const RegId& reg) const 247 { return actualTC->readVec64BitLaneReg(reg); } 248 249 /** Write a lane of the destination vector register. */ 250 virtual void setVecLane(const RegId& reg, 251 const LaneData<LaneSize::Byte>& val) 252 { return actualTC->setVecLane(reg, val); } 253 virtual void setVecLane(const RegId& reg, 254 const LaneData<LaneSize::TwoByte>& val) 255 { return actualTC->setVecLane(reg, val); } 256 virtual void setVecLane(const RegId& reg, 257 const LaneData<LaneSize::FourByte>& val) 258 { return actualTC->setVecLane(reg, val); } 259 virtual void setVecLane(const RegId& reg, 260 const LaneData<LaneSize::EightByte>& val) 261 { return actualTC->setVecLane(reg, val); } 262 /** @} */ 263 264 const VecElem& readVecElem(const RegId& reg) const 265 { return actualTC->readVecElem(reg); } 266 267 CCReg readCCReg(int reg_idx) 268 { return actualTC->readCCReg(reg_idx); } 269 270 void setIntReg(int reg_idx, uint64_t val) 271 { 272 actualTC->setIntReg(reg_idx, val); 273 checkerTC->setIntReg(reg_idx, val); 274 } 275 276 void setFloatReg(int reg_idx, FloatReg val) 277 { 278 actualTC->setFloatReg(reg_idx, val); 279 checkerTC->setFloatReg(reg_idx, val); 280 } 281 282 void setFloatRegBits(int reg_idx, FloatRegBits val) 283 { 284 actualTC->setFloatRegBits(reg_idx, val); 285 checkerTC->setFloatRegBits(reg_idx, val); 286 } 287 288 void setVecReg(const RegId& reg, const VecRegContainer& val) 289 { 290 actualTC->setVecReg(reg, val); 291 checkerTC->setVecReg(reg, val); 292 } 293 294 void setVecElem(const RegId& reg, const VecElem& val) 295 { 296 actualTC->setVecElem(reg, val); 297 checkerTC->setVecElem(reg, val); 298 } 299 300 void setCCReg(int reg_idx, CCReg val) 301 { 302 actualTC->setCCReg(reg_idx, val); 303 checkerTC->setCCReg(reg_idx, val); 304 } 305 306 /** Reads this thread's PC state. */ 307 TheISA::PCState pcState() 308 { return actualTC->pcState(); } 309 310 /** Sets this thread's PC state. */ 311 void pcState(const TheISA::PCState &val) 312 { 313 DPRINTF(Checker, "Changing PC to %s, old PC %s\n", 314 val, checkerTC->pcState()); 315 checkerTC->pcState(val); 316 checkerCPU->recordPCChange(val); 317 return actualTC->pcState(val); 318 } 319 320 void setNPC(Addr val) 321 { 322 checkerTC->setNPC(val); 323 actualTC->setNPC(val); 324 } 325 326 void pcStateNoRecord(const TheISA::PCState &val) 327 { 328 return actualTC->pcState(val); 329 } 330 331 /** Reads this thread's PC. */ 332 Addr instAddr() 333 { return actualTC->instAddr(); } 334 335 /** Reads this thread's next PC. */ 336 Addr nextInstAddr() 337 { return actualTC->nextInstAddr(); } 338 339 /** Reads this thread's next PC. */ 340 MicroPC microPC() 341 { return actualTC->microPC(); } 342 343 MiscReg readMiscRegNoEffect(int misc_reg) const 344 { return actualTC->readMiscRegNoEffect(misc_reg); } 345 346 MiscReg readMiscReg(int misc_reg) 347 { return actualTC->readMiscReg(misc_reg); } 348 349 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 350 { 351 DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker" 352 " and O3..\n", misc_reg); 353 checkerTC->setMiscRegNoEffect(misc_reg, val); 354 actualTC->setMiscRegNoEffect(misc_reg, val); 355 } 356 357 void setMiscReg(int misc_reg, const MiscReg &val) 358 { 359 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker" 360 " and O3..\n", misc_reg); 361 checkerTC->setMiscReg(misc_reg, val); 362 actualTC->setMiscReg(misc_reg, val); 363 } 364 365 RegId flattenRegId(const RegId& regId) const { 366 return actualTC->flattenRegId(regId); 367 } 368 369 unsigned readStCondFailures() 370 { return actualTC->readStCondFailures(); } 371 372 void setStCondFailures(unsigned sc_failures) 373 { 374 actualTC->setStCondFailures(sc_failures); 375 } 376 377 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 378 379 uint64_t readIntRegFlat(int idx) 380 { return actualTC->readIntRegFlat(idx); } 381 382 void setIntRegFlat(int idx, uint64_t val) 383 { actualTC->setIntRegFlat(idx, val); } 384 385 FloatReg readFloatRegFlat(int idx) 386 { return actualTC->readFloatRegFlat(idx); } 387 388 void setFloatRegFlat(int idx, FloatReg val) 389 { actualTC->setFloatRegFlat(idx, val); } 390 391 FloatRegBits readFloatRegBitsFlat(int idx) 392 { return actualTC->readFloatRegBitsFlat(idx); } 393 394 void setFloatRegBitsFlat(int idx, FloatRegBits val) 395 { actualTC->setFloatRegBitsFlat(idx, val); } 396 397 const VecRegContainer& readVecRegFlat(int idx) const 398 { return actualTC->readVecRegFlat(idx); } 399 400 /** 401 * Read vector register for modification, flat indexing. 402 */ 403 VecRegContainer& getWritableVecRegFlat(int idx) 404 { return actualTC->getWritableVecRegFlat(idx); } 405 406 void setVecRegFlat(int idx, const VecRegContainer& val) 407 { actualTC->setVecRegFlat(idx, val); } 408 409 const VecElem& readVecElemFlat(const RegIndex& idx, 410 const ElemIndex& elem_idx) const 411 { return actualTC->readVecElemFlat(idx, elem_idx); } 412 413 void setVecElemFlat(const RegIndex& idx, 414 const ElemIndex& elem_idx, const VecElem& val) 415 { actualTC->setVecElemFlat(idx, elem_idx, val); } 416 417 CCReg readCCRegFlat(int idx) 418 { return actualTC->readCCRegFlat(idx); } 419 420 void setCCRegFlat(int idx, CCReg val) 421 { actualTC->setCCRegFlat(idx, val); } 422}; 423 424#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ 425