thread_context.hh revision 10033
1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 */ 43 44#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__ 45#define __CPU_CHECKER_THREAD_CONTEXT_HH__ 46 47#include "arch/types.hh" 48#include "config/the_isa.hh" 49#include "cpu/checker/cpu.hh" 50#include "cpu/simple_thread.hh" 51#include "cpu/thread_context.hh" 52#include "debug/Checker.hh" 53 54class EndQuiesceEvent; 55namespace TheISA { 56 namespace Kernel { 57 class Statistics; 58 }; 59 class Decoder; 60}; 61 62/** 63 * Derived ThreadContext class for use with the Checker. The template 64 * parameter is the ThreadContext class used by the specific CPU being 65 * verified. This CheckerThreadContext is then used by the main CPU 66 * in place of its usual ThreadContext class. It handles updating the 67 * checker's state any time state is updated externally through the 68 * ThreadContext. 69 */ 70template <class TC> 71class CheckerThreadContext : public ThreadContext 72{ 73 public: 74 CheckerThreadContext(TC *actual_tc, 75 CheckerCPU *checker_cpu) 76 : actualTC(actual_tc), checkerTC(checker_cpu->thread), 77 checkerCPU(checker_cpu) 78 { } 79 80 private: 81 /** The main CPU's ThreadContext, or class that implements the 82 * ThreadContext interface. */ 83 TC *actualTC; 84 /** The checker's own SimpleThread. Will be updated any time 85 * anything uses this ThreadContext to externally update a 86 * thread's state. */ 87 SimpleThread *checkerTC; 88 /** Pointer to the checker CPU. */ 89 CheckerCPU *checkerCPU; 90 91 public: 92 93 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 94 95 int cpuId() { return actualTC->cpuId(); } 96 97 int contextId() { return actualTC->contextId(); } 98 99 void setContextId(int id) 100 { 101 actualTC->setContextId(id); 102 checkerTC->setContextId(id); 103 } 104 105 /** Returns this thread's ID number. */ 106 int threadId() { return actualTC->threadId(); } 107 void setThreadId(int id) 108 { 109 checkerTC->setThreadId(id); 110 actualTC->setThreadId(id); 111 } 112 113 TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 114 115 TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 116 117 CheckerCPU *getCheckerCpuPtr() 118 { 119 return checkerCPU; 120 } 121 122 TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 123 124 System *getSystemPtr() { return actualTC->getSystemPtr(); } 125 126 TheISA::Kernel::Statistics *getKernelStats() 127 { return actualTC->getKernelStats(); } 128 129 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 130 131 PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); } 132 133 FSTranslatingPortProxy &getVirtProxy() 134 { return actualTC->getVirtProxy(); } 135 136 void initMemProxies(ThreadContext *tc) 137 { actualTC->initMemProxies(tc); } 138 139 void connectMemPorts(ThreadContext *tc) 140 { 141 actualTC->connectMemPorts(tc); 142 } 143 144 SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); } 145 146 /** Executes a syscall in SE mode. */ 147 void syscall(int64_t callnum) 148 { return actualTC->syscall(callnum); } 149 150 Status status() const { return actualTC->status(); } 151 152 void setStatus(Status new_status) 153 { 154 actualTC->setStatus(new_status); 155 checkerTC->setStatus(new_status); 156 } 157 158 /// Set the status to Active. Optional delay indicates number of 159 /// cycles to wait before beginning execution. 160 void activate(Cycles delay = Cycles(1)) 161 { actualTC->activate(delay); } 162 163 /// Set the status to Suspended. 164 void suspend(Cycles delay) { actualTC->suspend(delay); } 165 166 /// Set the status to Halted. 167 void halt(Cycles delay) { actualTC->halt(delay); } 168 169 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 170 171 void takeOverFrom(ThreadContext *oldContext) 172 { 173 actualTC->takeOverFrom(oldContext); 174 checkerTC->copyState(oldContext); 175 } 176 177 void regStats(const std::string &name) 178 { 179 actualTC->regStats(name); 180 checkerTC->regStats(name); 181 } 182 183 void serialize(std::ostream &os) { actualTC->serialize(os); } 184 void unserialize(Checkpoint *cp, const std::string §ion) 185 { actualTC->unserialize(cp, section); } 186 187 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 188 189 Tick readLastActivate() { return actualTC->readLastActivate(); } 190 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 191 192 void profileClear() { return actualTC->profileClear(); } 193 void profileSample() { return actualTC->profileSample(); } 194 195 // @todo: Do I need this? 196 void copyArchRegs(ThreadContext *tc) 197 { 198 actualTC->copyArchRegs(tc); 199 checkerTC->copyArchRegs(tc); 200 } 201 202 void clearArchRegs() 203 { 204 actualTC->clearArchRegs(); 205 checkerTC->clearArchRegs(); 206 } 207 208 // 209 // New accessors for new decoder. 210 // 211 uint64_t readIntReg(int reg_idx) 212 { return actualTC->readIntReg(reg_idx); } 213 214 FloatReg readFloatReg(int reg_idx) 215 { return actualTC->readFloatReg(reg_idx); } 216 217 FloatRegBits readFloatRegBits(int reg_idx) 218 { return actualTC->readFloatRegBits(reg_idx); } 219 220 CCReg readCCReg(int reg_idx) 221 { return actualTC->readCCReg(reg_idx); } 222 223 void setIntReg(int reg_idx, uint64_t val) 224 { 225 actualTC->setIntReg(reg_idx, val); 226 checkerTC->setIntReg(reg_idx, val); 227 } 228 229 void setFloatReg(int reg_idx, FloatReg val) 230 { 231 actualTC->setFloatReg(reg_idx, val); 232 checkerTC->setFloatReg(reg_idx, val); 233 } 234 235 void setFloatRegBits(int reg_idx, FloatRegBits val) 236 { 237 actualTC->setFloatRegBits(reg_idx, val); 238 checkerTC->setFloatRegBits(reg_idx, val); 239 } 240 241 void setCCReg(int reg_idx, CCReg val) 242 { 243 actualTC->setCCReg(reg_idx, val); 244 checkerTC->setCCReg(reg_idx, val); 245 } 246 247 /** Reads this thread's PC state. */ 248 TheISA::PCState pcState() 249 { return actualTC->pcState(); } 250 251 /** Sets this thread's PC state. */ 252 void pcState(const TheISA::PCState &val) 253 { 254 DPRINTF(Checker, "Changing PC to %s, old PC %s\n", 255 val, checkerTC->pcState()); 256 checkerTC->pcState(val); 257 checkerCPU->recordPCChange(val); 258 return actualTC->pcState(val); 259 } 260 261 void pcStateNoRecord(const TheISA::PCState &val) 262 { 263 return actualTC->pcState(val); 264 } 265 266 /** Reads this thread's PC. */ 267 Addr instAddr() 268 { return actualTC->instAddr(); } 269 270 /** Reads this thread's next PC. */ 271 Addr nextInstAddr() 272 { return actualTC->nextInstAddr(); } 273 274 /** Reads this thread's next PC. */ 275 MicroPC microPC() 276 { return actualTC->microPC(); } 277 278 MiscReg readMiscRegNoEffect(int misc_reg) 279 { return actualTC->readMiscRegNoEffect(misc_reg); } 280 281 MiscReg readMiscReg(int misc_reg) 282 { return actualTC->readMiscReg(misc_reg); } 283 284 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 285 { 286 DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker" 287 " and O3..\n", misc_reg); 288 checkerTC->setMiscRegNoEffect(misc_reg, val); 289 actualTC->setMiscRegNoEffect(misc_reg, val); 290 } 291 292 void setMiscReg(int misc_reg, const MiscReg &val) 293 { 294 DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker" 295 " and O3..\n", misc_reg); 296 checkerTC->setMiscReg(misc_reg, val); 297 actualTC->setMiscReg(misc_reg, val); 298 } 299 300 int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); } 301 int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); } 302 int flattenCCIndex(int reg) { return actualTC->flattenCCIndex(reg); } 303 int flattenMiscIndex(int reg) { return actualTC->flattenMiscIndex(reg); } 304 305 unsigned readStCondFailures() 306 { return actualTC->readStCondFailures(); } 307 308 void setStCondFailures(unsigned sc_failures) 309 { 310 actualTC->setStCondFailures(sc_failures); 311 } 312 313 // @todo: Fix this! 314 bool misspeculating() { return actualTC->misspeculating(); } 315 316 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 317 318 uint64_t readIntRegFlat(int idx) 319 { return actualTC->readIntRegFlat(idx); } 320 321 void setIntRegFlat(int idx, uint64_t val) 322 { actualTC->setIntRegFlat(idx, val); } 323 324 FloatReg readFloatRegFlat(int idx) 325 { return actualTC->readFloatRegFlat(idx); } 326 327 void setFloatRegFlat(int idx, FloatReg val) 328 { actualTC->setFloatRegFlat(idx, val); } 329 330 FloatRegBits readFloatRegBitsFlat(int idx) 331 { return actualTC->readFloatRegBitsFlat(idx); } 332 333 void setFloatRegBitsFlat(int idx, FloatRegBits val) 334 { actualTC->setFloatRegBitsFlat(idx, val); } 335 336 CCReg readCCRegFlat(int idx) 337 { return actualTC->readCCRegFlat(idx); } 338 339 void setCCRegFlat(int idx, CCReg val) 340 { actualTC->setCCRegFlat(idx, val); } 341}; 342 343#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ 344