thread_context.hh revision 8887
12330SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2011 ARM Limited 38733Sgeoffrey.blake@arm.com * All rights reserved 48733Sgeoffrey.blake@arm.com * 58733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 68733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 78733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 88733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 98733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 108733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 118733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 128733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 138733Sgeoffrey.blake@arm.com * 142330SN/A * Copyright (c) 2006 The Regents of The University of Michigan 152330SN/A * All rights reserved. 162330SN/A * 172330SN/A * Redistribution and use in source and binary forms, with or without 182330SN/A * modification, are permitted provided that the following conditions are 192330SN/A * met: redistributions of source code must retain the above copyright 202330SN/A * notice, this list of conditions and the following disclaimer; 212330SN/A * redistributions in binary form must reproduce the above copyright 222330SN/A * notice, this list of conditions and the following disclaimer in the 232330SN/A * documentation and/or other materials provided with the distribution; 242330SN/A * neither the name of the copyright holders nor the names of its 252330SN/A * contributors may be used to endorse or promote products derived from 262330SN/A * this software without specific prior written permission. 272330SN/A * 282330SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292330SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302330SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312330SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322330SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332330SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342330SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352330SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362330SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372330SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382330SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392689Sktlim@umich.edu * 402689Sktlim@umich.edu * Authors: Kevin Lim 412330SN/A */ 422330SN/A 432683Sktlim@umich.edu#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__ 442683Sktlim@umich.edu#define __CPU_CHECKER_THREAD_CONTEXT_HH__ 452315SN/A 462972Sgblack@eecs.umich.edu#include "arch/types.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 482315SN/A#include "cpu/checker/cpu.hh" 492683Sktlim@umich.edu#include "cpu/simple_thread.hh" 502680SN/A#include "cpu/thread_context.hh" 518733Sgeoffrey.blake@arm.com#include "debug/Checker.hh" 522315SN/A 532315SN/Aclass EndQuiesceEvent; 543548Sgblack@eecs.umich.edunamespace TheISA { 553548Sgblack@eecs.umich.edu namespace Kernel { 563548Sgblack@eecs.umich.edu class Statistics; 573548Sgblack@eecs.umich.edu }; 582330SN/A}; 592315SN/A 602350SN/A/** 612680SN/A * Derived ThreadContext class for use with the Checker. The template 622680SN/A * parameter is the ThreadContext class used by the specific CPU being 632683Sktlim@umich.edu * verified. This CheckerThreadContext is then used by the main CPU 642683Sktlim@umich.edu * in place of its usual ThreadContext class. It handles updating the 652683Sktlim@umich.edu * checker's state any time state is updated externally through the 662683Sktlim@umich.edu * ThreadContext. 672350SN/A */ 682680SN/Atemplate <class TC> 692680SN/Aclass CheckerThreadContext : public ThreadContext 702315SN/A{ 712315SN/A public: 722680SN/A CheckerThreadContext(TC *actual_tc, 732683Sktlim@umich.edu CheckerCPU *checker_cpu) 742683Sktlim@umich.edu : actualTC(actual_tc), checkerTC(checker_cpu->thread), 752330SN/A checkerCPU(checker_cpu) 762315SN/A { } 772315SN/A 782315SN/A private: 792683Sktlim@umich.edu /** The main CPU's ThreadContext, or class that implements the 802683Sktlim@umich.edu * ThreadContext interface. */ 812680SN/A TC *actualTC; 822683Sktlim@umich.edu /** The checker's own SimpleThread. Will be updated any time 832683Sktlim@umich.edu * anything uses this ThreadContext to externally update a 842683Sktlim@umich.edu * thread's state. */ 852683Sktlim@umich.edu SimpleThread *checkerTC; 862683Sktlim@umich.edu /** Pointer to the checker CPU. */ 872315SN/A CheckerCPU *checkerCPU; 882315SN/A 892315SN/A public: 902315SN/A 912680SN/A BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 922315SN/A 938733Sgeoffrey.blake@arm.com int cpuId() { return actualTC->cpuId(); } 948733Sgeoffrey.blake@arm.com 958733Sgeoffrey.blake@arm.com int contextId() { return actualTC->contextId(); } 968733Sgeoffrey.blake@arm.com 978733Sgeoffrey.blake@arm.com void setContextId(int id) 982315SN/A { 998733Sgeoffrey.blake@arm.com actualTC->setContextId(id); 1008733Sgeoffrey.blake@arm.com checkerTC->setContextId(id); 1012315SN/A } 1022315SN/A 1038733Sgeoffrey.blake@arm.com /** Returns this thread's ID number. */ 1048733Sgeoffrey.blake@arm.com int threadId() { return actualTC->threadId(); } 1058733Sgeoffrey.blake@arm.com void setThreadId(int id) 1068733Sgeoffrey.blake@arm.com { 1078733Sgeoffrey.blake@arm.com checkerTC->setThreadId(id); 1088733Sgeoffrey.blake@arm.com actualTC->setThreadId(id); 1098733Sgeoffrey.blake@arm.com } 1102315SN/A 1116022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 1124997Sgblack@eecs.umich.edu 1136022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 1144997Sgblack@eecs.umich.edu 1158887Sgeoffrey.blake@arm.com CheckerCPU *getCheckerCpuPtr() 1168887Sgeoffrey.blake@arm.com { 1178887Sgeoffrey.blake@arm.com return checkerCPU; 1188887Sgeoffrey.blake@arm.com } 1198733Sgeoffrey.blake@arm.com 1208733Sgeoffrey.blake@arm.com Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 1218733Sgeoffrey.blake@arm.com 1222680SN/A System *getSystemPtr() { return actualTC->getSystemPtr(); } 1232315SN/A 1242680SN/A PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); } 1252315SN/A 1263548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() 1273548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 1282690Sktlim@umich.edu 1297679Sgblack@eecs.umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 1307679Sgblack@eecs.umich.edu 1318852Sandreas.hansson@arm.com PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); } 1322690Sktlim@umich.edu 1338852Sandreas.hansson@arm.com FSTranslatingPortProxy &getVirtProxy() 1348706Sandreas.hansson@arm.com { return actualTC->getVirtProxy(); } 1358733Sgeoffrey.blake@arm.com 1368733Sgeoffrey.blake@arm.com void initMemProxies(ThreadContext *tc) 1378733Sgeoffrey.blake@arm.com { actualTC->initMemProxies(tc); } 1388733Sgeoffrey.blake@arm.com 1398733Sgeoffrey.blake@arm.com void connectMemPorts(ThreadContext *tc) 1408733Sgeoffrey.blake@arm.com { 1418733Sgeoffrey.blake@arm.com actualTC->connectMemPorts(tc); 1428733Sgeoffrey.blake@arm.com } 1438809Sgblack@eecs.umich.edu 1448852Sandreas.hansson@arm.com SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); } 1452690Sktlim@umich.edu 1468733Sgeoffrey.blake@arm.com /** Executes a syscall in SE mode. */ 1478733Sgeoffrey.blake@arm.com void syscall(int64_t callnum) 1488733Sgeoffrey.blake@arm.com { return actualTC->syscall(callnum); } 1492315SN/A 1502680SN/A Status status() const { return actualTC->status(); } 1512315SN/A 1522315SN/A void setStatus(Status new_status) 1532330SN/A { 1542680SN/A actualTC->setStatus(new_status); 1552680SN/A checkerTC->setStatus(new_status); 1562330SN/A } 1572315SN/A 1582315SN/A /// Set the status to Active. Optional delay indicates number of 1592315SN/A /// cycles to wait before beginning execution. 1602680SN/A void activate(int delay = 1) { actualTC->activate(delay); } 1612315SN/A 1622315SN/A /// Set the status to Suspended. 1638733Sgeoffrey.blake@arm.com void suspend(int delay) { actualTC->suspend(delay); } 1642315SN/A 1652315SN/A /// Set the status to Halted. 1668733Sgeoffrey.blake@arm.com void halt(int delay) { actualTC->halt(delay); } 1672315SN/A 1682680SN/A void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 1692315SN/A 1702680SN/A void takeOverFrom(ThreadContext *oldContext) 1712315SN/A { 1722680SN/A actualTC->takeOverFrom(oldContext); 1733225Sktlim@umich.edu checkerTC->copyState(oldContext); 1742315SN/A } 1752315SN/A 1768733Sgeoffrey.blake@arm.com void regStats(const std::string &name) 1778733Sgeoffrey.blake@arm.com { 1788733Sgeoffrey.blake@arm.com actualTC->regStats(name); 1798733Sgeoffrey.blake@arm.com checkerTC->regStats(name); 1808733Sgeoffrey.blake@arm.com } 1812315SN/A 1822680SN/A void serialize(std::ostream &os) { actualTC->serialize(os); } 1832315SN/A void unserialize(Checkpoint *cp, const std::string §ion) 1842680SN/A { actualTC->unserialize(cp, section); } 1852315SN/A 1862680SN/A EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 1872315SN/A 1882680SN/A Tick readLastActivate() { return actualTC->readLastActivate(); } 1892680SN/A Tick readLastSuspend() { return actualTC->readLastSuspend(); } 1902315SN/A 1912680SN/A void profileClear() { return actualTC->profileClear(); } 1922680SN/A void profileSample() { return actualTC->profileSample(); } 1932315SN/A 1942315SN/A // @todo: Do I need this? 1952680SN/A void copyArchRegs(ThreadContext *tc) 1962315SN/A { 1972680SN/A actualTC->copyArchRegs(tc); 1982680SN/A checkerTC->copyArchRegs(tc); 1992315SN/A } 2002315SN/A 2012315SN/A void clearArchRegs() 2022315SN/A { 2032680SN/A actualTC->clearArchRegs(); 2042680SN/A checkerTC->clearArchRegs(); 2052315SN/A } 2062315SN/A 2072315SN/A // 2082315SN/A // New accessors for new decoder. 2092315SN/A // 2102315SN/A uint64_t readIntReg(int reg_idx) 2112680SN/A { return actualTC->readIntReg(reg_idx); } 2122315SN/A 2132669SN/A FloatReg readFloatReg(int reg_idx) 2142680SN/A { return actualTC->readFloatReg(reg_idx); } 2152315SN/A 2162669SN/A FloatRegBits readFloatRegBits(int reg_idx) 2172680SN/A { return actualTC->readFloatRegBits(reg_idx); } 2182315SN/A 2192315SN/A void setIntReg(int reg_idx, uint64_t val) 2202315SN/A { 2212680SN/A actualTC->setIntReg(reg_idx, val); 2222680SN/A checkerTC->setIntReg(reg_idx, val); 2232315SN/A } 2242315SN/A 2252669SN/A void setFloatReg(int reg_idx, FloatReg val) 2262315SN/A { 2272680SN/A actualTC->setFloatReg(reg_idx, val); 2282680SN/A checkerTC->setFloatReg(reg_idx, val); 2292315SN/A } 2302315SN/A 2312669SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 2322669SN/A { 2332680SN/A actualTC->setFloatRegBits(reg_idx, val); 2342680SN/A checkerTC->setFloatRegBits(reg_idx, val); 2352315SN/A } 2362315SN/A 2378733Sgeoffrey.blake@arm.com /** Reads this thread's PC state. */ 2388733Sgeoffrey.blake@arm.com TheISA::PCState pcState() 2398733Sgeoffrey.blake@arm.com { return actualTC->pcState(); } 2402315SN/A 2418733Sgeoffrey.blake@arm.com /** Sets this thread's PC state. */ 2428733Sgeoffrey.blake@arm.com void pcState(const TheISA::PCState &val) 2432315SN/A { 2448733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Changing PC to %s, old PC %s\n", 2458733Sgeoffrey.blake@arm.com val, checkerTC->pcState()); 2468733Sgeoffrey.blake@arm.com checkerTC->pcState(val); 2472315SN/A checkerCPU->recordPCChange(val); 2488733Sgeoffrey.blake@arm.com return actualTC->pcState(val); 2492315SN/A } 2502315SN/A 2518733Sgeoffrey.blake@arm.com void pcStateNoRecord(const TheISA::PCState &val) 2522315SN/A { 2538733Sgeoffrey.blake@arm.com return actualTC->pcState(val); 2542315SN/A } 2552315SN/A 2568733Sgeoffrey.blake@arm.com /** Reads this thread's PC. */ 2578733Sgeoffrey.blake@arm.com Addr instAddr() 2588733Sgeoffrey.blake@arm.com { return actualTC->instAddr(); } 2592669SN/A 2608733Sgeoffrey.blake@arm.com /** Reads this thread's next PC. */ 2618733Sgeoffrey.blake@arm.com Addr nextInstAddr() 2628733Sgeoffrey.blake@arm.com { return actualTC->nextInstAddr(); } 2638733Sgeoffrey.blake@arm.com 2648733Sgeoffrey.blake@arm.com /** Reads this thread's next PC. */ 2658733Sgeoffrey.blake@arm.com MicroPC microPC() 2668733Sgeoffrey.blake@arm.com { return actualTC->microPC(); } 2672669SN/A 2684172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 2694172Ssaidi@eecs.umich.edu { return actualTC->readMiscRegNoEffect(misc_reg); } 2704172Ssaidi@eecs.umich.edu 2712315SN/A MiscReg readMiscReg(int misc_reg) 2722680SN/A { return actualTC->readMiscReg(misc_reg); } 2732315SN/A 2744172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 2754172Ssaidi@eecs.umich.edu { 2768733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker" 2778733Sgeoffrey.blake@arm.com " and O3..\n", misc_reg); 2784172Ssaidi@eecs.umich.edu checkerTC->setMiscRegNoEffect(misc_reg, val); 2794172Ssaidi@eecs.umich.edu actualTC->setMiscRegNoEffect(misc_reg, val); 2804172Ssaidi@eecs.umich.edu } 2812315SN/A 2823468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 2832315SN/A { 2848733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker" 2858733Sgeoffrey.blake@arm.com " and O3..\n", misc_reg); 2862680SN/A checkerTC->setMiscReg(misc_reg, val); 2873468Sgblack@eecs.umich.edu actualTC->setMiscReg(misc_reg, val); 2882315SN/A } 2892315SN/A 2908733Sgeoffrey.blake@arm.com int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); } 2918733Sgeoffrey.blake@arm.com int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); } 2928733Sgeoffrey.blake@arm.com 2932315SN/A unsigned readStCondFailures() 2942680SN/A { return actualTC->readStCondFailures(); } 2952315SN/A 2962315SN/A void setStCondFailures(unsigned sc_failures) 2972315SN/A { 2982680SN/A actualTC->setStCondFailures(sc_failures); 2992315SN/A } 3002315SN/A 3012315SN/A // @todo: Fix this! 3022680SN/A bool misspeculating() { return actualTC->misspeculating(); } 3032315SN/A 3042680SN/A Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 3052315SN/A}; 3062315SN/A 3072315SN/A#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ 308