thread_context.hh revision 2683
12330SN/A/*
22330SN/A * Copyright (c) 2006 The Regents of The University of Michigan
32330SN/A * All rights reserved.
42330SN/A *
52330SN/A * Redistribution and use in source and binary forms, with or without
62330SN/A * modification, are permitted provided that the following conditions are
72330SN/A * met: redistributions of source code must retain the above copyright
82330SN/A * notice, this list of conditions and the following disclaimer;
92330SN/A * redistributions in binary form must reproduce the above copyright
102330SN/A * notice, this list of conditions and the following disclaimer in the
112330SN/A * documentation and/or other materials provided with the distribution;
122330SN/A * neither the name of the copyright holders nor the names of its
132330SN/A * contributors may be used to endorse or promote products derived from
142330SN/A * this software without specific prior written permission.
152330SN/A *
162330SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172330SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182330SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192330SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202330SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212330SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222330SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232330SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242330SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252330SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262330SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272330SN/A */
282330SN/A
292683Sktlim@umich.edu#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
302683Sktlim@umich.edu#define __CPU_CHECKER_THREAD_CONTEXT_HH__
312315SN/A
322315SN/A#include "cpu/checker/cpu.hh"
332683Sktlim@umich.edu#include "cpu/simple_thread.hh"
342680SN/A#include "cpu/thread_context.hh"
352315SN/A
362315SN/Aclass EndQuiesceEvent;
372330SN/Anamespace Kernel {
382330SN/A    class Statistics;
392330SN/A};
402315SN/A
412350SN/A/**
422680SN/A * Derived ThreadContext class for use with the Checker.  The template
432680SN/A * parameter is the ThreadContext class used by the specific CPU being
442683Sktlim@umich.edu * verified.  This CheckerThreadContext is then used by the main CPU
452683Sktlim@umich.edu * in place of its usual ThreadContext class.  It handles updating the
462683Sktlim@umich.edu * checker's state any time state is updated externally through the
472683Sktlim@umich.edu * ThreadContext.
482350SN/A */
492680SN/Atemplate <class TC>
502680SN/Aclass CheckerThreadContext : public ThreadContext
512315SN/A{
522315SN/A  public:
532680SN/A    CheckerThreadContext(TC *actual_tc,
542683Sktlim@umich.edu                         CheckerCPU *checker_cpu)
552683Sktlim@umich.edu        : actualTC(actual_tc), checkerTC(checker_cpu->thread),
562330SN/A          checkerCPU(checker_cpu)
572315SN/A    { }
582315SN/A
592315SN/A  private:
602683Sktlim@umich.edu    /** The main CPU's ThreadContext, or class that implements the
612683Sktlim@umich.edu     * ThreadContext interface. */
622680SN/A    TC *actualTC;
632683Sktlim@umich.edu    /** The checker's own SimpleThread. Will be updated any time
642683Sktlim@umich.edu     * anything uses this ThreadContext to externally update a
652683Sktlim@umich.edu     * thread's state. */
662683Sktlim@umich.edu    SimpleThread *checkerTC;
672683Sktlim@umich.edu    /** Pointer to the checker CPU. */
682315SN/A    CheckerCPU *checkerCPU;
692315SN/A
702315SN/A  public:
712315SN/A
722680SN/A    BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
732315SN/A
742315SN/A    void setCpuId(int id)
752315SN/A    {
762680SN/A        actualTC->setCpuId(id);
772680SN/A        checkerTC->setCpuId(id);
782315SN/A    }
792315SN/A
802680SN/A    int readCpuId() { return actualTC->readCpuId(); }
812315SN/A
822680SN/A    TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
832315SN/A
842315SN/A#if FULL_SYSTEM
852680SN/A    System *getSystemPtr() { return actualTC->getSystemPtr(); }
862315SN/A
872680SN/A    PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
882315SN/A
892680SN/A    AlphaITB *getITBPtr() { return actualTC->getITBPtr(); }
902315SN/A
912680SN/A    AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); }
922330SN/A
932680SN/A    Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); }
942315SN/A#else
952680SN/A    Process *getProcessPtr() { return actualTC->getProcessPtr(); }
962315SN/A#endif
972315SN/A
982680SN/A    Status status() const { return actualTC->status(); }
992315SN/A
1002315SN/A    void setStatus(Status new_status)
1012330SN/A    {
1022680SN/A        actualTC->setStatus(new_status);
1032680SN/A        checkerTC->setStatus(new_status);
1042330SN/A    }
1052315SN/A
1062315SN/A    /// Set the status to Active.  Optional delay indicates number of
1072315SN/A    /// cycles to wait before beginning execution.
1082680SN/A    void activate(int delay = 1) { actualTC->activate(delay); }
1092315SN/A
1102315SN/A    /// Set the status to Suspended.
1112680SN/A    void suspend() { actualTC->suspend(); }
1122315SN/A
1132315SN/A    /// Set the status to Unallocated.
1142680SN/A    void deallocate() { actualTC->deallocate(); }
1152315SN/A
1162315SN/A    /// Set the status to Halted.
1172680SN/A    void halt() { actualTC->halt(); }
1182315SN/A
1192315SN/A#if FULL_SYSTEM
1202680SN/A    void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
1212315SN/A#endif
1222315SN/A
1232680SN/A    void takeOverFrom(ThreadContext *oldContext)
1242315SN/A    {
1252680SN/A        actualTC->takeOverFrom(oldContext);
1262680SN/A        checkerTC->takeOverFrom(oldContext);
1272315SN/A    }
1282315SN/A
1292680SN/A    void regStats(const std::string &name) { actualTC->regStats(name); }
1302315SN/A
1312680SN/A    void serialize(std::ostream &os) { actualTC->serialize(os); }
1322315SN/A    void unserialize(Checkpoint *cp, const std::string &section)
1332680SN/A    { actualTC->unserialize(cp, section); }
1342315SN/A
1352315SN/A#if FULL_SYSTEM
1362680SN/A    EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
1372315SN/A
1382680SN/A    Tick readLastActivate() { return actualTC->readLastActivate(); }
1392680SN/A    Tick readLastSuspend() { return actualTC->readLastSuspend(); }
1402315SN/A
1412680SN/A    void profileClear() { return actualTC->profileClear(); }
1422680SN/A    void profileSample() { return actualTC->profileSample(); }
1432315SN/A#endif
1442315SN/A
1452680SN/A    int getThreadNum() { return actualTC->getThreadNum(); }
1462315SN/A
1472315SN/A    // @todo: Do I need this?
1482680SN/A    MachInst getInst() { return actualTC->getInst(); }
1492315SN/A
1502315SN/A    // @todo: Do I need this?
1512680SN/A    void copyArchRegs(ThreadContext *tc)
1522315SN/A    {
1532680SN/A        actualTC->copyArchRegs(tc);
1542680SN/A        checkerTC->copyArchRegs(tc);
1552315SN/A    }
1562315SN/A
1572315SN/A    void clearArchRegs()
1582315SN/A    {
1592680SN/A        actualTC->clearArchRegs();
1602680SN/A        checkerTC->clearArchRegs();
1612315SN/A    }
1622315SN/A
1632315SN/A    //
1642315SN/A    // New accessors for new decoder.
1652315SN/A    //
1662315SN/A    uint64_t readIntReg(int reg_idx)
1672680SN/A    { return actualTC->readIntReg(reg_idx); }
1682315SN/A
1692669SN/A    FloatReg readFloatReg(int reg_idx, int width)
1702680SN/A    { return actualTC->readFloatReg(reg_idx, width); }
1712315SN/A
1722669SN/A    FloatReg readFloatReg(int reg_idx)
1732680SN/A    { return actualTC->readFloatReg(reg_idx); }
1742315SN/A
1752669SN/A    FloatRegBits readFloatRegBits(int reg_idx, int width)
1762680SN/A    { return actualTC->readFloatRegBits(reg_idx, width); }
1772669SN/A
1782669SN/A    FloatRegBits readFloatRegBits(int reg_idx)
1792680SN/A    { return actualTC->readFloatRegBits(reg_idx); }
1802315SN/A
1812315SN/A    void setIntReg(int reg_idx, uint64_t val)
1822315SN/A    {
1832680SN/A        actualTC->setIntReg(reg_idx, val);
1842680SN/A        checkerTC->setIntReg(reg_idx, val);
1852315SN/A    }
1862315SN/A
1872669SN/A    void setFloatReg(int reg_idx, FloatReg val, int width)
1882315SN/A    {
1892680SN/A        actualTC->setFloatReg(reg_idx, val, width);
1902680SN/A        checkerTC->setFloatReg(reg_idx, val, width);
1912315SN/A    }
1922315SN/A
1932669SN/A    void setFloatReg(int reg_idx, FloatReg val)
1942315SN/A    {
1952680SN/A        actualTC->setFloatReg(reg_idx, val);
1962680SN/A        checkerTC->setFloatReg(reg_idx, val);
1972315SN/A    }
1982315SN/A
1992669SN/A    void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
2002315SN/A    {
2012680SN/A        actualTC->setFloatRegBits(reg_idx, val, width);
2022680SN/A        checkerTC->setFloatRegBits(reg_idx, val, width);
2032669SN/A    }
2042669SN/A
2052669SN/A    void setFloatRegBits(int reg_idx, FloatRegBits val)
2062669SN/A    {
2072680SN/A        actualTC->setFloatRegBits(reg_idx, val);
2082680SN/A        checkerTC->setFloatRegBits(reg_idx, val);
2092315SN/A    }
2102315SN/A
2112680SN/A    uint64_t readPC() { return actualTC->readPC(); }
2122315SN/A
2132315SN/A    void setPC(uint64_t val)
2142315SN/A    {
2152680SN/A        actualTC->setPC(val);
2162680SN/A        checkerTC->setPC(val);
2172315SN/A        checkerCPU->recordPCChange(val);
2182315SN/A    }
2192315SN/A
2202680SN/A    uint64_t readNextPC() { return actualTC->readNextPC(); }
2212315SN/A
2222315SN/A    void setNextPC(uint64_t val)
2232315SN/A    {
2242680SN/A        actualTC->setNextPC(val);
2252680SN/A        checkerTC->setNextPC(val);
2262315SN/A        checkerCPU->recordNextPCChange(val);
2272315SN/A    }
2282315SN/A
2292680SN/A    uint64_t readNextNPC() { return actualTC->readNextNPC(); }
2302669SN/A
2312669SN/A    void setNextNPC(uint64_t val)
2322669SN/A    {
2332680SN/A        actualTC->setNextNPC(val);
2342680SN/A        checkerTC->setNextNPC(val);
2352669SN/A        checkerCPU->recordNextPCChange(val);
2362669SN/A    }
2372669SN/A
2382315SN/A    MiscReg readMiscReg(int misc_reg)
2392680SN/A    { return actualTC->readMiscReg(misc_reg); }
2402315SN/A
2412315SN/A    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
2422680SN/A    { return actualTC->readMiscRegWithEffect(misc_reg, fault); }
2432315SN/A
2442315SN/A    Fault setMiscReg(int misc_reg, const MiscReg &val)
2452315SN/A    {
2462680SN/A        checkerTC->setMiscReg(misc_reg, val);
2472680SN/A        return actualTC->setMiscReg(misc_reg, val);
2482315SN/A    }
2492315SN/A
2502315SN/A    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
2512315SN/A    {
2522680SN/A        checkerTC->setMiscRegWithEffect(misc_reg, val);
2532680SN/A        return actualTC->setMiscRegWithEffect(misc_reg, val);
2542315SN/A    }
2552315SN/A
2562315SN/A    unsigned readStCondFailures()
2572680SN/A    { return actualTC->readStCondFailures(); }
2582315SN/A
2592315SN/A    void setStCondFailures(unsigned sc_failures)
2602315SN/A    {
2612680SN/A        checkerTC->setStCondFailures(sc_failures);
2622680SN/A        actualTC->setStCondFailures(sc_failures);
2632315SN/A    }
2642315SN/A#if FULL_SYSTEM
2652680SN/A    bool inPalMode() { return actualTC->inPalMode(); }
2662315SN/A#endif
2672315SN/A
2682315SN/A    // @todo: Fix this!
2692680SN/A    bool misspeculating() { return actualTC->misspeculating(); }
2702315SN/A
2712315SN/A#if !FULL_SYSTEM
2722680SN/A    IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); }
2732315SN/A
2742315SN/A    // used to shift args for indirect syscall
2752315SN/A    void setSyscallArg(int i, IntReg val)
2762315SN/A    {
2772680SN/A        checkerTC->setSyscallArg(i, val);
2782680SN/A        actualTC->setSyscallArg(i, val);
2792315SN/A    }
2802315SN/A
2812315SN/A    void setSyscallReturn(SyscallReturn return_value)
2822315SN/A    {
2832680SN/A        checkerTC->setSyscallReturn(return_value);
2842680SN/A        actualTC->setSyscallReturn(return_value);
2852315SN/A    }
2862315SN/A
2872680SN/A    Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
2882315SN/A#endif
2892669SN/A    void changeRegFileContext(RegFile::ContextParam param,
2902669SN/A            RegFile::ContextVal val)
2912669SN/A    {
2922680SN/A        actualTC->changeRegFileContext(param, val);
2932680SN/A        checkerTC->changeRegFileContext(param, val);
2942669SN/A    }
2952315SN/A};
2962315SN/A
2972315SN/A#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
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