thread_context.hh revision 13693
12330SN/A/* 213610Sgiacomo.gabrielli@arm.com * Copyright (c) 2011-2012, 2016-2018 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152330SN/A * Copyright (c) 2006 The Regents of The University of Michigan 162330SN/A * All rights reserved. 172330SN/A * 182330SN/A * Redistribution and use in source and binary forms, with or without 192330SN/A * modification, are permitted provided that the following conditions are 202330SN/A * met: redistributions of source code must retain the above copyright 212330SN/A * notice, this list of conditions and the following disclaimer; 222330SN/A * redistributions in binary form must reproduce the above copyright 232330SN/A * notice, this list of conditions and the following disclaimer in the 242330SN/A * documentation and/or other materials provided with the distribution; 252330SN/A * neither the name of the copyright holders nor the names of its 262330SN/A * contributors may be used to endorse or promote products derived from 272330SN/A * this software without specific prior written permission. 282330SN/A * 292330SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302330SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312330SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322330SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332330SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342330SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352330SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362330SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372330SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382330SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392330SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Kevin Lim 422330SN/A */ 432330SN/A 442683Sktlim@umich.edu#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__ 452683Sktlim@umich.edu#define __CPU_CHECKER_THREAD_CONTEXT_HH__ 462315SN/A 472972Sgblack@eecs.umich.edu#include "arch/types.hh" 486658Snate@binkert.org#include "config/the_isa.hh" 492315SN/A#include "cpu/checker/cpu.hh" 502683Sktlim@umich.edu#include "cpu/simple_thread.hh" 512680SN/A#include "cpu/thread_context.hh" 528733Sgeoffrey.blake@arm.com#include "debug/Checker.hh" 532315SN/A 542315SN/Aclass EndQuiesceEvent; 553548Sgblack@eecs.umich.edunamespace TheISA { 563548Sgblack@eecs.umich.edu namespace Kernel { 573548Sgblack@eecs.umich.edu class Statistics; 583548Sgblack@eecs.umich.edu }; 599020Sgblack@eecs.umich.edu class Decoder; 602330SN/A}; 612315SN/A 622350SN/A/** 632680SN/A * Derived ThreadContext class for use with the Checker. The template 642680SN/A * parameter is the ThreadContext class used by the specific CPU being 652683Sktlim@umich.edu * verified. This CheckerThreadContext is then used by the main CPU 662683Sktlim@umich.edu * in place of its usual ThreadContext class. It handles updating the 672683Sktlim@umich.edu * checker's state any time state is updated externally through the 682683Sktlim@umich.edu * ThreadContext. 692350SN/A */ 702680SN/Atemplate <class TC> 712680SN/Aclass CheckerThreadContext : public ThreadContext 722315SN/A{ 732315SN/A public: 742680SN/A CheckerThreadContext(TC *actual_tc, 752683Sktlim@umich.edu CheckerCPU *checker_cpu) 762683Sktlim@umich.edu : actualTC(actual_tc), checkerTC(checker_cpu->thread), 772330SN/A checkerCPU(checker_cpu) 782315SN/A { } 792315SN/A 802315SN/A private: 812683Sktlim@umich.edu /** The main CPU's ThreadContext, or class that implements the 822683Sktlim@umich.edu * ThreadContext interface. */ 832680SN/A TC *actualTC; 842683Sktlim@umich.edu /** The checker's own SimpleThread. Will be updated any time 852683Sktlim@umich.edu * anything uses this ThreadContext to externally update a 862683Sktlim@umich.edu * thread's state. */ 872683Sktlim@umich.edu SimpleThread *checkerTC; 882683Sktlim@umich.edu /** Pointer to the checker CPU. */ 892315SN/A CheckerCPU *checkerCPU; 902315SN/A 912315SN/A public: 922315SN/A 9313628SAndrea.Mondelli@ucf.edu BaseCPU *getCpuPtr() override { return actualTC->getCpuPtr(); } 942315SN/A 9513628SAndrea.Mondelli@ucf.edu uint32_t socketId() const override { return actualTC->socketId(); } 9610190Sakash.bagdia@arm.com 9713628SAndrea.Mondelli@ucf.edu int cpuId() const override { return actualTC->cpuId(); } 988733Sgeoffrey.blake@arm.com 9913628SAndrea.Mondelli@ucf.edu ContextID contextId() const override { return actualTC->contextId(); } 1008733Sgeoffrey.blake@arm.com 10113628SAndrea.Mondelli@ucf.edu void setContextId(ContextID id)override 1022315SN/A { 1038733Sgeoffrey.blake@arm.com actualTC->setContextId(id); 1048733Sgeoffrey.blake@arm.com checkerTC->setContextId(id); 1052315SN/A } 1062315SN/A 1078733Sgeoffrey.blake@arm.com /** Returns this thread's ID number. */ 10813628SAndrea.Mondelli@ucf.edu int threadId() const override { return actualTC->threadId(); } 10913628SAndrea.Mondelli@ucf.edu void setThreadId(int id) override 1108733Sgeoffrey.blake@arm.com { 1118733Sgeoffrey.blake@arm.com checkerTC->setThreadId(id); 1128733Sgeoffrey.blake@arm.com actualTC->setThreadId(id); 1138733Sgeoffrey.blake@arm.com } 1142315SN/A 11513628SAndrea.Mondelli@ucf.edu BaseTLB *getITBPtr() override { return actualTC->getITBPtr(); } 1164997Sgblack@eecs.umich.edu 11713628SAndrea.Mondelli@ucf.edu BaseTLB *getDTBPtr() override { return actualTC->getDTBPtr(); } 1184997Sgblack@eecs.umich.edu 11913628SAndrea.Mondelli@ucf.edu CheckerCPU *getCheckerCpuPtr()override 1208887Sgeoffrey.blake@arm.com { 1218887Sgeoffrey.blake@arm.com return checkerCPU; 1228887Sgeoffrey.blake@arm.com } 1238733Sgeoffrey.blake@arm.com 12413693Sgiacomo.gabrielli@arm.com TheISA::ISA *getIsaPtr() override { return actualTC->getIsaPtr(); } 12513693Sgiacomo.gabrielli@arm.com 12613628SAndrea.Mondelli@ucf.edu TheISA::Decoder *getDecoderPtr() override { 12713628SAndrea.Mondelli@ucf.edu return actualTC->getDecoderPtr(); 12813628SAndrea.Mondelli@ucf.edu } 1298733Sgeoffrey.blake@arm.com 13013628SAndrea.Mondelli@ucf.edu System *getSystemPtr() override { return actualTC->getSystemPtr(); } 1312315SN/A 13213628SAndrea.Mondelli@ucf.edu TheISA::Kernel::Statistics *getKernelStats()override 1333548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 1342690Sktlim@umich.edu 13513628SAndrea.Mondelli@ucf.edu Process *getProcessPtr() override { return actualTC->getProcessPtr(); } 1367679Sgblack@eecs.umich.edu 13713628SAndrea.Mondelli@ucf.edu void setProcessPtr(Process *p) override { actualTC->setProcessPtr(p); } 13811886Sbrandon.potter@amd.com 13913628SAndrea.Mondelli@ucf.edu PortProxy &getPhysProxy() override { return actualTC->getPhysProxy(); } 1402690Sktlim@umich.edu 14113628SAndrea.Mondelli@ucf.edu FSTranslatingPortProxy &getVirtProxy() override 1428706Sandreas.hansson@arm.com { return actualTC->getVirtProxy(); } 1438733Sgeoffrey.blake@arm.com 14413628SAndrea.Mondelli@ucf.edu void initMemProxies(ThreadContext *tc) override 1458733Sgeoffrey.blake@arm.com { actualTC->initMemProxies(tc); } 1468733Sgeoffrey.blake@arm.com 1478733Sgeoffrey.blake@arm.com void connectMemPorts(ThreadContext *tc) 1488733Sgeoffrey.blake@arm.com { 1498733Sgeoffrey.blake@arm.com actualTC->connectMemPorts(tc); 1508733Sgeoffrey.blake@arm.com } 1518809Sgblack@eecs.umich.edu 15213628SAndrea.Mondelli@ucf.edu SETranslatingPortProxy &getMemProxy() override { 15313628SAndrea.Mondelli@ucf.edu return actualTC->getMemProxy(); 15413628SAndrea.Mondelli@ucf.edu } 1552690Sktlim@umich.edu 1568733Sgeoffrey.blake@arm.com /** Executes a syscall in SE mode. */ 15713628SAndrea.Mondelli@ucf.edu void syscall(int64_t callnum, Fault *fault)override 15811877Sbrandon.potter@amd.com { return actualTC->syscall(callnum, fault); } 1592315SN/A 16013628SAndrea.Mondelli@ucf.edu Status status() const override { return actualTC->status(); } 1612315SN/A 16213628SAndrea.Mondelli@ucf.edu void setStatus(Status new_status) override 1632330SN/A { 1642680SN/A actualTC->setStatus(new_status); 1652680SN/A checkerTC->setStatus(new_status); 1662330SN/A } 1672315SN/A 16810407Smitch.hayenga@arm.com /// Set the status to Active. 16913628SAndrea.Mondelli@ucf.edu void activate() override { actualTC->activate(); } 1702315SN/A 1712315SN/A /// Set the status to Suspended. 17213628SAndrea.Mondelli@ucf.edu void suspend() override{ actualTC->suspend(); } 1732315SN/A 1742315SN/A /// Set the status to Halted. 17513628SAndrea.Mondelli@ucf.edu void halt() override{ actualTC->halt(); } 1762315SN/A 17713628SAndrea.Mondelli@ucf.edu void dumpFuncProfile() override{ actualTC->dumpFuncProfile(); } 1782315SN/A 17913628SAndrea.Mondelli@ucf.edu void takeOverFrom(ThreadContext *oldContext) override 1802315SN/A { 1812680SN/A actualTC->takeOverFrom(oldContext); 1823225Sktlim@umich.edu checkerTC->copyState(oldContext); 1832315SN/A } 1842315SN/A 18513628SAndrea.Mondelli@ucf.edu void regStats(const std::string &name) override 1868733Sgeoffrey.blake@arm.com { 1878733Sgeoffrey.blake@arm.com actualTC->regStats(name); 1888733Sgeoffrey.blake@arm.com checkerTC->regStats(name); 1898733Sgeoffrey.blake@arm.com } 1902315SN/A 19113628SAndrea.Mondelli@ucf.edu EndQuiesceEvent *getQuiesceEvent() override { 19213628SAndrea.Mondelli@ucf.edu return actualTC->getQuiesceEvent(); 19313628SAndrea.Mondelli@ucf.edu } 1942315SN/A 19513628SAndrea.Mondelli@ucf.edu Tick readLastActivate() override{ return actualTC->readLastActivate(); } 19613628SAndrea.Mondelli@ucf.edu Tick readLastSuspend() override{ return actualTC->readLastSuspend(); } 1972315SN/A 19813628SAndrea.Mondelli@ucf.edu void profileClear() override{ return actualTC->profileClear(); } 19913628SAndrea.Mondelli@ucf.edu void profileSample() override{ return actualTC->profileSample(); } 2002315SN/A 2012315SN/A // @todo: Do I need this? 20213628SAndrea.Mondelli@ucf.edu void copyArchRegs(ThreadContext *tc) override 2032315SN/A { 2042680SN/A actualTC->copyArchRegs(tc); 2052680SN/A checkerTC->copyArchRegs(tc); 2062315SN/A } 2072315SN/A 20813628SAndrea.Mondelli@ucf.edu void clearArchRegs() override 2092315SN/A { 2102680SN/A actualTC->clearArchRegs(); 2112680SN/A checkerTC->clearArchRegs(); 2122315SN/A } 2132315SN/A 2142315SN/A // 2152315SN/A // New accessors for new decoder. 2162315SN/A // 21713628SAndrea.Mondelli@ucf.edu RegVal readIntReg(int reg_idx) override { 21813628SAndrea.Mondelli@ucf.edu return actualTC->readIntReg(reg_idx); 21913628SAndrea.Mondelli@ucf.edu } 2202315SN/A 22113557Sgabeblack@google.com RegVal 22213628SAndrea.Mondelli@ucf.edu readFloatReg(int reg_idx) override 22313557Sgabeblack@google.com { 22413611Sgabeblack@google.com return actualTC->readFloatReg(reg_idx); 22513557Sgabeblack@google.com } 2262315SN/A 22713628SAndrea.Mondelli@ucf.edu const VecRegContainer& readVecReg (const RegId& reg) const override 22812109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVecReg(reg); } 22912109SRekai.GonzalezAlberquilla@arm.com 23012109SRekai.GonzalezAlberquilla@arm.com /** 23112109SRekai.GonzalezAlberquilla@arm.com * Read vector register for modification, hierarchical indexing. 23212109SRekai.GonzalezAlberquilla@arm.com */ 23313628SAndrea.Mondelli@ucf.edu VecRegContainer& getWritableVecReg (const RegId& reg) override 23412109SRekai.GonzalezAlberquilla@arm.com { return actualTC->getWritableVecReg(reg); } 23512109SRekai.GonzalezAlberquilla@arm.com 23612109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 23712109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 23812109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 23912109SRekai.GonzalezAlberquilla@arm.com ConstVecLane8 24013628SAndrea.Mondelli@ucf.edu readVec8BitLaneReg(const RegId& reg) const override 24112109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVec8BitLaneReg(reg); } 24212109SRekai.GonzalezAlberquilla@arm.com 24312109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 24412109SRekai.GonzalezAlberquilla@arm.com ConstVecLane16 24513628SAndrea.Mondelli@ucf.edu readVec16BitLaneReg(const RegId& reg) const override 24612109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVec16BitLaneReg(reg); } 24712109SRekai.GonzalezAlberquilla@arm.com 24812109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 24912109SRekai.GonzalezAlberquilla@arm.com ConstVecLane32 25013628SAndrea.Mondelli@ucf.edu readVec32BitLaneReg(const RegId& reg) const override 25112109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVec32BitLaneReg(reg); } 25212109SRekai.GonzalezAlberquilla@arm.com 25312109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 25412109SRekai.GonzalezAlberquilla@arm.com ConstVecLane64 25513628SAndrea.Mondelli@ucf.edu readVec64BitLaneReg(const RegId& reg) const override 25612109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVec64BitLaneReg(reg); } 25712109SRekai.GonzalezAlberquilla@arm.com 25812109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 25912109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 26013628SAndrea.Mondelli@ucf.edu const LaneData<LaneSize::Byte>& val) override 26112109SRekai.GonzalezAlberquilla@arm.com { return actualTC->setVecLane(reg, val); } 26212109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 26313628SAndrea.Mondelli@ucf.edu const LaneData<LaneSize::TwoByte>& val) override 26412109SRekai.GonzalezAlberquilla@arm.com { return actualTC->setVecLane(reg, val); } 26512109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 26613628SAndrea.Mondelli@ucf.edu const LaneData<LaneSize::FourByte>& val) override 26712109SRekai.GonzalezAlberquilla@arm.com { return actualTC->setVecLane(reg, val); } 26812109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 26913628SAndrea.Mondelli@ucf.edu const LaneData<LaneSize::EightByte>& val) override 27012109SRekai.GonzalezAlberquilla@arm.com { return actualTC->setVecLane(reg, val); } 27112109SRekai.GonzalezAlberquilla@arm.com /** @} */ 27212109SRekai.GonzalezAlberquilla@arm.com 27313628SAndrea.Mondelli@ucf.edu const VecElem& readVecElem(const RegId& reg) const override 27412109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVecElem(reg); } 27512109SRekai.GonzalezAlberquilla@arm.com 27613610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& readVecPredReg(const RegId& reg) const override 27713610Sgiacomo.gabrielli@arm.com { return actualTC->readVecPredReg(reg); } 27813610Sgiacomo.gabrielli@arm.com 27913610Sgiacomo.gabrielli@arm.com VecPredRegContainer& getWritableVecPredReg(const RegId& reg) override 28013610Sgiacomo.gabrielli@arm.com { return actualTC->getWritableVecPredReg(reg); } 28113610Sgiacomo.gabrielli@arm.com 28213628SAndrea.Mondelli@ucf.edu RegVal readCCReg(int reg_idx) override 2839920Syasuko.eckert@amd.com { return actualTC->readCCReg(reg_idx); } 2849920Syasuko.eckert@amd.com 28513557Sgabeblack@google.com void 28613628SAndrea.Mondelli@ucf.edu setIntReg(int reg_idx, RegVal val) override 2872315SN/A { 2882680SN/A actualTC->setIntReg(reg_idx, val); 2892680SN/A checkerTC->setIntReg(reg_idx, val); 2902315SN/A } 2912315SN/A 29213557Sgabeblack@google.com void 29313628SAndrea.Mondelli@ucf.edu setFloatReg(int reg_idx, RegVal val) override 2942669SN/A { 29513611Sgabeblack@google.com actualTC->setFloatReg(reg_idx, val); 29613611Sgabeblack@google.com checkerTC->setFloatReg(reg_idx, val); 2972315SN/A } 2982315SN/A 29913557Sgabeblack@google.com void 30013628SAndrea.Mondelli@ucf.edu setVecReg(const RegId& reg, const VecRegContainer& val) override 30112109SRekai.GonzalezAlberquilla@arm.com { 30212109SRekai.GonzalezAlberquilla@arm.com actualTC->setVecReg(reg, val); 30312109SRekai.GonzalezAlberquilla@arm.com checkerTC->setVecReg(reg, val); 30412109SRekai.GonzalezAlberquilla@arm.com } 30512109SRekai.GonzalezAlberquilla@arm.com 30613557Sgabeblack@google.com void 30713628SAndrea.Mondelli@ucf.edu setVecElem(const RegId& reg, const VecElem& val) override 30812109SRekai.GonzalezAlberquilla@arm.com { 30912109SRekai.GonzalezAlberquilla@arm.com actualTC->setVecElem(reg, val); 31012109SRekai.GonzalezAlberquilla@arm.com checkerTC->setVecElem(reg, val); 31112109SRekai.GonzalezAlberquilla@arm.com } 31212109SRekai.GonzalezAlberquilla@arm.com 31313557Sgabeblack@google.com void 31413628SAndrea.Mondelli@ucf.edu setVecPredReg(const RegId& reg, const VecPredRegContainer& val) override 31513610Sgiacomo.gabrielli@arm.com { 31613610Sgiacomo.gabrielli@arm.com actualTC->setVecPredReg(reg, val); 31713610Sgiacomo.gabrielli@arm.com checkerTC->setVecPredReg(reg, val); 31813610Sgiacomo.gabrielli@arm.com } 31913610Sgiacomo.gabrielli@arm.com 32013610Sgiacomo.gabrielli@arm.com void 32113628SAndrea.Mondelli@ucf.edu setCCReg(int reg_idx, RegVal val) override 3229920Syasuko.eckert@amd.com { 3239920Syasuko.eckert@amd.com actualTC->setCCReg(reg_idx, val); 3249920Syasuko.eckert@amd.com checkerTC->setCCReg(reg_idx, val); 3259920Syasuko.eckert@amd.com } 3269920Syasuko.eckert@amd.com 3278733Sgeoffrey.blake@arm.com /** Reads this thread's PC state. */ 32813628SAndrea.Mondelli@ucf.edu TheISA::PCState pcState() override 3298733Sgeoffrey.blake@arm.com { return actualTC->pcState(); } 3302315SN/A 3318733Sgeoffrey.blake@arm.com /** Sets this thread's PC state. */ 33213557Sgabeblack@google.com void 33313628SAndrea.Mondelli@ucf.edu pcState(const TheISA::PCState &val) override 3342315SN/A { 3358733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Changing PC to %s, old PC %s\n", 3368733Sgeoffrey.blake@arm.com val, checkerTC->pcState()); 3378733Sgeoffrey.blake@arm.com checkerTC->pcState(val); 3382315SN/A checkerCPU->recordPCChange(val); 3398733Sgeoffrey.blake@arm.com return actualTC->pcState(val); 3402315SN/A } 3412315SN/A 34213557Sgabeblack@google.com void 34313557Sgabeblack@google.com setNPC(Addr val) 34411886Sbrandon.potter@amd.com { 34511886Sbrandon.potter@amd.com checkerTC->setNPC(val); 34611886Sbrandon.potter@amd.com actualTC->setNPC(val); 34711886Sbrandon.potter@amd.com } 34811886Sbrandon.potter@amd.com 34913557Sgabeblack@google.com void 35013628SAndrea.Mondelli@ucf.edu pcStateNoRecord(const TheISA::PCState &val) override 3512315SN/A { 3528733Sgeoffrey.blake@arm.com return actualTC->pcState(val); 3532315SN/A } 3542315SN/A 3558733Sgeoffrey.blake@arm.com /** Reads this thread's PC. */ 35613628SAndrea.Mondelli@ucf.edu Addr instAddr() override 3578733Sgeoffrey.blake@arm.com { return actualTC->instAddr(); } 3582669SN/A 3598733Sgeoffrey.blake@arm.com /** Reads this thread's next PC. */ 36013628SAndrea.Mondelli@ucf.edu Addr nextInstAddr() override 3618733Sgeoffrey.blake@arm.com { return actualTC->nextInstAddr(); } 3628733Sgeoffrey.blake@arm.com 3638733Sgeoffrey.blake@arm.com /** Reads this thread's next PC. */ 36413628SAndrea.Mondelli@ucf.edu MicroPC microPC() override 3658733Sgeoffrey.blake@arm.com { return actualTC->microPC(); } 3662669SN/A 36713628SAndrea.Mondelli@ucf.edu RegVal readMiscRegNoEffect(int misc_reg) const override 3684172Ssaidi@eecs.umich.edu { return actualTC->readMiscRegNoEffect(misc_reg); } 3694172Ssaidi@eecs.umich.edu 37013628SAndrea.Mondelli@ucf.edu RegVal readMiscReg(int misc_reg) override 3712680SN/A { return actualTC->readMiscReg(misc_reg); } 3722315SN/A 37313557Sgabeblack@google.com void 37413628SAndrea.Mondelli@ucf.edu setMiscRegNoEffect(int misc_reg, RegVal val) override 3754172Ssaidi@eecs.umich.edu { 3768733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker" 3778733Sgeoffrey.blake@arm.com " and O3..\n", misc_reg); 3784172Ssaidi@eecs.umich.edu checkerTC->setMiscRegNoEffect(misc_reg, val); 3794172Ssaidi@eecs.umich.edu actualTC->setMiscRegNoEffect(misc_reg, val); 3804172Ssaidi@eecs.umich.edu } 3812315SN/A 38213557Sgabeblack@google.com void 38313628SAndrea.Mondelli@ucf.edu setMiscReg(int misc_reg, RegVal val) override 3842315SN/A { 3858733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker" 3868733Sgeoffrey.blake@arm.com " and O3..\n", misc_reg); 3872680SN/A checkerTC->setMiscReg(misc_reg, val); 3883468Sgblack@eecs.umich.edu actualTC->setMiscReg(misc_reg, val); 3892315SN/A } 3902315SN/A 39113557Sgabeblack@google.com RegId 39213628SAndrea.Mondelli@ucf.edu flattenRegId(const RegId& regId) const override 39313557Sgabeblack@google.com { 39412106SRekai.GonzalezAlberquilla@arm.com return actualTC->flattenRegId(regId); 39512106SRekai.GonzalezAlberquilla@arm.com } 3968733Sgeoffrey.blake@arm.com 39713628SAndrea.Mondelli@ucf.edu unsigned readStCondFailures() override 3982680SN/A { return actualTC->readStCondFailures(); } 3992315SN/A 40013557Sgabeblack@google.com void 40113628SAndrea.Mondelli@ucf.edu setStCondFailures(unsigned sc_failures) override 4022315SN/A { 4032680SN/A actualTC->setStCondFailures(sc_failures); 4042315SN/A } 4052315SN/A 40613628SAndrea.Mondelli@ucf.edu Counter readFuncExeInst() override { return actualTC->readFuncExeInst(); } 4079426SAndreas.Sandberg@ARM.com 40813628SAndrea.Mondelli@ucf.edu RegVal readIntRegFlat(int idx) override { 40913628SAndrea.Mondelli@ucf.edu return actualTC->readIntRegFlat(idx); 41013628SAndrea.Mondelli@ucf.edu } 4119426SAndreas.Sandberg@ARM.com 41213557Sgabeblack@google.com void 41313628SAndrea.Mondelli@ucf.edu setIntRegFlat(int idx, RegVal val) override 41413557Sgabeblack@google.com { 41513557Sgabeblack@google.com actualTC->setIntRegFlat(idx, val); 41613557Sgabeblack@google.com } 4179426SAndreas.Sandberg@ARM.com 41813557Sgabeblack@google.com RegVal 41913628SAndrea.Mondelli@ucf.edu readFloatRegFlat(int idx) override 42013557Sgabeblack@google.com { 42113611Sgabeblack@google.com return actualTC->readFloatRegFlat(idx); 42213557Sgabeblack@google.com } 4239426SAndreas.Sandberg@ARM.com 42413557Sgabeblack@google.com void 42513628SAndrea.Mondelli@ucf.edu setFloatRegFlat(int idx, RegVal val) override 42613557Sgabeblack@google.com { 42713611Sgabeblack@google.com actualTC->setFloatRegFlat(idx, val); 42813557Sgabeblack@google.com } 4299920Syasuko.eckert@amd.com 43013557Sgabeblack@google.com const VecRegContainer & 43113628SAndrea.Mondelli@ucf.edu readVecRegFlat(int idx) const override 43213557Sgabeblack@google.com { 43313557Sgabeblack@google.com return actualTC->readVecRegFlat(idx); 43413557Sgabeblack@google.com } 43512109SRekai.GonzalezAlberquilla@arm.com 43612109SRekai.GonzalezAlberquilla@arm.com /** 43712109SRekai.GonzalezAlberquilla@arm.com * Read vector register for modification, flat indexing. 43812109SRekai.GonzalezAlberquilla@arm.com */ 43913557Sgabeblack@google.com VecRegContainer & 44013628SAndrea.Mondelli@ucf.edu getWritableVecRegFlat(int idx) override 44113557Sgabeblack@google.com { 44213557Sgabeblack@google.com return actualTC->getWritableVecRegFlat(idx); 44313557Sgabeblack@google.com } 44412109SRekai.GonzalezAlberquilla@arm.com 44513628SAndrea.Mondelli@ucf.edu void setVecRegFlat(int idx, const VecRegContainer& val) override 44612109SRekai.GonzalezAlberquilla@arm.com { actualTC->setVecRegFlat(idx, val); } 44712109SRekai.GonzalezAlberquilla@arm.com 44812109SRekai.GonzalezAlberquilla@arm.com const VecElem& readVecElemFlat(const RegIndex& idx, 44913628SAndrea.Mondelli@ucf.edu const ElemIndex& elem_idx) const override 45012109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVecElemFlat(idx, elem_idx); } 45112109SRekai.GonzalezAlberquilla@arm.com 45212109SRekai.GonzalezAlberquilla@arm.com void setVecElemFlat(const RegIndex& idx, 45313628SAndrea.Mondelli@ucf.edu const ElemIndex& elem_idx, const VecElem& val) override 45412109SRekai.GonzalezAlberquilla@arm.com { actualTC->setVecElemFlat(idx, elem_idx, val); } 45512109SRekai.GonzalezAlberquilla@arm.com 45613610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& readVecPredRegFlat(int idx) const override 45713610Sgiacomo.gabrielli@arm.com { return actualTC->readVecPredRegFlat(idx); } 45813610Sgiacomo.gabrielli@arm.com 45913610Sgiacomo.gabrielli@arm.com VecPredRegContainer& getWritableVecPredRegFlat(int idx) override 46013610Sgiacomo.gabrielli@arm.com { return actualTC->getWritableVecPredRegFlat(idx); } 46113610Sgiacomo.gabrielli@arm.com 46213610Sgiacomo.gabrielli@arm.com void setVecPredRegFlat(int idx, const VecPredRegContainer& val) override 46313610Sgiacomo.gabrielli@arm.com { actualTC->setVecPredRegFlat(idx, val); } 46413610Sgiacomo.gabrielli@arm.com 46513628SAndrea.Mondelli@ucf.edu RegVal readCCRegFlat(int idx) override 4669920Syasuko.eckert@amd.com { return actualTC->readCCRegFlat(idx); } 4679920Syasuko.eckert@amd.com 46813628SAndrea.Mondelli@ucf.edu void setCCRegFlat(int idx, RegVal val) override 4699920Syasuko.eckert@amd.com { actualTC->setCCRegFlat(idx, val); } 4702315SN/A}; 4712315SN/A 4722315SN/A#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ 473