thread_context.hh revision 13611
12330SN/A/* 213610Sgiacomo.gabrielli@arm.com * Copyright (c) 2011-2012, 2016-2018 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152330SN/A * Copyright (c) 2006 The Regents of The University of Michigan 162330SN/A * All rights reserved. 172330SN/A * 182330SN/A * Redistribution and use in source and binary forms, with or without 192330SN/A * modification, are permitted provided that the following conditions are 202330SN/A * met: redistributions of source code must retain the above copyright 212330SN/A * notice, this list of conditions and the following disclaimer; 222330SN/A * redistributions in binary form must reproduce the above copyright 232330SN/A * notice, this list of conditions and the following disclaimer in the 242330SN/A * documentation and/or other materials provided with the distribution; 252330SN/A * neither the name of the copyright holders nor the names of its 262330SN/A * contributors may be used to endorse or promote products derived from 272330SN/A * this software without specific prior written permission. 282330SN/A * 292330SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302330SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312330SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322330SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332330SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342330SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352330SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362330SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372330SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382330SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392330SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Kevin Lim 422330SN/A */ 432330SN/A 442683Sktlim@umich.edu#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__ 452683Sktlim@umich.edu#define __CPU_CHECKER_THREAD_CONTEXT_HH__ 462315SN/A 472972Sgblack@eecs.umich.edu#include "arch/types.hh" 486658Snate@binkert.org#include "config/the_isa.hh" 492315SN/A#include "cpu/checker/cpu.hh" 502683Sktlim@umich.edu#include "cpu/simple_thread.hh" 512680SN/A#include "cpu/thread_context.hh" 528733Sgeoffrey.blake@arm.com#include "debug/Checker.hh" 532315SN/A 542315SN/Aclass EndQuiesceEvent; 553548Sgblack@eecs.umich.edunamespace TheISA { 563548Sgblack@eecs.umich.edu namespace Kernel { 573548Sgblack@eecs.umich.edu class Statistics; 583548Sgblack@eecs.umich.edu }; 599020Sgblack@eecs.umich.edu class Decoder; 602330SN/A}; 612315SN/A 622350SN/A/** 632680SN/A * Derived ThreadContext class for use with the Checker. The template 642680SN/A * parameter is the ThreadContext class used by the specific CPU being 652683Sktlim@umich.edu * verified. This CheckerThreadContext is then used by the main CPU 662683Sktlim@umich.edu * in place of its usual ThreadContext class. It handles updating the 672683Sktlim@umich.edu * checker's state any time state is updated externally through the 682683Sktlim@umich.edu * ThreadContext. 692350SN/A */ 702680SN/Atemplate <class TC> 712680SN/Aclass CheckerThreadContext : public ThreadContext 722315SN/A{ 732315SN/A public: 742680SN/A CheckerThreadContext(TC *actual_tc, 752683Sktlim@umich.edu CheckerCPU *checker_cpu) 762683Sktlim@umich.edu : actualTC(actual_tc), checkerTC(checker_cpu->thread), 772330SN/A checkerCPU(checker_cpu) 782315SN/A { } 792315SN/A 802315SN/A private: 812683Sktlim@umich.edu /** The main CPU's ThreadContext, or class that implements the 822683Sktlim@umich.edu * ThreadContext interface. */ 832680SN/A TC *actualTC; 842683Sktlim@umich.edu /** The checker's own SimpleThread. Will be updated any time 852683Sktlim@umich.edu * anything uses this ThreadContext to externally update a 862683Sktlim@umich.edu * thread's state. */ 872683Sktlim@umich.edu SimpleThread *checkerTC; 882683Sktlim@umich.edu /** Pointer to the checker CPU. */ 892315SN/A CheckerCPU *checkerCPU; 902315SN/A 912315SN/A public: 922315SN/A 932680SN/A BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 942315SN/A 9510190Sakash.bagdia@arm.com uint32_t socketId() const { return actualTC->socketId(); } 9610190Sakash.bagdia@arm.com 9710110Sandreas.hansson@arm.com int cpuId() const { return actualTC->cpuId(); } 988733Sgeoffrey.blake@arm.com 9911005Sandreas.sandberg@arm.com ContextID contextId() const { return actualTC->contextId(); } 1008733Sgeoffrey.blake@arm.com 10111005Sandreas.sandberg@arm.com void setContextId(ContextID id) 1022315SN/A { 1038733Sgeoffrey.blake@arm.com actualTC->setContextId(id); 1048733Sgeoffrey.blake@arm.com checkerTC->setContextId(id); 1052315SN/A } 1062315SN/A 1078733Sgeoffrey.blake@arm.com /** Returns this thread's ID number. */ 10810110Sandreas.hansson@arm.com int threadId() const { return actualTC->threadId(); } 1098733Sgeoffrey.blake@arm.com void setThreadId(int id) 1108733Sgeoffrey.blake@arm.com { 1118733Sgeoffrey.blake@arm.com checkerTC->setThreadId(id); 1128733Sgeoffrey.blake@arm.com actualTC->setThreadId(id); 1138733Sgeoffrey.blake@arm.com } 1142315SN/A 11512406Sgabeblack@google.com BaseTLB *getITBPtr() { return actualTC->getITBPtr(); } 1164997Sgblack@eecs.umich.edu 11712406Sgabeblack@google.com BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); } 1184997Sgblack@eecs.umich.edu 1198887Sgeoffrey.blake@arm.com CheckerCPU *getCheckerCpuPtr() 1208887Sgeoffrey.blake@arm.com { 1218887Sgeoffrey.blake@arm.com return checkerCPU; 1228887Sgeoffrey.blake@arm.com } 1238733Sgeoffrey.blake@arm.com 1249020Sgblack@eecs.umich.edu TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 1258733Sgeoffrey.blake@arm.com 1262680SN/A System *getSystemPtr() { return actualTC->getSystemPtr(); } 1272315SN/A 1283548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() 1293548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 1302690Sktlim@umich.edu 1317679Sgblack@eecs.umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 1327679Sgblack@eecs.umich.edu 13311886Sbrandon.potter@amd.com void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); } 13411886Sbrandon.potter@amd.com 1358852Sandreas.hansson@arm.com PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); } 1362690Sktlim@umich.edu 1378852Sandreas.hansson@arm.com FSTranslatingPortProxy &getVirtProxy() 1388706Sandreas.hansson@arm.com { return actualTC->getVirtProxy(); } 1398733Sgeoffrey.blake@arm.com 1408733Sgeoffrey.blake@arm.com void initMemProxies(ThreadContext *tc) 1418733Sgeoffrey.blake@arm.com { actualTC->initMemProxies(tc); } 1428733Sgeoffrey.blake@arm.com 1438733Sgeoffrey.blake@arm.com void connectMemPorts(ThreadContext *tc) 1448733Sgeoffrey.blake@arm.com { 1458733Sgeoffrey.blake@arm.com actualTC->connectMemPorts(tc); 1468733Sgeoffrey.blake@arm.com } 1478809Sgblack@eecs.umich.edu 1488852Sandreas.hansson@arm.com SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); } 1492690Sktlim@umich.edu 1508733Sgeoffrey.blake@arm.com /** Executes a syscall in SE mode. */ 15111877Sbrandon.potter@amd.com void syscall(int64_t callnum, Fault *fault) 15211877Sbrandon.potter@amd.com { return actualTC->syscall(callnum, fault); } 1532315SN/A 1542680SN/A Status status() const { return actualTC->status(); } 1552315SN/A 1562315SN/A void setStatus(Status new_status) 1572330SN/A { 1582680SN/A actualTC->setStatus(new_status); 1592680SN/A checkerTC->setStatus(new_status); 1602330SN/A } 1612315SN/A 16210407Smitch.hayenga@arm.com /// Set the status to Active. 16310407Smitch.hayenga@arm.com void activate() { actualTC->activate(); } 1642315SN/A 1652315SN/A /// Set the status to Suspended. 16610407Smitch.hayenga@arm.com void suspend() { actualTC->suspend(); } 1672315SN/A 1682315SN/A /// Set the status to Halted. 16910407Smitch.hayenga@arm.com void halt() { actualTC->halt(); } 1702315SN/A 1712680SN/A void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 1722315SN/A 1732680SN/A void takeOverFrom(ThreadContext *oldContext) 1742315SN/A { 1752680SN/A actualTC->takeOverFrom(oldContext); 1763225Sktlim@umich.edu checkerTC->copyState(oldContext); 1772315SN/A } 1782315SN/A 1798733Sgeoffrey.blake@arm.com void regStats(const std::string &name) 1808733Sgeoffrey.blake@arm.com { 1818733Sgeoffrey.blake@arm.com actualTC->regStats(name); 1828733Sgeoffrey.blake@arm.com checkerTC->regStats(name); 1838733Sgeoffrey.blake@arm.com } 1842315SN/A 1852680SN/A EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 1862315SN/A 1872680SN/A Tick readLastActivate() { return actualTC->readLastActivate(); } 1882680SN/A Tick readLastSuspend() { return actualTC->readLastSuspend(); } 1892315SN/A 1902680SN/A void profileClear() { return actualTC->profileClear(); } 1912680SN/A void profileSample() { return actualTC->profileSample(); } 1922315SN/A 1932315SN/A // @todo: Do I need this? 1942680SN/A void copyArchRegs(ThreadContext *tc) 1952315SN/A { 1962680SN/A actualTC->copyArchRegs(tc); 1972680SN/A checkerTC->copyArchRegs(tc); 1982315SN/A } 1992315SN/A 2002315SN/A void clearArchRegs() 2012315SN/A { 2022680SN/A actualTC->clearArchRegs(); 2032680SN/A checkerTC->clearArchRegs(); 2042315SN/A } 2052315SN/A 2062315SN/A // 2072315SN/A // New accessors for new decoder. 2082315SN/A // 20913557Sgabeblack@google.com RegVal readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); } 2102315SN/A 21113557Sgabeblack@google.com RegVal 21213611Sgabeblack@google.com readFloatReg(int reg_idx) 21313557Sgabeblack@google.com { 21413611Sgabeblack@google.com return actualTC->readFloatReg(reg_idx); 21513557Sgabeblack@google.com } 2162315SN/A 21712109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& readVecReg(const RegId& reg) const 21812109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVecReg(reg); } 21912109SRekai.GonzalezAlberquilla@arm.com 22012109SRekai.GonzalezAlberquilla@arm.com /** 22112109SRekai.GonzalezAlberquilla@arm.com * Read vector register for modification, hierarchical indexing. 22212109SRekai.GonzalezAlberquilla@arm.com */ 22312109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& getWritableVecReg(const RegId& reg) 22412109SRekai.GonzalezAlberquilla@arm.com { return actualTC->getWritableVecReg(reg); } 22512109SRekai.GonzalezAlberquilla@arm.com 22612109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 22712109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 22812109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 22912109SRekai.GonzalezAlberquilla@arm.com ConstVecLane8 23012109SRekai.GonzalezAlberquilla@arm.com readVec8BitLaneReg(const RegId& reg) const 23112109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVec8BitLaneReg(reg); } 23212109SRekai.GonzalezAlberquilla@arm.com 23312109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 23412109SRekai.GonzalezAlberquilla@arm.com ConstVecLane16 23512109SRekai.GonzalezAlberquilla@arm.com readVec16BitLaneReg(const RegId& reg) const 23612109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVec16BitLaneReg(reg); } 23712109SRekai.GonzalezAlberquilla@arm.com 23812109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 23912109SRekai.GonzalezAlberquilla@arm.com ConstVecLane32 24012109SRekai.GonzalezAlberquilla@arm.com readVec32BitLaneReg(const RegId& reg) const 24112109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVec32BitLaneReg(reg); } 24212109SRekai.GonzalezAlberquilla@arm.com 24312109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 24412109SRekai.GonzalezAlberquilla@arm.com ConstVecLane64 24512109SRekai.GonzalezAlberquilla@arm.com readVec64BitLaneReg(const RegId& reg) const 24612109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVec64BitLaneReg(reg); } 24712109SRekai.GonzalezAlberquilla@arm.com 24812109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 24912109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 25012109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) 25112109SRekai.GonzalezAlberquilla@arm.com { return actualTC->setVecLane(reg, val); } 25212109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 25312109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) 25412109SRekai.GonzalezAlberquilla@arm.com { return actualTC->setVecLane(reg, val); } 25512109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 25612109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) 25712109SRekai.GonzalezAlberquilla@arm.com { return actualTC->setVecLane(reg, val); } 25812109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 25912109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) 26012109SRekai.GonzalezAlberquilla@arm.com { return actualTC->setVecLane(reg, val); } 26112109SRekai.GonzalezAlberquilla@arm.com /** @} */ 26212109SRekai.GonzalezAlberquilla@arm.com 26312109SRekai.GonzalezAlberquilla@arm.com const VecElem& readVecElem(const RegId& reg) const 26412109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVecElem(reg); } 26512109SRekai.GonzalezAlberquilla@arm.com 26613610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& readVecPredReg(const RegId& reg) const override 26713610Sgiacomo.gabrielli@arm.com { return actualTC->readVecPredReg(reg); } 26813610Sgiacomo.gabrielli@arm.com 26913610Sgiacomo.gabrielli@arm.com VecPredRegContainer& getWritableVecPredReg(const RegId& reg) override 27013610Sgiacomo.gabrielli@arm.com { return actualTC->getWritableVecPredReg(reg); } 27113610Sgiacomo.gabrielli@arm.com 2729920Syasuko.eckert@amd.com CCReg readCCReg(int reg_idx) 2739920Syasuko.eckert@amd.com { return actualTC->readCCReg(reg_idx); } 2749920Syasuko.eckert@amd.com 27513557Sgabeblack@google.com void 27613557Sgabeblack@google.com setIntReg(int reg_idx, RegVal val) 2772315SN/A { 2782680SN/A actualTC->setIntReg(reg_idx, val); 2792680SN/A checkerTC->setIntReg(reg_idx, val); 2802315SN/A } 2812315SN/A 28213557Sgabeblack@google.com void 28313611Sgabeblack@google.com setFloatReg(int reg_idx, RegVal val) 2842669SN/A { 28513611Sgabeblack@google.com actualTC->setFloatReg(reg_idx, val); 28613611Sgabeblack@google.com checkerTC->setFloatReg(reg_idx, val); 2872315SN/A } 2882315SN/A 28913557Sgabeblack@google.com void 29013557Sgabeblack@google.com setVecReg(const RegId& reg, const VecRegContainer& val) 29112109SRekai.GonzalezAlberquilla@arm.com { 29212109SRekai.GonzalezAlberquilla@arm.com actualTC->setVecReg(reg, val); 29312109SRekai.GonzalezAlberquilla@arm.com checkerTC->setVecReg(reg, val); 29412109SRekai.GonzalezAlberquilla@arm.com } 29512109SRekai.GonzalezAlberquilla@arm.com 29613557Sgabeblack@google.com void 29713557Sgabeblack@google.com setVecElem(const RegId& reg, const VecElem& val) 29812109SRekai.GonzalezAlberquilla@arm.com { 29912109SRekai.GonzalezAlberquilla@arm.com actualTC->setVecElem(reg, val); 30012109SRekai.GonzalezAlberquilla@arm.com checkerTC->setVecElem(reg, val); 30112109SRekai.GonzalezAlberquilla@arm.com } 30212109SRekai.GonzalezAlberquilla@arm.com 30313557Sgabeblack@google.com void 30413610Sgiacomo.gabrielli@arm.com setVecPredReg(const RegId& reg, const VecPredRegContainer& val) 30513610Sgiacomo.gabrielli@arm.com { 30613610Sgiacomo.gabrielli@arm.com actualTC->setVecPredReg(reg, val); 30713610Sgiacomo.gabrielli@arm.com checkerTC->setVecPredReg(reg, val); 30813610Sgiacomo.gabrielli@arm.com } 30913610Sgiacomo.gabrielli@arm.com 31013610Sgiacomo.gabrielli@arm.com void 31113557Sgabeblack@google.com setCCReg(int reg_idx, CCReg val) 3129920Syasuko.eckert@amd.com { 3139920Syasuko.eckert@amd.com actualTC->setCCReg(reg_idx, val); 3149920Syasuko.eckert@amd.com checkerTC->setCCReg(reg_idx, val); 3159920Syasuko.eckert@amd.com } 3169920Syasuko.eckert@amd.com 3178733Sgeoffrey.blake@arm.com /** Reads this thread's PC state. */ 3188733Sgeoffrey.blake@arm.com TheISA::PCState pcState() 3198733Sgeoffrey.blake@arm.com { return actualTC->pcState(); } 3202315SN/A 3218733Sgeoffrey.blake@arm.com /** Sets this thread's PC state. */ 32213557Sgabeblack@google.com void 32313557Sgabeblack@google.com pcState(const TheISA::PCState &val) 3242315SN/A { 3258733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Changing PC to %s, old PC %s\n", 3268733Sgeoffrey.blake@arm.com val, checkerTC->pcState()); 3278733Sgeoffrey.blake@arm.com checkerTC->pcState(val); 3282315SN/A checkerCPU->recordPCChange(val); 3298733Sgeoffrey.blake@arm.com return actualTC->pcState(val); 3302315SN/A } 3312315SN/A 33213557Sgabeblack@google.com void 33313557Sgabeblack@google.com setNPC(Addr val) 33411886Sbrandon.potter@amd.com { 33511886Sbrandon.potter@amd.com checkerTC->setNPC(val); 33611886Sbrandon.potter@amd.com actualTC->setNPC(val); 33711886Sbrandon.potter@amd.com } 33811886Sbrandon.potter@amd.com 33913557Sgabeblack@google.com void 34013557Sgabeblack@google.com pcStateNoRecord(const TheISA::PCState &val) 3412315SN/A { 3428733Sgeoffrey.blake@arm.com return actualTC->pcState(val); 3432315SN/A } 3442315SN/A 3458733Sgeoffrey.blake@arm.com /** Reads this thread's PC. */ 3468733Sgeoffrey.blake@arm.com Addr instAddr() 3478733Sgeoffrey.blake@arm.com { return actualTC->instAddr(); } 3482669SN/A 3498733Sgeoffrey.blake@arm.com /** Reads this thread's next PC. */ 3508733Sgeoffrey.blake@arm.com Addr nextInstAddr() 3518733Sgeoffrey.blake@arm.com { return actualTC->nextInstAddr(); } 3528733Sgeoffrey.blake@arm.com 3538733Sgeoffrey.blake@arm.com /** Reads this thread's next PC. */ 3548733Sgeoffrey.blake@arm.com MicroPC microPC() 3558733Sgeoffrey.blake@arm.com { return actualTC->microPC(); } 3562669SN/A 35713557Sgabeblack@google.com RegVal readMiscRegNoEffect(int misc_reg) const 3584172Ssaidi@eecs.umich.edu { return actualTC->readMiscRegNoEffect(misc_reg); } 3594172Ssaidi@eecs.umich.edu 36013557Sgabeblack@google.com RegVal readMiscReg(int misc_reg) 3612680SN/A { return actualTC->readMiscReg(misc_reg); } 3622315SN/A 36313557Sgabeblack@google.com void 36413582Sgabeblack@google.com setMiscRegNoEffect(int misc_reg, RegVal val) 3654172Ssaidi@eecs.umich.edu { 3668733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker" 3678733Sgeoffrey.blake@arm.com " and O3..\n", misc_reg); 3684172Ssaidi@eecs.umich.edu checkerTC->setMiscRegNoEffect(misc_reg, val); 3694172Ssaidi@eecs.umich.edu actualTC->setMiscRegNoEffect(misc_reg, val); 3704172Ssaidi@eecs.umich.edu } 3712315SN/A 37213557Sgabeblack@google.com void 37313582Sgabeblack@google.com setMiscReg(int misc_reg, RegVal val) 3742315SN/A { 3758733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker" 3768733Sgeoffrey.blake@arm.com " and O3..\n", misc_reg); 3772680SN/A checkerTC->setMiscReg(misc_reg, val); 3783468Sgblack@eecs.umich.edu actualTC->setMiscReg(misc_reg, val); 3792315SN/A } 3802315SN/A 38113557Sgabeblack@google.com RegId 38213557Sgabeblack@google.com flattenRegId(const RegId& regId) const 38313557Sgabeblack@google.com { 38412106SRekai.GonzalezAlberquilla@arm.com return actualTC->flattenRegId(regId); 38512106SRekai.GonzalezAlberquilla@arm.com } 3868733Sgeoffrey.blake@arm.com 3872315SN/A unsigned readStCondFailures() 3882680SN/A { return actualTC->readStCondFailures(); } 3892315SN/A 39013557Sgabeblack@google.com void 39113557Sgabeblack@google.com setStCondFailures(unsigned sc_failures) 3922315SN/A { 3932680SN/A actualTC->setStCondFailures(sc_failures); 3942315SN/A } 3952315SN/A 3962680SN/A Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 3979426SAndreas.Sandberg@ARM.com 39813557Sgabeblack@google.com RegVal readIntRegFlat(int idx) { return actualTC->readIntRegFlat(idx); } 3999426SAndreas.Sandberg@ARM.com 40013557Sgabeblack@google.com void 40113557Sgabeblack@google.com setIntRegFlat(int idx, RegVal val) 40213557Sgabeblack@google.com { 40313557Sgabeblack@google.com actualTC->setIntRegFlat(idx, val); 40413557Sgabeblack@google.com } 4059426SAndreas.Sandberg@ARM.com 40613557Sgabeblack@google.com RegVal 40713611Sgabeblack@google.com readFloatRegFlat(int idx) 40813557Sgabeblack@google.com { 40913611Sgabeblack@google.com return actualTC->readFloatRegFlat(idx); 41013557Sgabeblack@google.com } 4119426SAndreas.Sandberg@ARM.com 41213557Sgabeblack@google.com void 41313611Sgabeblack@google.com setFloatRegFlat(int idx, RegVal val) 41413557Sgabeblack@google.com { 41513611Sgabeblack@google.com actualTC->setFloatRegFlat(idx, val); 41613557Sgabeblack@google.com } 4179920Syasuko.eckert@amd.com 41813557Sgabeblack@google.com const VecRegContainer & 41913557Sgabeblack@google.com readVecRegFlat(int idx) const 42013557Sgabeblack@google.com { 42113557Sgabeblack@google.com return actualTC->readVecRegFlat(idx); 42213557Sgabeblack@google.com } 42312109SRekai.GonzalezAlberquilla@arm.com 42412109SRekai.GonzalezAlberquilla@arm.com /** 42512109SRekai.GonzalezAlberquilla@arm.com * Read vector register for modification, flat indexing. 42612109SRekai.GonzalezAlberquilla@arm.com */ 42713557Sgabeblack@google.com VecRegContainer & 42813557Sgabeblack@google.com getWritableVecRegFlat(int idx) 42913557Sgabeblack@google.com { 43013557Sgabeblack@google.com return actualTC->getWritableVecRegFlat(idx); 43113557Sgabeblack@google.com } 43212109SRekai.GonzalezAlberquilla@arm.com 43312109SRekai.GonzalezAlberquilla@arm.com void setVecRegFlat(int idx, const VecRegContainer& val) 43412109SRekai.GonzalezAlberquilla@arm.com { actualTC->setVecRegFlat(idx, val); } 43512109SRekai.GonzalezAlberquilla@arm.com 43612109SRekai.GonzalezAlberquilla@arm.com const VecElem& readVecElemFlat(const RegIndex& idx, 43712109SRekai.GonzalezAlberquilla@arm.com const ElemIndex& elem_idx) const 43812109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVecElemFlat(idx, elem_idx); } 43912109SRekai.GonzalezAlberquilla@arm.com 44012109SRekai.GonzalezAlberquilla@arm.com void setVecElemFlat(const RegIndex& idx, 44112109SRekai.GonzalezAlberquilla@arm.com const ElemIndex& elem_idx, const VecElem& val) 44212109SRekai.GonzalezAlberquilla@arm.com { actualTC->setVecElemFlat(idx, elem_idx, val); } 44312109SRekai.GonzalezAlberquilla@arm.com 44413610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& readVecPredRegFlat(int idx) const override 44513610Sgiacomo.gabrielli@arm.com { return actualTC->readVecPredRegFlat(idx); } 44613610Sgiacomo.gabrielli@arm.com 44713610Sgiacomo.gabrielli@arm.com VecPredRegContainer& getWritableVecPredRegFlat(int idx) override 44813610Sgiacomo.gabrielli@arm.com { return actualTC->getWritableVecPredRegFlat(idx); } 44913610Sgiacomo.gabrielli@arm.com 45013610Sgiacomo.gabrielli@arm.com void setVecPredRegFlat(int idx, const VecPredRegContainer& val) override 45113610Sgiacomo.gabrielli@arm.com { actualTC->setVecPredRegFlat(idx, val); } 45213610Sgiacomo.gabrielli@arm.com 4539920Syasuko.eckert@amd.com CCReg readCCRegFlat(int idx) 4549920Syasuko.eckert@amd.com { return actualTC->readCCRegFlat(idx); } 4559920Syasuko.eckert@amd.com 4569920Syasuko.eckert@amd.com void setCCRegFlat(int idx, CCReg val) 4579920Syasuko.eckert@amd.com { actualTC->setCCRegFlat(idx, val); } 4582315SN/A}; 4592315SN/A 4602315SN/A#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ 461