thread_context.hh revision 10033
12330SN/A/* 29426SAndreas.Sandberg@ARM.com * Copyright (c) 2011-2012 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152330SN/A * Copyright (c) 2006 The Regents of The University of Michigan 162330SN/A * All rights reserved. 172330SN/A * 182330SN/A * Redistribution and use in source and binary forms, with or without 192330SN/A * modification, are permitted provided that the following conditions are 202330SN/A * met: redistributions of source code must retain the above copyright 212330SN/A * notice, this list of conditions and the following disclaimer; 222330SN/A * redistributions in binary form must reproduce the above copyright 232330SN/A * notice, this list of conditions and the following disclaimer in the 242330SN/A * documentation and/or other materials provided with the distribution; 252330SN/A * neither the name of the copyright holders nor the names of its 262330SN/A * contributors may be used to endorse or promote products derived from 272330SN/A * this software without specific prior written permission. 282330SN/A * 292330SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302330SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312330SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322330SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332330SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342330SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352330SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362330SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372330SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382330SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392330SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Kevin Lim 422330SN/A */ 432330SN/A 442683Sktlim@umich.edu#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__ 452683Sktlim@umich.edu#define __CPU_CHECKER_THREAD_CONTEXT_HH__ 462315SN/A 472972Sgblack@eecs.umich.edu#include "arch/types.hh" 486658Snate@binkert.org#include "config/the_isa.hh" 492315SN/A#include "cpu/checker/cpu.hh" 502683Sktlim@umich.edu#include "cpu/simple_thread.hh" 512680SN/A#include "cpu/thread_context.hh" 528733Sgeoffrey.blake@arm.com#include "debug/Checker.hh" 532315SN/A 542315SN/Aclass EndQuiesceEvent; 553548Sgblack@eecs.umich.edunamespace TheISA { 563548Sgblack@eecs.umich.edu namespace Kernel { 573548Sgblack@eecs.umich.edu class Statistics; 583548Sgblack@eecs.umich.edu }; 599020Sgblack@eecs.umich.edu class Decoder; 602330SN/A}; 612315SN/A 622350SN/A/** 632680SN/A * Derived ThreadContext class for use with the Checker. The template 642680SN/A * parameter is the ThreadContext class used by the specific CPU being 652683Sktlim@umich.edu * verified. This CheckerThreadContext is then used by the main CPU 662683Sktlim@umich.edu * in place of its usual ThreadContext class. It handles updating the 672683Sktlim@umich.edu * checker's state any time state is updated externally through the 682683Sktlim@umich.edu * ThreadContext. 692350SN/A */ 702680SN/Atemplate <class TC> 712680SN/Aclass CheckerThreadContext : public ThreadContext 722315SN/A{ 732315SN/A public: 742680SN/A CheckerThreadContext(TC *actual_tc, 752683Sktlim@umich.edu CheckerCPU *checker_cpu) 762683Sktlim@umich.edu : actualTC(actual_tc), checkerTC(checker_cpu->thread), 772330SN/A checkerCPU(checker_cpu) 782315SN/A { } 792315SN/A 802315SN/A private: 812683Sktlim@umich.edu /** The main CPU's ThreadContext, or class that implements the 822683Sktlim@umich.edu * ThreadContext interface. */ 832680SN/A TC *actualTC; 842683Sktlim@umich.edu /** The checker's own SimpleThread. Will be updated any time 852683Sktlim@umich.edu * anything uses this ThreadContext to externally update a 862683Sktlim@umich.edu * thread's state. */ 872683Sktlim@umich.edu SimpleThread *checkerTC; 882683Sktlim@umich.edu /** Pointer to the checker CPU. */ 892315SN/A CheckerCPU *checkerCPU; 902315SN/A 912315SN/A public: 922315SN/A 932680SN/A BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 942315SN/A 958733Sgeoffrey.blake@arm.com int cpuId() { return actualTC->cpuId(); } 968733Sgeoffrey.blake@arm.com 978733Sgeoffrey.blake@arm.com int contextId() { return actualTC->contextId(); } 988733Sgeoffrey.blake@arm.com 998733Sgeoffrey.blake@arm.com void setContextId(int id) 1002315SN/A { 1018733Sgeoffrey.blake@arm.com actualTC->setContextId(id); 1028733Sgeoffrey.blake@arm.com checkerTC->setContextId(id); 1032315SN/A } 1042315SN/A 1058733Sgeoffrey.blake@arm.com /** Returns this thread's ID number. */ 1068733Sgeoffrey.blake@arm.com int threadId() { return actualTC->threadId(); } 1078733Sgeoffrey.blake@arm.com void setThreadId(int id) 1088733Sgeoffrey.blake@arm.com { 1098733Sgeoffrey.blake@arm.com checkerTC->setThreadId(id); 1108733Sgeoffrey.blake@arm.com actualTC->setThreadId(id); 1118733Sgeoffrey.blake@arm.com } 1122315SN/A 1136022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 1144997Sgblack@eecs.umich.edu 1156022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 1164997Sgblack@eecs.umich.edu 1178887Sgeoffrey.blake@arm.com CheckerCPU *getCheckerCpuPtr() 1188887Sgeoffrey.blake@arm.com { 1198887Sgeoffrey.blake@arm.com return checkerCPU; 1208887Sgeoffrey.blake@arm.com } 1218733Sgeoffrey.blake@arm.com 1229020Sgblack@eecs.umich.edu TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 1238733Sgeoffrey.blake@arm.com 1242680SN/A System *getSystemPtr() { return actualTC->getSystemPtr(); } 1252315SN/A 1263548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() 1273548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 1282690Sktlim@umich.edu 1297679Sgblack@eecs.umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 1307679Sgblack@eecs.umich.edu 1318852Sandreas.hansson@arm.com PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); } 1322690Sktlim@umich.edu 1338852Sandreas.hansson@arm.com FSTranslatingPortProxy &getVirtProxy() 1348706Sandreas.hansson@arm.com { return actualTC->getVirtProxy(); } 1358733Sgeoffrey.blake@arm.com 1368733Sgeoffrey.blake@arm.com void initMemProxies(ThreadContext *tc) 1378733Sgeoffrey.blake@arm.com { actualTC->initMemProxies(tc); } 1388733Sgeoffrey.blake@arm.com 1398733Sgeoffrey.blake@arm.com void connectMemPorts(ThreadContext *tc) 1408733Sgeoffrey.blake@arm.com { 1418733Sgeoffrey.blake@arm.com actualTC->connectMemPorts(tc); 1428733Sgeoffrey.blake@arm.com } 1438809Sgblack@eecs.umich.edu 1448852Sandreas.hansson@arm.com SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); } 1452690Sktlim@umich.edu 1468733Sgeoffrey.blake@arm.com /** Executes a syscall in SE mode. */ 1478733Sgeoffrey.blake@arm.com void syscall(int64_t callnum) 1488733Sgeoffrey.blake@arm.com { return actualTC->syscall(callnum); } 1492315SN/A 1502680SN/A Status status() const { return actualTC->status(); } 1512315SN/A 1522315SN/A void setStatus(Status new_status) 1532330SN/A { 1542680SN/A actualTC->setStatus(new_status); 1552680SN/A checkerTC->setStatus(new_status); 1562330SN/A } 1572315SN/A 1582315SN/A /// Set the status to Active. Optional delay indicates number of 1592315SN/A /// cycles to wait before beginning execution. 1609180Sandreas.hansson@arm.com void activate(Cycles delay = Cycles(1)) 1619180Sandreas.hansson@arm.com { actualTC->activate(delay); } 1622315SN/A 1632315SN/A /// Set the status to Suspended. 1649180Sandreas.hansson@arm.com void suspend(Cycles delay) { actualTC->suspend(delay); } 1652315SN/A 1662315SN/A /// Set the status to Halted. 1679180Sandreas.hansson@arm.com void halt(Cycles delay) { actualTC->halt(delay); } 1682315SN/A 1692680SN/A void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 1702315SN/A 1712680SN/A void takeOverFrom(ThreadContext *oldContext) 1722315SN/A { 1732680SN/A actualTC->takeOverFrom(oldContext); 1743225Sktlim@umich.edu checkerTC->copyState(oldContext); 1752315SN/A } 1762315SN/A 1778733Sgeoffrey.blake@arm.com void regStats(const std::string &name) 1788733Sgeoffrey.blake@arm.com { 1798733Sgeoffrey.blake@arm.com actualTC->regStats(name); 1808733Sgeoffrey.blake@arm.com checkerTC->regStats(name); 1818733Sgeoffrey.blake@arm.com } 1822315SN/A 1832680SN/A void serialize(std::ostream &os) { actualTC->serialize(os); } 1842315SN/A void unserialize(Checkpoint *cp, const std::string §ion) 1852680SN/A { actualTC->unserialize(cp, section); } 1862315SN/A 1872680SN/A EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 1882315SN/A 1892680SN/A Tick readLastActivate() { return actualTC->readLastActivate(); } 1902680SN/A Tick readLastSuspend() { return actualTC->readLastSuspend(); } 1912315SN/A 1922680SN/A void profileClear() { return actualTC->profileClear(); } 1932680SN/A void profileSample() { return actualTC->profileSample(); } 1942315SN/A 1952315SN/A // @todo: Do I need this? 1962680SN/A void copyArchRegs(ThreadContext *tc) 1972315SN/A { 1982680SN/A actualTC->copyArchRegs(tc); 1992680SN/A checkerTC->copyArchRegs(tc); 2002315SN/A } 2012315SN/A 2022315SN/A void clearArchRegs() 2032315SN/A { 2042680SN/A actualTC->clearArchRegs(); 2052680SN/A checkerTC->clearArchRegs(); 2062315SN/A } 2072315SN/A 2082315SN/A // 2092315SN/A // New accessors for new decoder. 2102315SN/A // 2112315SN/A uint64_t readIntReg(int reg_idx) 2122680SN/A { return actualTC->readIntReg(reg_idx); } 2132315SN/A 2142669SN/A FloatReg readFloatReg(int reg_idx) 2152680SN/A { return actualTC->readFloatReg(reg_idx); } 2162315SN/A 2172669SN/A FloatRegBits readFloatRegBits(int reg_idx) 2182680SN/A { return actualTC->readFloatRegBits(reg_idx); } 2192315SN/A 2209920Syasuko.eckert@amd.com CCReg readCCReg(int reg_idx) 2219920Syasuko.eckert@amd.com { return actualTC->readCCReg(reg_idx); } 2229920Syasuko.eckert@amd.com 2232315SN/A void setIntReg(int reg_idx, uint64_t val) 2242315SN/A { 2252680SN/A actualTC->setIntReg(reg_idx, val); 2262680SN/A checkerTC->setIntReg(reg_idx, val); 2272315SN/A } 2282315SN/A 2292669SN/A void setFloatReg(int reg_idx, FloatReg val) 2302315SN/A { 2312680SN/A actualTC->setFloatReg(reg_idx, val); 2322680SN/A checkerTC->setFloatReg(reg_idx, val); 2332315SN/A } 2342315SN/A 2352669SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 2362669SN/A { 2372680SN/A actualTC->setFloatRegBits(reg_idx, val); 2382680SN/A checkerTC->setFloatRegBits(reg_idx, val); 2392315SN/A } 2402315SN/A 2419920Syasuko.eckert@amd.com void setCCReg(int reg_idx, CCReg val) 2429920Syasuko.eckert@amd.com { 2439920Syasuko.eckert@amd.com actualTC->setCCReg(reg_idx, val); 2449920Syasuko.eckert@amd.com checkerTC->setCCReg(reg_idx, val); 2459920Syasuko.eckert@amd.com } 2469920Syasuko.eckert@amd.com 2478733Sgeoffrey.blake@arm.com /** Reads this thread's PC state. */ 2488733Sgeoffrey.blake@arm.com TheISA::PCState pcState() 2498733Sgeoffrey.blake@arm.com { return actualTC->pcState(); } 2502315SN/A 2518733Sgeoffrey.blake@arm.com /** Sets this thread's PC state. */ 2528733Sgeoffrey.blake@arm.com void pcState(const TheISA::PCState &val) 2532315SN/A { 2548733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Changing PC to %s, old PC %s\n", 2558733Sgeoffrey.blake@arm.com val, checkerTC->pcState()); 2568733Sgeoffrey.blake@arm.com checkerTC->pcState(val); 2572315SN/A checkerCPU->recordPCChange(val); 2588733Sgeoffrey.blake@arm.com return actualTC->pcState(val); 2592315SN/A } 2602315SN/A 2618733Sgeoffrey.blake@arm.com void pcStateNoRecord(const TheISA::PCState &val) 2622315SN/A { 2638733Sgeoffrey.blake@arm.com return actualTC->pcState(val); 2642315SN/A } 2652315SN/A 2668733Sgeoffrey.blake@arm.com /** Reads this thread's PC. */ 2678733Sgeoffrey.blake@arm.com Addr instAddr() 2688733Sgeoffrey.blake@arm.com { return actualTC->instAddr(); } 2692669SN/A 2708733Sgeoffrey.blake@arm.com /** Reads this thread's next PC. */ 2718733Sgeoffrey.blake@arm.com Addr nextInstAddr() 2728733Sgeoffrey.blake@arm.com { return actualTC->nextInstAddr(); } 2738733Sgeoffrey.blake@arm.com 2748733Sgeoffrey.blake@arm.com /** Reads this thread's next PC. */ 2758733Sgeoffrey.blake@arm.com MicroPC microPC() 2768733Sgeoffrey.blake@arm.com { return actualTC->microPC(); } 2772669SN/A 2784172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 2794172Ssaidi@eecs.umich.edu { return actualTC->readMiscRegNoEffect(misc_reg); } 2804172Ssaidi@eecs.umich.edu 2812315SN/A MiscReg readMiscReg(int misc_reg) 2822680SN/A { return actualTC->readMiscReg(misc_reg); } 2832315SN/A 2844172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 2854172Ssaidi@eecs.umich.edu { 2868733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker" 2878733Sgeoffrey.blake@arm.com " and O3..\n", misc_reg); 2884172Ssaidi@eecs.umich.edu checkerTC->setMiscRegNoEffect(misc_reg, val); 2894172Ssaidi@eecs.umich.edu actualTC->setMiscRegNoEffect(misc_reg, val); 2904172Ssaidi@eecs.umich.edu } 2912315SN/A 2923468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 2932315SN/A { 2948733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker" 2958733Sgeoffrey.blake@arm.com " and O3..\n", misc_reg); 2962680SN/A checkerTC->setMiscReg(misc_reg, val); 2973468Sgblack@eecs.umich.edu actualTC->setMiscReg(misc_reg, val); 2982315SN/A } 2992315SN/A 3008733Sgeoffrey.blake@arm.com int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); } 3018733Sgeoffrey.blake@arm.com int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); } 3029920Syasuko.eckert@amd.com int flattenCCIndex(int reg) { return actualTC->flattenCCIndex(reg); } 30310033SAli.Saidi@ARM.com int flattenMiscIndex(int reg) { return actualTC->flattenMiscIndex(reg); } 3048733Sgeoffrey.blake@arm.com 3052315SN/A unsigned readStCondFailures() 3062680SN/A { return actualTC->readStCondFailures(); } 3072315SN/A 3082315SN/A void setStCondFailures(unsigned sc_failures) 3092315SN/A { 3102680SN/A actualTC->setStCondFailures(sc_failures); 3112315SN/A } 3122315SN/A 3132315SN/A // @todo: Fix this! 3142680SN/A bool misspeculating() { return actualTC->misspeculating(); } 3152315SN/A 3162680SN/A Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 3179426SAndreas.Sandberg@ARM.com 3189426SAndreas.Sandberg@ARM.com uint64_t readIntRegFlat(int idx) 3199426SAndreas.Sandberg@ARM.com { return actualTC->readIntRegFlat(idx); } 3209426SAndreas.Sandberg@ARM.com 3219426SAndreas.Sandberg@ARM.com void setIntRegFlat(int idx, uint64_t val) 3229426SAndreas.Sandberg@ARM.com { actualTC->setIntRegFlat(idx, val); } 3239426SAndreas.Sandberg@ARM.com 3249426SAndreas.Sandberg@ARM.com FloatReg readFloatRegFlat(int idx) 3259426SAndreas.Sandberg@ARM.com { return actualTC->readFloatRegFlat(idx); } 3269426SAndreas.Sandberg@ARM.com 3279426SAndreas.Sandberg@ARM.com void setFloatRegFlat(int idx, FloatReg val) 3289426SAndreas.Sandberg@ARM.com { actualTC->setFloatRegFlat(idx, val); } 3299426SAndreas.Sandberg@ARM.com 3309426SAndreas.Sandberg@ARM.com FloatRegBits readFloatRegBitsFlat(int idx) 3319426SAndreas.Sandberg@ARM.com { return actualTC->readFloatRegBitsFlat(idx); } 3329426SAndreas.Sandberg@ARM.com 3339426SAndreas.Sandberg@ARM.com void setFloatRegBitsFlat(int idx, FloatRegBits val) 3349426SAndreas.Sandberg@ARM.com { actualTC->setFloatRegBitsFlat(idx, val); } 3359920Syasuko.eckert@amd.com 3369920Syasuko.eckert@amd.com CCReg readCCRegFlat(int idx) 3379920Syasuko.eckert@amd.com { return actualTC->readCCRegFlat(idx); } 3389920Syasuko.eckert@amd.com 3399920Syasuko.eckert@amd.com void setCCRegFlat(int idx, CCReg val) 3409920Syasuko.eckert@amd.com { actualTC->setCCRegFlat(idx, val); } 3412315SN/A}; 3422315SN/A 3432315SN/A#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ 344