cpu.hh revision 8922:17f037ad8918
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43#ifndef __CPU_CHECKER_CPU_HH__ 44#define __CPU_CHECKER_CPU_HH__ 45 46#include <list> 47#include <map> 48#include <queue> 49 50#include "arch/predecoder.hh" 51#include "arch/types.hh" 52#include "base/statistics.hh" 53#include "cpu/base.hh" 54#include "cpu/base_dyn_inst.hh" 55#include "cpu/pc_event.hh" 56#include "cpu/simple_thread.hh" 57#include "cpu/static_inst.hh" 58#include "debug/Checker.hh" 59#include "params/CheckerCPU.hh" 60#include "sim/eventq.hh" 61 62// forward declarations 63namespace TheISA 64{ 65 class TLB; 66} 67 68template <class> 69class BaseDynInst; 70class ThreadContext; 71class Request; 72 73/** 74 * CheckerCPU class. Dynamically verifies instructions as they are 75 * completed by making sure that the instruction and its results match 76 * the independent execution of the benchmark inside the checker. The 77 * checker verifies instructions in order, regardless of the order in 78 * which instructions complete. There are certain results that can 79 * not be verified, specifically the result of a store conditional or 80 * the values of uncached accesses. In these cases, and with 81 * instructions marked as "IsUnverifiable", the checker assumes that 82 * the value from the main CPU's execution is correct and simply 83 * copies that value. It provides a CheckerThreadContext (see 84 * checker/thread_context.hh) that provides hooks for updating the 85 * Checker's state through any ThreadContext accesses. This allows the 86 * checker to be able to correctly verify instructions, even with 87 * external accesses to the ThreadContext that change state. 88 */ 89class CheckerCPU : public BaseCPU 90{ 91 protected: 92 typedef TheISA::MachInst MachInst; 93 typedef TheISA::FloatReg FloatReg; 94 typedef TheISA::FloatRegBits FloatRegBits; 95 typedef TheISA::MiscReg MiscReg; 96 97 /** id attached to all issued requests */ 98 MasterID masterId; 99 public: 100 virtual void init(); 101 102 public: 103 typedef CheckerCPUParams Params; 104 const Params *params() const 105 { return reinterpret_cast<const Params *>(_params); } 106 CheckerCPU(Params *p); 107 virtual ~CheckerCPU(); 108 109 std::vector<Process*> workload; 110 111 void setSystem(System *system); 112 113 System *systemPtr; 114 115 void setIcachePort(CpuPort *icache_port); 116 117 CpuPort *icachePort; 118 119 void setDcachePort(CpuPort *dcache_port); 120 121 CpuPort *dcachePort; 122 123 CpuPort &getDataPort() 124 { 125 panic("Not supported on checker!"); 126 return *dcachePort; 127 } 128 129 CpuPort &getInstPort() 130 { 131 panic("Not supported on checker!"); 132 return *icachePort; 133 } 134 135 public: 136 // Primary thread being run. 137 SimpleThread *thread; 138 139 ThreadContext *tc; 140 141 TheISA::TLB *itb; 142 TheISA::TLB *dtb; 143 144 Addr dbg_vtophys(Addr addr); 145 146 union Result { 147 uint64_t integer; 148 double dbl; 149 void set(uint64_t i) { integer = i; } 150 void set(double d) { dbl = d; } 151 void get(uint64_t& i) { i = integer; } 152 void get(double& d) { d = dbl; } 153 }; 154 155 // ISAs like ARM can have multiple destination registers to check, 156 // keep them all in a std::queue 157 std::queue<Result> result; 158 159 // current instruction 160 TheISA::MachInst machInst; 161 162 // Pointer to the one memory request. 163 RequestPtr memReq; 164 165 StaticInstPtr curStaticInst; 166 StaticInstPtr curMacroStaticInst; 167 168 // number of simulated instructions 169 Counter numInst; 170 Counter startNumInst; 171 172 std::queue<int> miscRegIdxs; 173 174 TheISA::TLB* getITBPtr() { return itb; } 175 TheISA::TLB* getDTBPtr() { return dtb; } 176 177 virtual Counter totalInsts() const 178 { 179 return 0; 180 } 181 182 virtual Counter totalOps() const 183 { 184 return 0; 185 } 186 187 // number of simulated loads 188 Counter numLoad; 189 Counter startNumLoad; 190 191 virtual void serialize(std::ostream &os); 192 virtual void unserialize(Checkpoint *cp, const std::string §ion); 193 194 // These functions are only used in CPU models that split 195 // effective address computation from the actual memory access. 196 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } 197 Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); } 198 199 // The register accessor methods provide the index of the 200 // instruction's operand (e.g., 0 or 1), not the architectural 201 // register index, to simplify the implementation of register 202 // renaming. We find the architectural register index by indexing 203 // into the instruction's own operand index table. Note that a 204 // raw pointer to the StaticInst is provided instead of a 205 // ref-counted StaticInstPtr to redice overhead. This is fine as 206 // long as these methods don't copy the pointer into any long-term 207 // storage (which is pretty hard to imagine they would have reason 208 // to do). 209 210 uint64_t readIntRegOperand(const StaticInst *si, int idx) 211 { 212 return thread->readIntReg(si->srcRegIdx(idx)); 213 } 214 215 FloatReg readFloatRegOperand(const StaticInst *si, int idx) 216 { 217 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 218 return thread->readFloatReg(reg_idx); 219 } 220 221 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 222 { 223 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 224 return thread->readFloatRegBits(reg_idx); 225 } 226 227 template <class T> 228 void setResult(T t) 229 { 230 Result instRes; 231 instRes.set(t); 232 result.push(instRes); 233 } 234 235 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 236 { 237 thread->setIntReg(si->destRegIdx(idx), val); 238 setResult<uint64_t>(val); 239 } 240 241 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 242 { 243 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 244 thread->setFloatReg(reg_idx, val); 245 setResult<double>(val); 246 } 247 248 void setFloatRegOperandBits(const StaticInst *si, int idx, 249 FloatRegBits val) 250 { 251 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 252 thread->setFloatRegBits(reg_idx, val); 253 setResult<uint64_t>(val); 254 } 255 256 bool readPredicate() { return thread->readPredicate(); } 257 void setPredicate(bool val) 258 { 259 thread->setPredicate(val); 260 } 261 262 TheISA::PCState pcState() { return thread->pcState(); } 263 void pcState(const TheISA::PCState &val) 264 { 265 DPRINTF(Checker, "Changing PC to %s, old PC %s.\n", 266 val, thread->pcState()); 267 thread->pcState(val); 268 } 269 Addr instAddr() { return thread->instAddr(); } 270 Addr nextInstAddr() { return thread->nextInstAddr(); } 271 MicroPC microPC() { return thread->microPC(); } 272 ////////////////////////////////////////// 273 274 MiscReg readMiscRegNoEffect(int misc_reg) 275 { 276 return thread->readMiscRegNoEffect(misc_reg); 277 } 278 279 MiscReg readMiscReg(int misc_reg) 280 { 281 return thread->readMiscReg(misc_reg); 282 } 283 284 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 285 { 286 miscRegIdxs.push(misc_reg); 287 return thread->setMiscRegNoEffect(misc_reg, val); 288 } 289 290 void setMiscReg(int misc_reg, const MiscReg &val) 291 { 292 miscRegIdxs.push(misc_reg); 293 return thread->setMiscReg(misc_reg, val); 294 } 295 296 MiscReg readMiscRegOperand(const StaticInst *si, int idx) 297 { 298 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 299 return thread->readMiscReg(reg_idx); 300 } 301 302 void setMiscRegOperand( 303 const StaticInst *si, int idx, const MiscReg &val) 304 { 305 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 306 return thread->setMiscReg(reg_idx, val); 307 } 308 309#if THE_ISA == MIPS_ISA 310 uint64_t readRegOtherThread(int misc_reg) 311 { 312 panic("MIPS MT not defined for CheckerCPU.\n"); 313 return 0; 314 } 315 316 void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val) 317 { 318 panic("MIPS MT not defined for CheckerCPU.\n"); 319 } 320#endif 321 322 ///////////////////////////////////////// 323 324 void recordPCChange(const TheISA::PCState &val) 325 { 326 changedPC = true; 327 newPCState = val; 328 } 329 330 void demapPage(Addr vaddr, uint64_t asn) 331 { 332 this->itb->demapPage(vaddr, asn); 333 this->dtb->demapPage(vaddr, asn); 334 } 335 336 void demapInstPage(Addr vaddr, uint64_t asn) 337 { 338 this->itb->demapPage(vaddr, asn); 339 } 340 341 void demapDataPage(Addr vaddr, uint64_t asn) 342 { 343 this->dtb->demapPage(vaddr, asn); 344 } 345 346 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 347 Fault writeMem(uint8_t *data, unsigned size, 348 Addr addr, unsigned flags, uint64_t *res); 349 350 void setStCondFailures(unsigned sc_failures) 351 {} 352 ///////////////////////////////////////////////////// 353 354 Fault hwrei() { return thread->hwrei(); } 355 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 356 void wakeup() { } 357 // Assume that the normal CPU's call to syscall was successful. 358 // The checker's state would have already been updated by the syscall. 359 void syscall(uint64_t callnum) { } 360 361 void handleError() 362 { 363 if (exitOnError) 364 dumpAndExit(); 365 } 366 367 bool checkFlags(Request *unverified_req, Addr vAddr, 368 Addr pAddr, int flags); 369 370 void dumpAndExit(); 371 372 ThreadContext *tcBase() { return tc; } 373 SimpleThread *threadBase() { return thread; } 374 375 Result unverifiedResult; 376 Request *unverifiedReq; 377 uint8_t *unverifiedMemData; 378 379 bool changedPC; 380 bool willChangePC; 381 TheISA::PCState newPCState; 382 bool changedNextPC; 383 bool exitOnError; 384 bool updateOnError; 385 bool warnOnlyOnLoadError; 386 387 InstSeqNum youngestSN; 388}; 389 390/** 391 * Templated Checker class. This Checker class is templated on the 392 * DynInstPtr of the instruction type that will be verified. Proper 393 * template instantiations of the Checker must be placed at the bottom 394 * of checker/cpu.cc. 395 */ 396template <class Impl> 397class Checker : public CheckerCPU 398{ 399 private: 400 typedef typename Impl::DynInstPtr DynInstPtr; 401 402 public: 403 Checker(Params *p) 404 : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL), 405 predecoder(NULL) 406 { } 407 408 void switchOut(); 409 void takeOverFrom(BaseCPU *oldCPU); 410 411 void advancePC(Fault fault); 412 413 void verify(DynInstPtr &inst); 414 415 void validateInst(DynInstPtr &inst); 416 void validateExecution(DynInstPtr &inst); 417 void validateState(); 418 419 void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx); 420 void handlePendingInt(); 421 422 private: 423 void handleError(DynInstPtr &inst) 424 { 425 if (exitOnError) { 426 dumpAndExit(inst); 427 } else if (updateOnError) { 428 updateThisCycle = true; 429 } 430 } 431 432 void dumpAndExit(DynInstPtr &inst); 433 434 bool updateThisCycle; 435 436 DynInstPtr unverifiedInst; 437 TheISA::Predecoder predecoder; 438 439 std::list<DynInstPtr> instList; 440 typedef typename std::list<DynInstPtr>::iterator InstListIt; 441 void dumpInsts(); 442}; 443 444#endif // __CPU_CHECKER_CPU_HH__ 445