cpu.hh revision 2683:d6b72bb2ed97
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __CPU_CHECKER_CPU_HH__ 30#define __CPU_CHECKER_CPU_HH__ 31 32#include <list> 33#include <queue> 34#include <map> 35 36#include "arch/types.hh" 37#include "base/statistics.hh" 38#include "config/full_system.hh" 39#include "cpu/base.hh" 40#include "cpu/base_dyn_inst.hh" 41#include "cpu/simple_thread.hh" 42#include "cpu/pc_event.hh" 43#include "cpu/static_inst.hh" 44#include "sim/eventq.hh" 45 46// forward declarations 47#if FULL_SYSTEM 48class Processor; 49class AlphaITB; 50class AlphaDTB; 51class PhysicalMemory; 52 53class RemoteGDB; 54class GDBListener; 55 56#else 57 58class Process; 59 60#endif // FULL_SYSTEM 61template <class> 62class BaseDynInst; 63class ThreadContext; 64class MemInterface; 65class Checkpoint; 66class Request; 67class Sampler; 68 69/** 70 * CheckerCPU class. Dynamically verifies instructions as they are 71 * completed by making sure that the instruction and its results match 72 * the independent execution of the benchmark inside the checker. The 73 * checker verifies instructions in order, regardless of the order in 74 * which instructions complete. There are certain results that can 75 * not be verified, specifically the result of a store conditional or 76 * the values of uncached accesses. In these cases, and with 77 * instructions marked as "IsUnverifiable", the checker assumes that 78 * the value from the main CPU's execution is correct and simply 79 * copies that value. It provides a CheckerThreadContext (see 80 * checker/thread_context.hh) that provides hooks for updating the 81 * Checker's state through any ThreadContext accesses. This allows the 82 * checker to be able to correctly verify instructions, even with 83 * external accesses to the ThreadContext that change state. 84 */ 85class CheckerCPU : public BaseCPU 86{ 87 protected: 88 typedef TheISA::MachInst MachInst; 89 typedef TheISA::FloatReg FloatReg; 90 typedef TheISA::FloatRegBits FloatRegBits; 91 typedef TheISA::MiscReg MiscReg; 92 public: 93 virtual void init(); 94 95 struct Params : public BaseCPU::Params 96 { 97#if FULL_SYSTEM 98 AlphaITB *itb; 99 AlphaDTB *dtb; 100 FunctionalMemory *mem; 101#else 102 Process *process; 103#endif 104 bool exitOnError; 105 }; 106 107 public: 108 CheckerCPU(Params *p); 109 virtual ~CheckerCPU(); 110 111 Process *process; 112 113 void setMemory(MemObject *mem); 114 115 MemObject *memPtr; 116 117#if FULL_SYSTEM 118 void setSystem(System *system); 119 120 System *systemPtr; 121#endif 122 123 void setIcachePort(Port *icache_port); 124 125 Port *icachePort; 126 127 void setDcachePort(Port *dcache_port); 128 129 Port *dcachePort; 130 131 public: 132 // Primary thread being run. 133 SimpleThread *thread; 134 135 ThreadContext *tc; 136 137 AlphaITB *itb; 138 AlphaDTB *dtb; 139 140#if FULL_SYSTEM 141 Addr dbg_vtophys(Addr addr); 142#endif 143 144 union Result { 145 uint64_t integer; 146 float fp; 147 double dbl; 148 }; 149 150 Result result; 151 152 // current instruction 153 MachInst machInst; 154 155 // Pointer to the one memory request. 156 RequestPtr memReq; 157 158 StaticInstPtr curStaticInst; 159 160 // number of simulated instructions 161 Counter numInst; 162 Counter startNumInst; 163 164 std::queue<int> miscRegIdxs; 165 166 virtual Counter totalInstructions() const 167 { 168 return numInst - startNumInst; 169 } 170 171 // number of simulated loads 172 Counter numLoad; 173 Counter startNumLoad; 174 175 virtual void serialize(std::ostream &os); 176 virtual void unserialize(Checkpoint *cp, const std::string §ion); 177 178 template <class T> 179 Fault read(Addr addr, T &data, unsigned flags); 180 181 template <class T> 182 Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 183 184 // These functions are only used in CPU models that split 185 // effective address computation from the actual memory access. 186 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } 187 Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); } 188 189 void prefetch(Addr addr, unsigned flags) 190 { 191 // need to do this... 192 } 193 194 void writeHint(Addr addr, int size, unsigned flags) 195 { 196 // need to do this... 197 } 198 199 Fault copySrcTranslate(Addr src); 200 201 Fault copy(Addr dest); 202 203 // The register accessor methods provide the index of the 204 // instruction's operand (e.g., 0 or 1), not the architectural 205 // register index, to simplify the implementation of register 206 // renaming. We find the architectural register index by indexing 207 // into the instruction's own operand index table. Note that a 208 // raw pointer to the StaticInst is provided instead of a 209 // ref-counted StaticInstPtr to redice overhead. This is fine as 210 // long as these methods don't copy the pointer into any long-term 211 // storage (which is pretty hard to imagine they would have reason 212 // to do). 213 214 uint64_t readIntReg(const StaticInst *si, int idx) 215 { 216 return thread->readIntReg(si->srcRegIdx(idx)); 217 } 218 219 FloatReg readFloatReg(const StaticInst *si, int idx, int width) 220 { 221 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 222 return thread->readFloatReg(reg_idx, width); 223 } 224 225 FloatReg readFloatReg(const StaticInst *si, int idx) 226 { 227 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 228 return thread->readFloatReg(reg_idx); 229 } 230 231 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width) 232 { 233 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 234 return thread->readFloatRegBits(reg_idx, width); 235 } 236 237 FloatRegBits readFloatRegBits(const StaticInst *si, int idx) 238 { 239 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 240 return thread->readFloatRegBits(reg_idx); 241 } 242 243 void setIntReg(const StaticInst *si, int idx, uint64_t val) 244 { 245 thread->setIntReg(si->destRegIdx(idx), val); 246 result.integer = val; 247 } 248 249 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width) 250 { 251 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 252 thread->setFloatReg(reg_idx, val, width); 253 switch(width) { 254 case 32: 255 result.fp = val; 256 break; 257 case 64: 258 result.dbl = val; 259 break; 260 }; 261 } 262 263 void setFloatReg(const StaticInst *si, int idx, FloatReg val) 264 { 265 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 266 thread->setFloatReg(reg_idx, val); 267 result.fp = val; 268 } 269 270 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val, 271 int width) 272 { 273 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 274 thread->setFloatRegBits(reg_idx, val, width); 275 result.integer = val; 276 } 277 278 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val) 279 { 280 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 281 thread->setFloatRegBits(reg_idx, val); 282 result.integer = val; 283 } 284 285 uint64_t readPC() { return thread->readPC(); } 286 287 uint64_t readNextPC() { return thread->readNextPC(); } 288 289 void setNextPC(uint64_t val) { 290 thread->setNextPC(val); 291 } 292 293 MiscReg readMiscReg(int misc_reg) 294 { 295 return thread->readMiscReg(misc_reg); 296 } 297 298 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 299 { 300 return thread->readMiscRegWithEffect(misc_reg, fault); 301 } 302 303 Fault setMiscReg(int misc_reg, const MiscReg &val) 304 { 305 result.integer = val; 306 miscRegIdxs.push(misc_reg); 307 return thread->setMiscReg(misc_reg, val); 308 } 309 310 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 311 { 312 miscRegIdxs.push(misc_reg); 313 return thread->setMiscRegWithEffect(misc_reg, val); 314 } 315 316 void recordPCChange(uint64_t val) { changedPC = true; } 317 void recordNextPCChange(uint64_t val) { changedNextPC = true; } 318 319 bool translateInstReq(Request *req); 320 void translateDataWriteReq(Request *req); 321 void translateDataReadReq(Request *req); 322 323#if FULL_SYSTEM 324 Fault hwrei() { return thread->hwrei(); } 325 int readIntrFlag() { return thread->readIntrFlag(); } 326 void setIntrFlag(int val) { thread->setIntrFlag(val); } 327 bool inPalMode() { return thread->inPalMode(); } 328 void ev5_trap(Fault fault) { fault->invoke(xcProxy); } 329 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 330#else 331 // Assume that the normal CPU's call to syscall was successful. 332 // The checker's state would have already been updated by the syscall. 333 void syscall(uint64_t callnum) { } 334#endif 335 336 void handleError() 337 { 338 if (exitOnError) 339 panic("Checker found error!"); 340 } 341 bool checkFlags(Request *req); 342 343 ThreadContext *tcBase() { return tc; } 344 SimpleThread *threadBase() { return thread; } 345 346 Result unverifiedResult; 347 Request *unverifiedReq; 348 uint8_t *unverifiedMemData; 349 350 bool changedPC; 351 bool willChangePC; 352 uint64_t newPC; 353 bool changedNextPC; 354 bool exitOnError; 355 356 InstSeqNum youngestSN; 357}; 358 359/** 360 * Templated Checker class. This Checker class is templated on the 361 * DynInstPtr of the instruction type that will be verified. Proper 362 * template instantiations of the Checker must be placed at the bottom 363 * of checker/cpu.cc. 364 */ 365template <class DynInstPtr> 366class Checker : public CheckerCPU 367{ 368 public: 369 Checker(Params *p) 370 : CheckerCPU(p) 371 { } 372 373 void switchOut(Sampler *s); 374 void takeOverFrom(BaseCPU *oldCPU); 375 376 void tick(DynInstPtr &inst); 377 378 void validateInst(DynInstPtr &inst); 379 void validateExecution(DynInstPtr &inst); 380 void validateState(); 381 382 std::list<DynInstPtr> instList; 383 typedef typename std::list<DynInstPtr>::iterator InstListIt; 384 void dumpInsts(); 385}; 386 387#endif // __CPU_CHECKER_CPU_HH__ 388