cpu.hh revision 11169
1/*
2 * Copyright (c) 2011 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_CHECKER_CPU_HH__
45#define __CPU_CHECKER_CPU_HH__
46
47#include <list>
48#include <map>
49#include <queue>
50
51#include "arch/types.hh"
52#include "base/statistics.hh"
53#include "cpu/base.hh"
54#include "cpu/base_dyn_inst.hh"
55#include "cpu/exec_context.hh"
56#include "cpu/pc_event.hh"
57#include "cpu/simple_thread.hh"
58#include "cpu/static_inst.hh"
59#include "debug/Checker.hh"
60#include "params/CheckerCPU.hh"
61#include "sim/eventq.hh"
62
63// forward declarations
64namespace TheISA
65{
66    class TLB;
67}
68
69template <class>
70class BaseDynInst;
71class ThreadContext;
72class Request;
73
74/**
75 * CheckerCPU class.  Dynamically verifies instructions as they are
76 * completed by making sure that the instruction and its results match
77 * the independent execution of the benchmark inside the checker.  The
78 * checker verifies instructions in order, regardless of the order in
79 * which instructions complete.  There are certain results that can
80 * not be verified, specifically the result of a store conditional or
81 * the values of uncached accesses.  In these cases, and with
82 * instructions marked as "IsUnverifiable", the checker assumes that
83 * the value from the main CPU's execution is correct and simply
84 * copies that value.  It provides a CheckerThreadContext (see
85 * checker/thread_context.hh) that provides hooks for updating the
86 * Checker's state through any ThreadContext accesses.  This allows the
87 * checker to be able to correctly verify instructions, even with
88 * external accesses to the ThreadContext that change state.
89 */
90class CheckerCPU : public BaseCPU, public ExecContext
91{
92  protected:
93    typedef TheISA::MachInst MachInst;
94    typedef TheISA::FloatReg FloatReg;
95    typedef TheISA::FloatRegBits FloatRegBits;
96    typedef TheISA::MiscReg MiscReg;
97
98    /** id attached to all issued requests */
99    MasterID masterId;
100  public:
101    void init() override;
102
103    typedef CheckerCPUParams Params;
104    CheckerCPU(Params *p);
105    virtual ~CheckerCPU();
106
107    void setSystem(System *system);
108
109    void setIcachePort(MasterPort *icache_port);
110
111    void setDcachePort(MasterPort *dcache_port);
112
113    MasterPort &getDataPort() override
114    {
115        // the checker does not have ports on its own so return the
116        // data port of the actual CPU core
117        assert(dcachePort);
118        return *dcachePort;
119    }
120
121    MasterPort &getInstPort() override
122    {
123        // the checker does not have ports on its own so return the
124        // data port of the actual CPU core
125        assert(icachePort);
126        return *icachePort;
127    }
128
129  protected:
130
131    std::vector<Process*> workload;
132
133    System *systemPtr;
134
135    MasterPort *icachePort;
136    MasterPort *dcachePort;
137
138    ThreadContext *tc;
139
140    TheISA::TLB *itb;
141    TheISA::TLB *dtb;
142
143    Addr dbg_vtophys(Addr addr);
144
145    union Result {
146        uint64_t integer;
147        double dbl;
148        void set(uint64_t i) { integer = i; }
149        void set(double d) { dbl = d; }
150        void get(uint64_t& i) { i = integer; }
151        void get(double& d) { d = dbl; }
152    };
153
154    // ISAs like ARM can have multiple destination registers to check,
155    // keep them all in a std::queue
156    std::queue<Result> result;
157
158    // Pointer to the one memory request.
159    RequestPtr memReq;
160
161    StaticInstPtr curStaticInst;
162    StaticInstPtr curMacroStaticInst;
163
164    // number of simulated instructions
165    Counter numInst;
166    Counter startNumInst;
167
168    std::queue<int> miscRegIdxs;
169
170  public:
171
172    // Primary thread being run.
173    SimpleThread *thread;
174
175    TheISA::TLB* getITBPtr() { return itb; }
176    TheISA::TLB* getDTBPtr() { return dtb; }
177
178    virtual Counter totalInsts() const override
179    {
180        return 0;
181    }
182
183    virtual Counter totalOps() const override
184    {
185        return 0;
186    }
187
188    // number of simulated loads
189    Counter numLoad;
190    Counter startNumLoad;
191
192    void serialize(CheckpointOut &cp) const override;
193    void unserialize(CheckpointIn &cp) override;
194
195    // These functions are only used in CPU models that split
196    // effective address computation from the actual memory access.
197    void setEA(Addr EA) override
198    { panic("CheckerCPU::setEA() not implemented\n"); }
199    Addr getEA() const  override
200    { panic("CheckerCPU::getEA() not implemented\n"); }
201
202    // The register accessor methods provide the index of the
203    // instruction's operand (e.g., 0 or 1), not the architectural
204    // register index, to simplify the implementation of register
205    // renaming.  We find the architectural register index by indexing
206    // into the instruction's own operand index table.  Note that a
207    // raw pointer to the StaticInst is provided instead of a
208    // ref-counted StaticInstPtr to redice overhead.  This is fine as
209    // long as these methods don't copy the pointer into any long-term
210    // storage (which is pretty hard to imagine they would have reason
211    // to do).
212
213    IntReg readIntRegOperand(const StaticInst *si, int idx) override
214    {
215        return thread->readIntReg(si->srcRegIdx(idx));
216    }
217
218    FloatReg readFloatRegOperand(const StaticInst *si, int idx) override
219    {
220        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
221        return thread->readFloatReg(reg_idx);
222    }
223
224    FloatRegBits readFloatRegOperandBits(const StaticInst *si,
225                                         int idx) override
226    {
227        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
228        return thread->readFloatRegBits(reg_idx);
229    }
230
231    CCReg readCCRegOperand(const StaticInst *si, int idx) override
232    {
233        int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
234        return thread->readCCReg(reg_idx);
235    }
236
237    template <class T>
238    void setResult(T t)
239    {
240        Result instRes;
241        instRes.set(t);
242        result.push(instRes);
243    }
244
245    void setIntRegOperand(const StaticInst *si, int idx,
246                          IntReg val) override
247    {
248        thread->setIntReg(si->destRegIdx(idx), val);
249        setResult<uint64_t>(val);
250    }
251
252    void setFloatRegOperand(const StaticInst *si, int idx,
253                            FloatReg val) override
254    {
255        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
256        thread->setFloatReg(reg_idx, val);
257        setResult<double>(val);
258    }
259
260    void setFloatRegOperandBits(const StaticInst *si, int idx,
261                                FloatRegBits val) override
262    {
263        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
264        thread->setFloatRegBits(reg_idx, val);
265        setResult<uint64_t>(val);
266    }
267
268    void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
269    {
270        int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
271        thread->setCCReg(reg_idx, val);
272        setResult<uint64_t>(val);
273    }
274
275    bool readPredicate() override { return thread->readPredicate(); }
276    void setPredicate(bool val) override
277    {
278        thread->setPredicate(val);
279    }
280
281    TheISA::PCState pcState() const override { return thread->pcState(); }
282    void pcState(const TheISA::PCState &val) override
283    {
284        DPRINTF(Checker, "Changing PC to %s, old PC %s.\n",
285                         val, thread->pcState());
286        thread->pcState(val);
287    }
288    Addr instAddr() { return thread->instAddr(); }
289    Addr nextInstAddr() { return thread->nextInstAddr(); }
290    MicroPC microPC() { return thread->microPC(); }
291    //////////////////////////////////////////
292
293    MiscReg readMiscRegNoEffect(int misc_reg) const
294    {
295        return thread->readMiscRegNoEffect(misc_reg);
296    }
297
298    MiscReg readMiscReg(int misc_reg) override
299    {
300        return thread->readMiscReg(misc_reg);
301    }
302
303    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
304    {
305        DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n", misc_reg);
306        miscRegIdxs.push(misc_reg);
307        return thread->setMiscRegNoEffect(misc_reg, val);
308    }
309
310    void setMiscReg(int misc_reg, const MiscReg &val) override
311    {
312        DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg);
313        miscRegIdxs.push(misc_reg);
314        return thread->setMiscReg(misc_reg, val);
315    }
316
317    MiscReg readMiscRegOperand(const StaticInst *si, int idx) override
318    {
319        int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
320        return thread->readMiscReg(reg_idx);
321    }
322
323    void setMiscRegOperand(const StaticInst *si, int idx,
324                           const MiscReg &val) override
325    {
326        int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
327        return this->setMiscReg(reg_idx, val);
328    }
329
330#if THE_ISA == MIPS_ISA
331    MiscReg readRegOtherThread(int misc_reg, ThreadID tid)
332    {
333        panic("MIPS MT not defined for CheckerCPU.\n");
334        return 0;
335    }
336
337    void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid)
338    {
339        panic("MIPS MT not defined for CheckerCPU.\n");
340    }
341#endif
342
343    /////////////////////////////////////////
344
345    void recordPCChange(const TheISA::PCState &val)
346    {
347       changedPC = true;
348       newPCState = val;
349    }
350
351    void demapPage(Addr vaddr, uint64_t asn) override
352    {
353        this->itb->demapPage(vaddr, asn);
354        this->dtb->demapPage(vaddr, asn);
355    }
356
357    // monitor/mwait funtions
358    void armMonitor(Addr address) override
359    { BaseCPU::armMonitor(0, address); }
360    bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); }
361    void mwaitAtomic(ThreadContext *tc) override
362    { return BaseCPU::mwaitAtomic(0, tc, thread->dtb); }
363    AddressMonitor *getAddrMonitor() override
364    { return BaseCPU::getCpuAddrMonitor(0); }
365
366    void demapInstPage(Addr vaddr, uint64_t asn)
367    {
368        this->itb->demapPage(vaddr, asn);
369    }
370
371    void demapDataPage(Addr vaddr, uint64_t asn)
372    {
373        this->dtb->demapPage(vaddr, asn);
374    }
375
376    Fault readMem(Addr addr, uint8_t *data, unsigned size,
377                  unsigned flags) override;
378    Fault writeMem(uint8_t *data, unsigned size,
379                   Addr addr, unsigned flags, uint64_t *res) override;
380
381    unsigned int readStCondFailures() const override {
382        return thread->readStCondFailures();
383    }
384
385    void setStCondFailures(unsigned int sc_failures) override
386    {}
387    /////////////////////////////////////////////////////
388
389    Fault hwrei() override { return thread->hwrei(); }
390    bool simPalCheck(int palFunc) override
391    { return thread->simPalCheck(palFunc); }
392    void wakeup(ThreadID tid) override { }
393    // Assume that the normal CPU's call to syscall was successful.
394    // The checker's state would have already been updated by the syscall.
395    void syscall(int64_t callnum) override { }
396
397    void handleError()
398    {
399        if (exitOnError)
400            dumpAndExit();
401    }
402
403    bool checkFlags(Request *unverified_req, Addr vAddr,
404                    Addr pAddr, int flags);
405
406    void dumpAndExit();
407
408    ThreadContext *tcBase() override { return tc; }
409    SimpleThread *threadBase() { return thread; }
410
411    Result unverifiedResult;
412    Request *unverifiedReq;
413    uint8_t *unverifiedMemData;
414
415    bool changedPC;
416    bool willChangePC;
417    TheISA::PCState newPCState;
418    bool exitOnError;
419    bool updateOnError;
420    bool warnOnlyOnLoadError;
421
422    InstSeqNum youngestSN;
423};
424
425/**
426 * Templated Checker class.  This Checker class is templated on the
427 * DynInstPtr of the instruction type that will be verified.  Proper
428 * template instantiations of the Checker must be placed at the bottom
429 * of checker/cpu.cc.
430 */
431template <class Impl>
432class Checker : public CheckerCPU
433{
434  private:
435    typedef typename Impl::DynInstPtr DynInstPtr;
436
437  public:
438    Checker(Params *p)
439        : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL)
440    { }
441
442    void switchOut();
443    void takeOverFrom(BaseCPU *oldCPU);
444
445    void advancePC(const Fault &fault);
446
447    void verify(DynInstPtr &inst);
448
449    void validateInst(DynInstPtr &inst);
450    void validateExecution(DynInstPtr &inst);
451    void validateState();
452
453    void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx);
454    void handlePendingInt();
455
456  private:
457    void handleError(DynInstPtr &inst)
458    {
459        if (exitOnError) {
460            dumpAndExit(inst);
461        } else if (updateOnError) {
462            updateThisCycle = true;
463        }
464    }
465
466    void dumpAndExit(DynInstPtr &inst);
467
468    bool updateThisCycle;
469
470    DynInstPtr unverifiedInst;
471
472    std::list<DynInstPtr> instList;
473    typedef typename std::list<DynInstPtr>::iterator InstListIt;
474    void dumpInsts();
475};
476
477#endif // __CPU_CHECKER_CPU_HH__
478