cpu.hh revision 6022
12315SN/A/* 22332SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32315SN/A * All rights reserved. 42315SN/A * 52315SN/A * Redistribution and use in source and binary forms, with or without 62315SN/A * modification, are permitted provided that the following conditions are 72315SN/A * met: redistributions of source code must retain the above copyright 82315SN/A * notice, this list of conditions and the following disclaimer; 92315SN/A * redistributions in binary form must reproduce the above copyright 102315SN/A * notice, this list of conditions and the following disclaimer in the 112315SN/A * documentation and/or other materials provided with the distribution; 122315SN/A * neither the name of the copyright holders nor the names of its 132315SN/A * contributors may be used to endorse or promote products derived from 142315SN/A * this software without specific prior written permission. 152315SN/A * 162315SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172315SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182315SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192315SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202315SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212315SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232315SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242315SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252315SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262315SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292315SN/A */ 302315SN/A 312315SN/A#ifndef __CPU_CHECKER_CPU_HH__ 322315SN/A#define __CPU_CHECKER_CPU_HH__ 332315SN/A 342315SN/A#include <list> 352315SN/A#include <queue> 362315SN/A#include <map> 372315SN/A 382669Sktlim@umich.edu#include "arch/types.hh" 392315SN/A#include "base/statistics.hh" 402315SN/A#include "config/full_system.hh" 412315SN/A#include "cpu/base.hh" 422315SN/A#include "cpu/base_dyn_inst.hh" 432683Sktlim@umich.edu#include "cpu/simple_thread.hh" 442315SN/A#include "cpu/pc_event.hh" 452315SN/A#include "cpu/static_inst.hh" 462315SN/A#include "sim/eventq.hh" 472315SN/A 482315SN/A// forward declarations 492315SN/A#if FULL_SYSTEM 503468Sgblack@eecs.umich.edunamespace TheISA 513468Sgblack@eecs.umich.edu{ 526022Sgblack@eecs.umich.edu class TLB; 533468Sgblack@eecs.umich.edu} 542315SN/Aclass Processor; 552315SN/Aclass PhysicalMemory; 562315SN/A 572315SN/Aclass RemoteGDB; 582315SN/Aclass GDBListener; 592315SN/A 602315SN/A#else 612315SN/A 622315SN/Aclass Process; 632315SN/A 642315SN/A#endif // FULL_SYSTEM 652315SN/Atemplate <class> 662315SN/Aclass BaseDynInst; 675529Snate@binkert.orgclass CheckerCPUParams; 682680Sktlim@umich.educlass ThreadContext; 692315SN/Aclass MemInterface; 702315SN/Aclass Checkpoint; 712669Sktlim@umich.educlass Request; 722315SN/A 732350SN/A/** 742350SN/A * CheckerCPU class. Dynamically verifies instructions as they are 752350SN/A * completed by making sure that the instruction and its results match 762350SN/A * the independent execution of the benchmark inside the checker. The 772350SN/A * checker verifies instructions in order, regardless of the order in 782350SN/A * which instructions complete. There are certain results that can 792350SN/A * not be verified, specifically the result of a store conditional or 802350SN/A * the values of uncached accesses. In these cases, and with 812350SN/A * instructions marked as "IsUnverifiable", the checker assumes that 822350SN/A * the value from the main CPU's execution is correct and simply 832680Sktlim@umich.edu * copies that value. It provides a CheckerThreadContext (see 842683Sktlim@umich.edu * checker/thread_context.hh) that provides hooks for updating the 852680Sktlim@umich.edu * Checker's state through any ThreadContext accesses. This allows the 862350SN/A * checker to be able to correctly verify instructions, even with 872680Sktlim@umich.edu * external accesses to the ThreadContext that change state. 882350SN/A */ 892315SN/Aclass CheckerCPU : public BaseCPU 902315SN/A{ 912315SN/A protected: 922315SN/A typedef TheISA::MachInst MachInst; 932669Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 942669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 952315SN/A typedef TheISA::MiscReg MiscReg; 962315SN/A public: 972315SN/A virtual void init(); 982315SN/A 992315SN/A public: 1005529Snate@binkert.org typedef CheckerCPUParams Params; 1015529Snate@binkert.org const Params *params() const 1025529Snate@binkert.org { return reinterpret_cast<const Params *>(_params); } 1032315SN/A CheckerCPU(Params *p); 1042315SN/A virtual ~CheckerCPU(); 1052315SN/A 1062679Sktlim@umich.edu Process *process; 1072679Sktlim@umich.edu 1082315SN/A void setSystem(System *system); 1092315SN/A 1102315SN/A System *systemPtr; 1112679Sktlim@umich.edu 1122679Sktlim@umich.edu void setIcachePort(Port *icache_port); 1132679Sktlim@umich.edu 1142679Sktlim@umich.edu Port *icachePort; 1152679Sktlim@umich.edu 1162679Sktlim@umich.edu void setDcachePort(Port *dcache_port); 1172679Sktlim@umich.edu 1182679Sktlim@umich.edu Port *dcachePort; 1192679Sktlim@umich.edu 1202871Sktlim@umich.edu virtual Port *getPort(const std::string &name, int idx) 1212871Sktlim@umich.edu { 1222871Sktlim@umich.edu panic("Not supported on checker!"); 1232871Sktlim@umich.edu return NULL; 1242871Sktlim@umich.edu } 1252871Sktlim@umich.edu 1262315SN/A public: 1272683Sktlim@umich.edu // Primary thread being run. 1282683Sktlim@umich.edu SimpleThread *thread; 1292315SN/A 1302680Sktlim@umich.edu ThreadContext *tc; 1312315SN/A 1326022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1336022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1342315SN/A 1352315SN/A#if FULL_SYSTEM 1362315SN/A Addr dbg_vtophys(Addr addr); 1372315SN/A#endif 1382315SN/A 1392315SN/A union Result { 1402315SN/A uint64_t integer; 1412360SN/A// float fp; 1422315SN/A double dbl; 1432315SN/A }; 1442315SN/A 1452315SN/A Result result; 1462315SN/A 1472315SN/A // current instruction 1482315SN/A MachInst machInst; 1492315SN/A 1502679Sktlim@umich.edu // Pointer to the one memory request. 1512679Sktlim@umich.edu RequestPtr memReq; 1522315SN/A 1532315SN/A StaticInstPtr curStaticInst; 1542315SN/A 1552315SN/A // number of simulated instructions 1562315SN/A Counter numInst; 1572315SN/A Counter startNumInst; 1582315SN/A 1592315SN/A std::queue<int> miscRegIdxs; 1602315SN/A 1612315SN/A virtual Counter totalInstructions() const 1622315SN/A { 1632930Sktlim@umich.edu return 0; 1642315SN/A } 1652315SN/A 1662315SN/A // number of simulated loads 1672315SN/A Counter numLoad; 1682315SN/A Counter startNumLoad; 1692315SN/A 1702315SN/A virtual void serialize(std::ostream &os); 1712315SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1722315SN/A 1732315SN/A template <class T> 1742315SN/A Fault read(Addr addr, T &data, unsigned flags); 1752315SN/A 1762315SN/A template <class T> 1772315SN/A Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1782315SN/A 1792315SN/A // These functions are only used in CPU models that split 1802315SN/A // effective address computation from the actual memory access. 1812315SN/A void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } 1825543Ssaidi@eecs.umich.edu Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); } 1832315SN/A 1842315SN/A void prefetch(Addr addr, unsigned flags) 1852315SN/A { 1862315SN/A // need to do this... 1872315SN/A } 1882315SN/A 1892315SN/A void writeHint(Addr addr, int size, unsigned flags) 1902315SN/A { 1912315SN/A // need to do this... 1922315SN/A } 1932315SN/A 1942315SN/A Fault copySrcTranslate(Addr src); 1952315SN/A 1962315SN/A Fault copy(Addr dest); 1972315SN/A 1982315SN/A // The register accessor methods provide the index of the 1992315SN/A // instruction's operand (e.g., 0 or 1), not the architectural 2002315SN/A // register index, to simplify the implementation of register 2012315SN/A // renaming. We find the architectural register index by indexing 2022315SN/A // into the instruction's own operand index table. Note that a 2032315SN/A // raw pointer to the StaticInst is provided instead of a 2042315SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 2052315SN/A // long as these methods don't copy the pointer into any long-term 2062315SN/A // storage (which is pretty hard to imagine they would have reason 2072315SN/A // to do). 2082315SN/A 2093735Sstever@eecs.umich.edu uint64_t readIntRegOperand(const StaticInst *si, int idx) 2102315SN/A { 2112683Sktlim@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 2122315SN/A } 2132315SN/A 2143735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) 2152315SN/A { 2162315SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2172683Sktlim@umich.edu return thread->readFloatReg(reg_idx, width); 2182315SN/A } 2192315SN/A 2203735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx) 2212315SN/A { 2222315SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2232683Sktlim@umich.edu return thread->readFloatReg(reg_idx); 2242315SN/A } 2252315SN/A 2263735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, 2273735Sstever@eecs.umich.edu int width) 2282315SN/A { 2292315SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2302683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx, width); 2312669Sktlim@umich.edu } 2322669Sktlim@umich.edu 2333735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 2342669Sktlim@umich.edu { 2352669Sktlim@umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2362683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx); 2372315SN/A } 2382315SN/A 2393735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 2402315SN/A { 2412683Sktlim@umich.edu thread->setIntReg(si->destRegIdx(idx), val); 2422315SN/A result.integer = val; 2432315SN/A } 2442315SN/A 2453735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 2463735Sstever@eecs.umich.edu int width) 2472315SN/A { 2482315SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2492683Sktlim@umich.edu thread->setFloatReg(reg_idx, val, width); 2502669Sktlim@umich.edu switch(width) { 2512669Sktlim@umich.edu case 32: 2523126Sktlim@umich.edu result.dbl = (double)val; 2532669Sktlim@umich.edu break; 2542669Sktlim@umich.edu case 64: 2552669Sktlim@umich.edu result.dbl = val; 2562669Sktlim@umich.edu break; 2572669Sktlim@umich.edu }; 2582669Sktlim@umich.edu } 2592669Sktlim@umich.edu 2603735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 2612669Sktlim@umich.edu { 2622669Sktlim@umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2632683Sktlim@umich.edu thread->setFloatReg(reg_idx, val); 2642360SN/A result.dbl = (double)val; 2652315SN/A } 2662315SN/A 2673735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 2683735Sstever@eecs.umich.edu FloatRegBits val, int width) 2692315SN/A { 2702315SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2712683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val, width); 2722669Sktlim@umich.edu result.integer = val; 2732315SN/A } 2742315SN/A 2753735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 2763735Sstever@eecs.umich.edu FloatRegBits val) 2772315SN/A { 2782315SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2792683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val); 2802315SN/A result.integer = val; 2812315SN/A } 2822315SN/A 2832683Sktlim@umich.edu uint64_t readPC() { return thread->readPC(); } 2842669Sktlim@umich.edu 2852683Sktlim@umich.edu uint64_t readNextPC() { return thread->readNextPC(); } 2862669Sktlim@umich.edu 2872315SN/A void setNextPC(uint64_t val) { 2882683Sktlim@umich.edu thread->setNextPC(val); 2892315SN/A } 2902315SN/A 2914172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 2924172Ssaidi@eecs.umich.edu { 2934172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 2944172Ssaidi@eecs.umich.edu } 2954172Ssaidi@eecs.umich.edu 2962315SN/A MiscReg readMiscReg(int misc_reg) 2972315SN/A { 2982683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 2992315SN/A } 3002315SN/A 3014172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3022315SN/A { 3034172Ssaidi@eecs.umich.edu result.integer = val; 3044172Ssaidi@eecs.umich.edu miscRegIdxs.push(misc_reg); 3054172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(misc_reg, val); 3062315SN/A } 3072315SN/A 3083468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 3092315SN/A { 3102315SN/A miscRegIdxs.push(misc_reg); 3112683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 3122315SN/A } 3132315SN/A 3142360SN/A void recordPCChange(uint64_t val) { changedPC = true; newPC = val; } 3152315SN/A void recordNextPCChange(uint64_t val) { changedNextPC = true; } 3162315SN/A 3175358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 3185358Sgblack@eecs.umich.edu { 3195358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3205358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3215358Sgblack@eecs.umich.edu } 3225358Sgblack@eecs.umich.edu 3235358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 3245358Sgblack@eecs.umich.edu { 3255358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3265358Sgblack@eecs.umich.edu } 3275358Sgblack@eecs.umich.edu 3285358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 3295358Sgblack@eecs.umich.edu { 3305358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3315358Sgblack@eecs.umich.edu } 3325358Sgblack@eecs.umich.edu 3332315SN/A#if FULL_SYSTEM 3345702Ssaidi@eecs.umich.edu Fault hwrei() { return thread->hwrei(); } 3352690Sktlim@umich.edu void ev5_trap(Fault fault) { fault->invoke(tc); } 3365702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 3372315SN/A#else 3382315SN/A // Assume that the normal CPU's call to syscall was successful. 3392332SN/A // The checker's state would have already been updated by the syscall. 3402669Sktlim@umich.edu void syscall(uint64_t callnum) { } 3412315SN/A#endif 3422315SN/A 3432315SN/A void handleError() 3442315SN/A { 3452315SN/A if (exitOnError) 3462732Sktlim@umich.edu dumpAndExit(); 3472315SN/A } 3482732Sktlim@umich.edu 3492669Sktlim@umich.edu bool checkFlags(Request *req); 3502315SN/A 3512732Sktlim@umich.edu void dumpAndExit(); 3522732Sktlim@umich.edu 3532680Sktlim@umich.edu ThreadContext *tcBase() { return tc; } 3542683Sktlim@umich.edu SimpleThread *threadBase() { return thread; } 3552315SN/A 3562315SN/A Result unverifiedResult; 3572669Sktlim@umich.edu Request *unverifiedReq; 3582679Sktlim@umich.edu uint8_t *unverifiedMemData; 3592315SN/A 3602315SN/A bool changedPC; 3612315SN/A bool willChangePC; 3622315SN/A uint64_t newPC; 3632315SN/A bool changedNextPC; 3642315SN/A bool exitOnError; 3652354SN/A bool updateOnError; 3662732Sktlim@umich.edu bool warnOnlyOnLoadError; 3672315SN/A 3682315SN/A InstSeqNum youngestSN; 3692315SN/A}; 3702315SN/A 3712350SN/A/** 3722350SN/A * Templated Checker class. This Checker class is templated on the 3732350SN/A * DynInstPtr of the instruction type that will be verified. Proper 3742350SN/A * template instantiations of the Checker must be placed at the bottom 3752350SN/A * of checker/cpu.cc. 3762350SN/A */ 3772315SN/Atemplate <class DynInstPtr> 3782315SN/Aclass Checker : public CheckerCPU 3792315SN/A{ 3802315SN/A public: 3812315SN/A Checker(Params *p) 3822354SN/A : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL) 3832315SN/A { } 3842315SN/A 3852840Sktlim@umich.edu void switchOut(); 3862315SN/A void takeOverFrom(BaseCPU *oldCPU); 3872315SN/A 3882732Sktlim@umich.edu void verify(DynInstPtr &inst); 3892315SN/A 3902315SN/A void validateInst(DynInstPtr &inst); 3912315SN/A void validateExecution(DynInstPtr &inst); 3922315SN/A void validateState(); 3932315SN/A 3942732Sktlim@umich.edu void copyResult(DynInstPtr &inst); 3952732Sktlim@umich.edu 3962732Sktlim@umich.edu private: 3972732Sktlim@umich.edu void handleError(DynInstPtr &inst) 3982732Sktlim@umich.edu { 3992360SN/A if (exitOnError) { 4002732Sktlim@umich.edu dumpAndExit(inst); 4012360SN/A } else if (updateOnError) { 4022354SN/A updateThisCycle = true; 4032360SN/A } 4042732Sktlim@umich.edu } 4052732Sktlim@umich.edu 4062732Sktlim@umich.edu void dumpAndExit(DynInstPtr &inst); 4072732Sktlim@umich.edu 4082354SN/A bool updateThisCycle; 4092354SN/A 4102354SN/A DynInstPtr unverifiedInst; 4112354SN/A 4122315SN/A std::list<DynInstPtr> instList; 4132315SN/A typedef typename std::list<DynInstPtr>::iterator InstListIt; 4142315SN/A void dumpInsts(); 4152315SN/A}; 4162315SN/A 4172315SN/A#endif // __CPU_CHECKER_CPU_HH__ 418