cpu.hh revision 3126
12315SN/A/* 22332SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32315SN/A * All rights reserved. 42315SN/A * 52315SN/A * Redistribution and use in source and binary forms, with or without 62315SN/A * modification, are permitted provided that the following conditions are 72315SN/A * met: redistributions of source code must retain the above copyright 82315SN/A * notice, this list of conditions and the following disclaimer; 92315SN/A * redistributions in binary form must reproduce the above copyright 102315SN/A * notice, this list of conditions and the following disclaimer in the 112315SN/A * documentation and/or other materials provided with the distribution; 122315SN/A * neither the name of the copyright holders nor the names of its 132315SN/A * contributors may be used to endorse or promote products derived from 142315SN/A * this software without specific prior written permission. 152315SN/A * 162315SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172315SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182315SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192315SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202315SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212315SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232315SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242315SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252315SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262315SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292315SN/A */ 302315SN/A 312315SN/A#ifndef __CPU_CHECKER_CPU_HH__ 322315SN/A#define __CPU_CHECKER_CPU_HH__ 332315SN/A 342315SN/A#include <list> 352315SN/A#include <queue> 362315SN/A#include <map> 372315SN/A 382669Sktlim@umich.edu#include "arch/types.hh" 392315SN/A#include "base/statistics.hh" 402315SN/A#include "config/full_system.hh" 412315SN/A#include "cpu/base.hh" 422315SN/A#include "cpu/base_dyn_inst.hh" 432683Sktlim@umich.edu#include "cpu/simple_thread.hh" 442315SN/A#include "cpu/pc_event.hh" 452315SN/A#include "cpu/static_inst.hh" 462315SN/A#include "sim/eventq.hh" 472315SN/A 482315SN/A// forward declarations 492315SN/A#if FULL_SYSTEM 502315SN/Aclass Processor; 512315SN/Aclass AlphaITB; 522315SN/Aclass AlphaDTB; 532315SN/Aclass PhysicalMemory; 542315SN/A 552315SN/Aclass RemoteGDB; 562315SN/Aclass GDBListener; 572315SN/A 582315SN/A#else 592315SN/A 602315SN/Aclass Process; 612315SN/A 622315SN/A#endif // FULL_SYSTEM 632315SN/Atemplate <class> 642315SN/Aclass BaseDynInst; 652680Sktlim@umich.educlass ThreadContext; 662315SN/Aclass MemInterface; 672315SN/Aclass Checkpoint; 682669Sktlim@umich.educlass Request; 692315SN/A 702350SN/A/** 712350SN/A * CheckerCPU class. Dynamically verifies instructions as they are 722350SN/A * completed by making sure that the instruction and its results match 732350SN/A * the independent execution of the benchmark inside the checker. The 742350SN/A * checker verifies instructions in order, regardless of the order in 752350SN/A * which instructions complete. There are certain results that can 762350SN/A * not be verified, specifically the result of a store conditional or 772350SN/A * the values of uncached accesses. In these cases, and with 782350SN/A * instructions marked as "IsUnverifiable", the checker assumes that 792350SN/A * the value from the main CPU's execution is correct and simply 802680Sktlim@umich.edu * copies that value. It provides a CheckerThreadContext (see 812683Sktlim@umich.edu * checker/thread_context.hh) that provides hooks for updating the 822680Sktlim@umich.edu * Checker's state through any ThreadContext accesses. This allows the 832350SN/A * checker to be able to correctly verify instructions, even with 842680Sktlim@umich.edu * external accesses to the ThreadContext that change state. 852350SN/A */ 862315SN/Aclass CheckerCPU : public BaseCPU 872315SN/A{ 882315SN/A protected: 892315SN/A typedef TheISA::MachInst MachInst; 902669Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 912669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 922315SN/A typedef TheISA::MiscReg MiscReg; 932315SN/A public: 942315SN/A virtual void init(); 952315SN/A 962315SN/A struct Params : public BaseCPU::Params 972315SN/A { 982315SN/A#if FULL_SYSTEM 992315SN/A AlphaITB *itb; 1002315SN/A AlphaDTB *dtb; 1012315SN/A#else 1022315SN/A Process *process; 1032315SN/A#endif 1042315SN/A bool exitOnError; 1052354SN/A bool updateOnError; 1062732Sktlim@umich.edu bool warnOnlyOnLoadError; 1072315SN/A }; 1082315SN/A 1092315SN/A public: 1102315SN/A CheckerCPU(Params *p); 1112315SN/A virtual ~CheckerCPU(); 1122315SN/A 1132679Sktlim@umich.edu Process *process; 1142679Sktlim@umich.edu 1152669Sktlim@umich.edu void setMemory(MemObject *mem); 1162315SN/A 1172669Sktlim@umich.edu MemObject *memPtr; 1182315SN/A 1192315SN/A void setSystem(System *system); 1202315SN/A 1212315SN/A System *systemPtr; 1222679Sktlim@umich.edu 1232679Sktlim@umich.edu void setIcachePort(Port *icache_port); 1242679Sktlim@umich.edu 1252679Sktlim@umich.edu Port *icachePort; 1262679Sktlim@umich.edu 1272679Sktlim@umich.edu void setDcachePort(Port *dcache_port); 1282679Sktlim@umich.edu 1292679Sktlim@umich.edu Port *dcachePort; 1302679Sktlim@umich.edu 1312871Sktlim@umich.edu virtual Port *getPort(const std::string &name, int idx) 1322871Sktlim@umich.edu { 1332871Sktlim@umich.edu panic("Not supported on checker!"); 1342871Sktlim@umich.edu return NULL; 1352871Sktlim@umich.edu } 1362871Sktlim@umich.edu 1372315SN/A public: 1382683Sktlim@umich.edu // Primary thread being run. 1392683Sktlim@umich.edu SimpleThread *thread; 1402315SN/A 1412680Sktlim@umich.edu ThreadContext *tc; 1422315SN/A 1432315SN/A AlphaITB *itb; 1442315SN/A AlphaDTB *dtb; 1452315SN/A 1462315SN/A#if FULL_SYSTEM 1472315SN/A Addr dbg_vtophys(Addr addr); 1482315SN/A#endif 1492315SN/A 1502315SN/A union Result { 1512315SN/A uint64_t integer; 1522360SN/A// float fp; 1532315SN/A double dbl; 1542315SN/A }; 1552315SN/A 1562315SN/A Result result; 1572315SN/A 1582315SN/A // current instruction 1592315SN/A MachInst machInst; 1602315SN/A 1612679Sktlim@umich.edu // Pointer to the one memory request. 1622679Sktlim@umich.edu RequestPtr memReq; 1632315SN/A 1642315SN/A StaticInstPtr curStaticInst; 1652315SN/A 1662315SN/A // number of simulated instructions 1672315SN/A Counter numInst; 1682315SN/A Counter startNumInst; 1692315SN/A 1702315SN/A std::queue<int> miscRegIdxs; 1712315SN/A 1722315SN/A virtual Counter totalInstructions() const 1732315SN/A { 1742930Sktlim@umich.edu return 0; 1752315SN/A } 1762315SN/A 1772315SN/A // number of simulated loads 1782315SN/A Counter numLoad; 1792315SN/A Counter startNumLoad; 1802315SN/A 1812315SN/A virtual void serialize(std::ostream &os); 1822315SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1832315SN/A 1842315SN/A template <class T> 1852315SN/A Fault read(Addr addr, T &data, unsigned flags); 1862315SN/A 1872315SN/A template <class T> 1882315SN/A Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1892315SN/A 1902315SN/A // These functions are only used in CPU models that split 1912315SN/A // effective address computation from the actual memory access. 1922315SN/A void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } 1932315SN/A Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); } 1942315SN/A 1952315SN/A void prefetch(Addr addr, unsigned flags) 1962315SN/A { 1972315SN/A // need to do this... 1982315SN/A } 1992315SN/A 2002315SN/A void writeHint(Addr addr, int size, unsigned flags) 2012315SN/A { 2022315SN/A // need to do this... 2032315SN/A } 2042315SN/A 2052315SN/A Fault copySrcTranslate(Addr src); 2062315SN/A 2072315SN/A Fault copy(Addr dest); 2082315SN/A 2092315SN/A // The register accessor methods provide the index of the 2102315SN/A // instruction's operand (e.g., 0 or 1), not the architectural 2112315SN/A // register index, to simplify the implementation of register 2122315SN/A // renaming. We find the architectural register index by indexing 2132315SN/A // into the instruction's own operand index table. Note that a 2142315SN/A // raw pointer to the StaticInst is provided instead of a 2152315SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 2162315SN/A // long as these methods don't copy the pointer into any long-term 2172315SN/A // storage (which is pretty hard to imagine they would have reason 2182315SN/A // to do). 2192315SN/A 2202315SN/A uint64_t readIntReg(const StaticInst *si, int idx) 2212315SN/A { 2222683Sktlim@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 2232315SN/A } 2242315SN/A 2252669Sktlim@umich.edu FloatReg readFloatReg(const StaticInst *si, int idx, int width) 2262315SN/A { 2272315SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2282683Sktlim@umich.edu return thread->readFloatReg(reg_idx, width); 2292315SN/A } 2302315SN/A 2312669Sktlim@umich.edu FloatReg readFloatReg(const StaticInst *si, int idx) 2322315SN/A { 2332315SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2342683Sktlim@umich.edu return thread->readFloatReg(reg_idx); 2352315SN/A } 2362315SN/A 2372669Sktlim@umich.edu FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width) 2382315SN/A { 2392315SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2402683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx, width); 2412669Sktlim@umich.edu } 2422669Sktlim@umich.edu 2432669Sktlim@umich.edu FloatRegBits readFloatRegBits(const StaticInst *si, int idx) 2442669Sktlim@umich.edu { 2452669Sktlim@umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2462683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx); 2472315SN/A } 2482315SN/A 2492315SN/A void setIntReg(const StaticInst *si, int idx, uint64_t val) 2502315SN/A { 2512683Sktlim@umich.edu thread->setIntReg(si->destRegIdx(idx), val); 2522315SN/A result.integer = val; 2532315SN/A } 2542315SN/A 2552669Sktlim@umich.edu void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width) 2562315SN/A { 2572315SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2582683Sktlim@umich.edu thread->setFloatReg(reg_idx, val, width); 2592669Sktlim@umich.edu switch(width) { 2602669Sktlim@umich.edu case 32: 2613126Sktlim@umich.edu result.dbl = (double)val; 2622669Sktlim@umich.edu break; 2632669Sktlim@umich.edu case 64: 2642669Sktlim@umich.edu result.dbl = val; 2652669Sktlim@umich.edu break; 2662669Sktlim@umich.edu }; 2672669Sktlim@umich.edu } 2682669Sktlim@umich.edu 2692669Sktlim@umich.edu void setFloatReg(const StaticInst *si, int idx, FloatReg val) 2702669Sktlim@umich.edu { 2712669Sktlim@umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2722683Sktlim@umich.edu thread->setFloatReg(reg_idx, val); 2732360SN/A result.dbl = (double)val; 2742315SN/A } 2752315SN/A 2762669Sktlim@umich.edu void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val, 2772669Sktlim@umich.edu int width) 2782315SN/A { 2792315SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2802683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val, width); 2812669Sktlim@umich.edu result.integer = val; 2822315SN/A } 2832315SN/A 2842669Sktlim@umich.edu void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val) 2852315SN/A { 2862315SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2872683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val); 2882315SN/A result.integer = val; 2892315SN/A } 2902315SN/A 2912683Sktlim@umich.edu uint64_t readPC() { return thread->readPC(); } 2922669Sktlim@umich.edu 2932683Sktlim@umich.edu uint64_t readNextPC() { return thread->readNextPC(); } 2942669Sktlim@umich.edu 2952315SN/A void setNextPC(uint64_t val) { 2962683Sktlim@umich.edu thread->setNextPC(val); 2972315SN/A } 2982315SN/A 2992315SN/A MiscReg readMiscReg(int misc_reg) 3002315SN/A { 3012683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 3022315SN/A } 3032315SN/A 3042315SN/A MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 3052315SN/A { 3062683Sktlim@umich.edu return thread->readMiscRegWithEffect(misc_reg, fault); 3072315SN/A } 3082315SN/A 3092315SN/A Fault setMiscReg(int misc_reg, const MiscReg &val) 3102315SN/A { 3112315SN/A result.integer = val; 3122315SN/A miscRegIdxs.push(misc_reg); 3132683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 3142315SN/A } 3152315SN/A 3162315SN/A Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 3172315SN/A { 3182315SN/A miscRegIdxs.push(misc_reg); 3192683Sktlim@umich.edu return thread->setMiscRegWithEffect(misc_reg, val); 3202315SN/A } 3212315SN/A 3222360SN/A void recordPCChange(uint64_t val) { changedPC = true; newPC = val; } 3232315SN/A void recordNextPCChange(uint64_t val) { changedNextPC = true; } 3242315SN/A 3252669Sktlim@umich.edu bool translateInstReq(Request *req); 3262669Sktlim@umich.edu void translateDataWriteReq(Request *req); 3272669Sktlim@umich.edu void translateDataReadReq(Request *req); 3282315SN/A 3292315SN/A#if FULL_SYSTEM 3302683Sktlim@umich.edu Fault hwrei() { return thread->hwrei(); } 3312683Sktlim@umich.edu int readIntrFlag() { return thread->readIntrFlag(); } 3322683Sktlim@umich.edu void setIntrFlag(int val) { thread->setIntrFlag(val); } 3332683Sktlim@umich.edu bool inPalMode() { return thread->inPalMode(); } 3342690Sktlim@umich.edu void ev5_trap(Fault fault) { fault->invoke(tc); } 3352683Sktlim@umich.edu bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 3362315SN/A#else 3372315SN/A // Assume that the normal CPU's call to syscall was successful. 3382332SN/A // The checker's state would have already been updated by the syscall. 3392669Sktlim@umich.edu void syscall(uint64_t callnum) { } 3402315SN/A#endif 3412315SN/A 3422315SN/A void handleError() 3432315SN/A { 3442315SN/A if (exitOnError) 3452732Sktlim@umich.edu dumpAndExit(); 3462315SN/A } 3472732Sktlim@umich.edu 3482669Sktlim@umich.edu bool checkFlags(Request *req); 3492315SN/A 3502732Sktlim@umich.edu void dumpAndExit(); 3512732Sktlim@umich.edu 3522680Sktlim@umich.edu ThreadContext *tcBase() { return tc; } 3532683Sktlim@umich.edu SimpleThread *threadBase() { return thread; } 3542315SN/A 3552315SN/A Result unverifiedResult; 3562669Sktlim@umich.edu Request *unverifiedReq; 3572679Sktlim@umich.edu uint8_t *unverifiedMemData; 3582315SN/A 3592315SN/A bool changedPC; 3602315SN/A bool willChangePC; 3612315SN/A uint64_t newPC; 3622315SN/A bool changedNextPC; 3632315SN/A bool exitOnError; 3642354SN/A bool updateOnError; 3652732Sktlim@umich.edu bool warnOnlyOnLoadError; 3662315SN/A 3672315SN/A InstSeqNum youngestSN; 3682315SN/A}; 3692315SN/A 3702350SN/A/** 3712350SN/A * Templated Checker class. This Checker class is templated on the 3722350SN/A * DynInstPtr of the instruction type that will be verified. Proper 3732350SN/A * template instantiations of the Checker must be placed at the bottom 3742350SN/A * of checker/cpu.cc. 3752350SN/A */ 3762315SN/Atemplate <class DynInstPtr> 3772315SN/Aclass Checker : public CheckerCPU 3782315SN/A{ 3792315SN/A public: 3802315SN/A Checker(Params *p) 3812354SN/A : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL) 3822315SN/A { } 3832315SN/A 3842840Sktlim@umich.edu void switchOut(); 3852315SN/A void takeOverFrom(BaseCPU *oldCPU); 3862315SN/A 3872732Sktlim@umich.edu void verify(DynInstPtr &inst); 3882315SN/A 3892315SN/A void validateInst(DynInstPtr &inst); 3902315SN/A void validateExecution(DynInstPtr &inst); 3912315SN/A void validateState(); 3922315SN/A 3932732Sktlim@umich.edu void copyResult(DynInstPtr &inst); 3942732Sktlim@umich.edu 3952732Sktlim@umich.edu private: 3962732Sktlim@umich.edu void handleError(DynInstPtr &inst) 3972732Sktlim@umich.edu { 3982360SN/A if (exitOnError) { 3992732Sktlim@umich.edu dumpAndExit(inst); 4002360SN/A } else if (updateOnError) { 4012354SN/A updateThisCycle = true; 4022360SN/A } 4032732Sktlim@umich.edu } 4042732Sktlim@umich.edu 4052732Sktlim@umich.edu void dumpAndExit(DynInstPtr &inst); 4062732Sktlim@umich.edu 4072354SN/A bool updateThisCycle; 4082354SN/A 4092354SN/A DynInstPtr unverifiedInst; 4102354SN/A 4112315SN/A std::list<DynInstPtr> instList; 4122315SN/A typedef typename std::list<DynInstPtr>::iterator InstListIt; 4132315SN/A void dumpInsts(); 4142315SN/A}; 4152315SN/A 4162315SN/A#endif // __CPU_CHECKER_CPU_HH__ 417