cpu.hh revision 2689
12315SN/A/* 22332SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32315SN/A * All rights reserved. 42315SN/A * 52315SN/A * Redistribution and use in source and binary forms, with or without 62315SN/A * modification, are permitted provided that the following conditions are 72315SN/A * met: redistributions of source code must retain the above copyright 82315SN/A * notice, this list of conditions and the following disclaimer; 92315SN/A * redistributions in binary form must reproduce the above copyright 102315SN/A * notice, this list of conditions and the following disclaimer in the 112315SN/A * documentation and/or other materials provided with the distribution; 122315SN/A * neither the name of the copyright holders nor the names of its 132315SN/A * contributors may be used to endorse or promote products derived from 142315SN/A * this software without specific prior written permission. 152315SN/A * 162315SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172315SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182315SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192315SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202315SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212315SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232315SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242315SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252315SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262315SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292315SN/A */ 302315SN/A 312315SN/A#ifndef __CPU_CHECKER_CPU_HH__ 322315SN/A#define __CPU_CHECKER_CPU_HH__ 332315SN/A 342315SN/A#include <list> 352315SN/A#include <queue> 362315SN/A#include <map> 372315SN/A 382669Sktlim@umich.edu#include "arch/types.hh" 392315SN/A#include "base/statistics.hh" 402315SN/A#include "config/full_system.hh" 412315SN/A#include "cpu/base.hh" 422315SN/A#include "cpu/base_dyn_inst.hh" 432683Sktlim@umich.edu#include "cpu/simple_thread.hh" 442315SN/A#include "cpu/pc_event.hh" 452315SN/A#include "cpu/static_inst.hh" 462315SN/A#include "sim/eventq.hh" 472315SN/A 482315SN/A// forward declarations 492315SN/A#if FULL_SYSTEM 502315SN/Aclass Processor; 512315SN/Aclass AlphaITB; 522315SN/Aclass AlphaDTB; 532315SN/Aclass PhysicalMemory; 542315SN/A 552315SN/Aclass RemoteGDB; 562315SN/Aclass GDBListener; 572315SN/A 582315SN/A#else 592315SN/A 602315SN/Aclass Process; 612315SN/A 622315SN/A#endif // FULL_SYSTEM 632315SN/Atemplate <class> 642315SN/Aclass BaseDynInst; 652680Sktlim@umich.educlass ThreadContext; 662315SN/Aclass MemInterface; 672315SN/Aclass Checkpoint; 682669Sktlim@umich.educlass Request; 692332SN/Aclass Sampler; 702315SN/A 712350SN/A/** 722350SN/A * CheckerCPU class. Dynamically verifies instructions as they are 732350SN/A * completed by making sure that the instruction and its results match 742350SN/A * the independent execution of the benchmark inside the checker. The 752350SN/A * checker verifies instructions in order, regardless of the order in 762350SN/A * which instructions complete. There are certain results that can 772350SN/A * not be verified, specifically the result of a store conditional or 782350SN/A * the values of uncached accesses. In these cases, and with 792350SN/A * instructions marked as "IsUnverifiable", the checker assumes that 802350SN/A * the value from the main CPU's execution is correct and simply 812680Sktlim@umich.edu * copies that value. It provides a CheckerThreadContext (see 822683Sktlim@umich.edu * checker/thread_context.hh) that provides hooks for updating the 832680Sktlim@umich.edu * Checker's state through any ThreadContext accesses. This allows the 842350SN/A * checker to be able to correctly verify instructions, even with 852680Sktlim@umich.edu * external accesses to the ThreadContext that change state. 862350SN/A */ 872315SN/Aclass CheckerCPU : public BaseCPU 882315SN/A{ 892315SN/A protected: 902315SN/A typedef TheISA::MachInst MachInst; 912669Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 922669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 932315SN/A typedef TheISA::MiscReg MiscReg; 942315SN/A public: 952315SN/A virtual void init(); 962315SN/A 972315SN/A struct Params : public BaseCPU::Params 982315SN/A { 992315SN/A#if FULL_SYSTEM 1002315SN/A AlphaITB *itb; 1012315SN/A AlphaDTB *dtb; 1022315SN/A FunctionalMemory *mem; 1032315SN/A#else 1042315SN/A Process *process; 1052315SN/A#endif 1062315SN/A bool exitOnError; 1072315SN/A }; 1082315SN/A 1092315SN/A public: 1102315SN/A CheckerCPU(Params *p); 1112315SN/A virtual ~CheckerCPU(); 1122315SN/A 1132679Sktlim@umich.edu Process *process; 1142679Sktlim@umich.edu 1152669Sktlim@umich.edu void setMemory(MemObject *mem); 1162315SN/A 1172669Sktlim@umich.edu MemObject *memPtr; 1182315SN/A 1192315SN/A#if FULL_SYSTEM 1202315SN/A void setSystem(System *system); 1212315SN/A 1222315SN/A System *systemPtr; 1232315SN/A#endif 1242679Sktlim@umich.edu 1252679Sktlim@umich.edu void setIcachePort(Port *icache_port); 1262679Sktlim@umich.edu 1272679Sktlim@umich.edu Port *icachePort; 1282679Sktlim@umich.edu 1292679Sktlim@umich.edu void setDcachePort(Port *dcache_port); 1302679Sktlim@umich.edu 1312679Sktlim@umich.edu Port *dcachePort; 1322679Sktlim@umich.edu 1332315SN/A public: 1342683Sktlim@umich.edu // Primary thread being run. 1352683Sktlim@umich.edu SimpleThread *thread; 1362315SN/A 1372680Sktlim@umich.edu ThreadContext *tc; 1382315SN/A 1392315SN/A AlphaITB *itb; 1402315SN/A AlphaDTB *dtb; 1412315SN/A 1422315SN/A#if FULL_SYSTEM 1432315SN/A Addr dbg_vtophys(Addr addr); 1442315SN/A#endif 1452315SN/A 1462315SN/A union Result { 1472315SN/A uint64_t integer; 1482315SN/A float fp; 1492315SN/A double dbl; 1502315SN/A }; 1512315SN/A 1522315SN/A Result result; 1532315SN/A 1542315SN/A // current instruction 1552315SN/A MachInst machInst; 1562315SN/A 1572679Sktlim@umich.edu // Pointer to the one memory request. 1582679Sktlim@umich.edu RequestPtr memReq; 1592315SN/A 1602315SN/A StaticInstPtr curStaticInst; 1612315SN/A 1622315SN/A // number of simulated instructions 1632315SN/A Counter numInst; 1642315SN/A Counter startNumInst; 1652315SN/A 1662315SN/A std::queue<int> miscRegIdxs; 1672315SN/A 1682315SN/A virtual Counter totalInstructions() const 1692315SN/A { 1702315SN/A return numInst - startNumInst; 1712315SN/A } 1722315SN/A 1732315SN/A // number of simulated loads 1742315SN/A Counter numLoad; 1752315SN/A Counter startNumLoad; 1762315SN/A 1772315SN/A virtual void serialize(std::ostream &os); 1782315SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1792315SN/A 1802315SN/A template <class T> 1812315SN/A Fault read(Addr addr, T &data, unsigned flags); 1822315SN/A 1832315SN/A template <class T> 1842315SN/A Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1852315SN/A 1862315SN/A // These functions are only used in CPU models that split 1872315SN/A // effective address computation from the actual memory access. 1882315SN/A void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } 1892315SN/A Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); } 1902315SN/A 1912315SN/A void prefetch(Addr addr, unsigned flags) 1922315SN/A { 1932315SN/A // need to do this... 1942315SN/A } 1952315SN/A 1962315SN/A void writeHint(Addr addr, int size, unsigned flags) 1972315SN/A { 1982315SN/A // need to do this... 1992315SN/A } 2002315SN/A 2012315SN/A Fault copySrcTranslate(Addr src); 2022315SN/A 2032315SN/A Fault copy(Addr dest); 2042315SN/A 2052315SN/A // The register accessor methods provide the index of the 2062315SN/A // instruction's operand (e.g., 0 or 1), not the architectural 2072315SN/A // register index, to simplify the implementation of register 2082315SN/A // renaming. We find the architectural register index by indexing 2092315SN/A // into the instruction's own operand index table. Note that a 2102315SN/A // raw pointer to the StaticInst is provided instead of a 2112315SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 2122315SN/A // long as these methods don't copy the pointer into any long-term 2132315SN/A // storage (which is pretty hard to imagine they would have reason 2142315SN/A // to do). 2152315SN/A 2162315SN/A uint64_t readIntReg(const StaticInst *si, int idx) 2172315SN/A { 2182683Sktlim@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 2192315SN/A } 2202315SN/A 2212669Sktlim@umich.edu FloatReg readFloatReg(const StaticInst *si, int idx, int width) 2222315SN/A { 2232315SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2242683Sktlim@umich.edu return thread->readFloatReg(reg_idx, width); 2252315SN/A } 2262315SN/A 2272669Sktlim@umich.edu FloatReg readFloatReg(const StaticInst *si, int idx) 2282315SN/A { 2292315SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2302683Sktlim@umich.edu return thread->readFloatReg(reg_idx); 2312315SN/A } 2322315SN/A 2332669Sktlim@umich.edu FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width) 2342315SN/A { 2352315SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2362683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx, width); 2372669Sktlim@umich.edu } 2382669Sktlim@umich.edu 2392669Sktlim@umich.edu FloatRegBits readFloatRegBits(const StaticInst *si, int idx) 2402669Sktlim@umich.edu { 2412669Sktlim@umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2422683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx); 2432315SN/A } 2442315SN/A 2452315SN/A void setIntReg(const StaticInst *si, int idx, uint64_t val) 2462315SN/A { 2472683Sktlim@umich.edu thread->setIntReg(si->destRegIdx(idx), val); 2482315SN/A result.integer = val; 2492315SN/A } 2502315SN/A 2512669Sktlim@umich.edu void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width) 2522315SN/A { 2532315SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2542683Sktlim@umich.edu thread->setFloatReg(reg_idx, val, width); 2552669Sktlim@umich.edu switch(width) { 2562669Sktlim@umich.edu case 32: 2572669Sktlim@umich.edu result.fp = val; 2582669Sktlim@umich.edu break; 2592669Sktlim@umich.edu case 64: 2602669Sktlim@umich.edu result.dbl = val; 2612669Sktlim@umich.edu break; 2622669Sktlim@umich.edu }; 2632669Sktlim@umich.edu } 2642669Sktlim@umich.edu 2652669Sktlim@umich.edu void setFloatReg(const StaticInst *si, int idx, FloatReg val) 2662669Sktlim@umich.edu { 2672669Sktlim@umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2682683Sktlim@umich.edu thread->setFloatReg(reg_idx, val); 2692315SN/A result.fp = val; 2702315SN/A } 2712315SN/A 2722669Sktlim@umich.edu void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val, 2732669Sktlim@umich.edu int width) 2742315SN/A { 2752315SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2762683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val, width); 2772669Sktlim@umich.edu result.integer = val; 2782315SN/A } 2792315SN/A 2802669Sktlim@umich.edu void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val) 2812315SN/A { 2822315SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2832683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val); 2842315SN/A result.integer = val; 2852315SN/A } 2862315SN/A 2872683Sktlim@umich.edu uint64_t readPC() { return thread->readPC(); } 2882669Sktlim@umich.edu 2892683Sktlim@umich.edu uint64_t readNextPC() { return thread->readNextPC(); } 2902669Sktlim@umich.edu 2912315SN/A void setNextPC(uint64_t val) { 2922683Sktlim@umich.edu thread->setNextPC(val); 2932315SN/A } 2942315SN/A 2952315SN/A MiscReg readMiscReg(int misc_reg) 2962315SN/A { 2972683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 2982315SN/A } 2992315SN/A 3002315SN/A MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 3012315SN/A { 3022683Sktlim@umich.edu return thread->readMiscRegWithEffect(misc_reg, fault); 3032315SN/A } 3042315SN/A 3052315SN/A Fault setMiscReg(int misc_reg, const MiscReg &val) 3062315SN/A { 3072315SN/A result.integer = val; 3082315SN/A miscRegIdxs.push(misc_reg); 3092683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 3102315SN/A } 3112315SN/A 3122315SN/A Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 3132315SN/A { 3142315SN/A miscRegIdxs.push(misc_reg); 3152683Sktlim@umich.edu return thread->setMiscRegWithEffect(misc_reg, val); 3162315SN/A } 3172315SN/A 3182315SN/A void recordPCChange(uint64_t val) { changedPC = true; } 3192315SN/A void recordNextPCChange(uint64_t val) { changedNextPC = true; } 3202315SN/A 3212669Sktlim@umich.edu bool translateInstReq(Request *req); 3222669Sktlim@umich.edu void translateDataWriteReq(Request *req); 3232669Sktlim@umich.edu void translateDataReadReq(Request *req); 3242315SN/A 3252315SN/A#if FULL_SYSTEM 3262683Sktlim@umich.edu Fault hwrei() { return thread->hwrei(); } 3272683Sktlim@umich.edu int readIntrFlag() { return thread->readIntrFlag(); } 3282683Sktlim@umich.edu void setIntrFlag(int val) { thread->setIntrFlag(val); } 3292683Sktlim@umich.edu bool inPalMode() { return thread->inPalMode(); } 3302315SN/A void ev5_trap(Fault fault) { fault->invoke(xcProxy); } 3312683Sktlim@umich.edu bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 3322315SN/A#else 3332315SN/A // Assume that the normal CPU's call to syscall was successful. 3342332SN/A // The checker's state would have already been updated by the syscall. 3352669Sktlim@umich.edu void syscall(uint64_t callnum) { } 3362315SN/A#endif 3372315SN/A 3382315SN/A void handleError() 3392315SN/A { 3402315SN/A if (exitOnError) 3412315SN/A panic("Checker found error!"); 3422315SN/A } 3432669Sktlim@umich.edu bool checkFlags(Request *req); 3442315SN/A 3452680Sktlim@umich.edu ThreadContext *tcBase() { return tc; } 3462683Sktlim@umich.edu SimpleThread *threadBase() { return thread; } 3472315SN/A 3482315SN/A Result unverifiedResult; 3492669Sktlim@umich.edu Request *unverifiedReq; 3502679Sktlim@umich.edu uint8_t *unverifiedMemData; 3512315SN/A 3522315SN/A bool changedPC; 3532315SN/A bool willChangePC; 3542315SN/A uint64_t newPC; 3552315SN/A bool changedNextPC; 3562315SN/A bool exitOnError; 3572315SN/A 3582315SN/A InstSeqNum youngestSN; 3592315SN/A}; 3602315SN/A 3612350SN/A/** 3622350SN/A * Templated Checker class. This Checker class is templated on the 3632350SN/A * DynInstPtr of the instruction type that will be verified. Proper 3642350SN/A * template instantiations of the Checker must be placed at the bottom 3652350SN/A * of checker/cpu.cc. 3662350SN/A */ 3672315SN/Atemplate <class DynInstPtr> 3682315SN/Aclass Checker : public CheckerCPU 3692315SN/A{ 3702315SN/A public: 3712315SN/A Checker(Params *p) 3722315SN/A : CheckerCPU(p) 3732315SN/A { } 3742315SN/A 3752315SN/A void switchOut(Sampler *s); 3762315SN/A void takeOverFrom(BaseCPU *oldCPU); 3772315SN/A 3782315SN/A void tick(DynInstPtr &inst); 3792315SN/A 3802315SN/A void validateInst(DynInstPtr &inst); 3812315SN/A void validateExecution(DynInstPtr &inst); 3822315SN/A void validateState(); 3832315SN/A 3842315SN/A std::list<DynInstPtr> instList; 3852315SN/A typedef typename std::list<DynInstPtr>::iterator InstListIt; 3862315SN/A void dumpInsts(); 3872315SN/A}; 3882315SN/A 3892315SN/A#endif // __CPU_CHECKER_CPU_HH__ 390