cpu.hh revision 2354
11060SN/A/* 22702Sktlim@umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 31060SN/A * All rights reserved. 41060SN/A * 51060SN/A * Redistribution and use in source and binary forms, with or without 61060SN/A * modification, are permitted provided that the following conditions are 71060SN/A * met: redistributions of source code must retain the above copyright 81060SN/A * notice, this list of conditions and the following disclaimer; 91060SN/A * redistributions in binary form must reproduce the above copyright 101060SN/A * notice, this list of conditions and the following disclaimer in the 111060SN/A * documentation and/or other materials provided with the distribution; 121060SN/A * neither the name of the copyright holders nor the names of its 131060SN/A * contributors may be used to endorse or promote products derived from 141060SN/A * this software without specific prior written permission. 151060SN/A * 161060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 291060SN/A#ifndef __CPU_CHECKER_CPU_HH__ 301060SN/A#define __CPU_CHECKER_CPU_HH__ 311464SN/A 321464SN/A#include <list> 331060SN/A#include <queue> 342731Sktlim@umich.edu#include <map> 352292SN/A 361464SN/A#include "base/statistics.hh" 371060SN/A#include "config/full_system.hh" 382669Sktlim@umich.edu#include "cpu/base.hh" 391060SN/A#include "cpu/base_dyn_inst.hh" 401060SN/A#include "cpu/cpu_exec_context.hh" 411858SN/A#include "cpu/pc_event.hh" 423770Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 431464SN/A#include "sim/eventq.hh" 441464SN/A 452669Sktlim@umich.edu// forward declarations 461060SN/A#if FULL_SYSTEM 472669Sktlim@umich.educlass Processor; 482292SN/Aclass AlphaITB; 491060SN/Aclass AlphaDTB; 501060SN/Aclass PhysicalMemory; 511060SN/A 521060SN/Aclass RemoteGDB; 531060SN/Aclass GDBListener; 541060SN/A 551061SN/A#else 561061SN/A 571060SN/Aclass Process; 581060SN/A 591061SN/A#endif // FULL_SYSTEM 601060SN/Atemplate <class> 611060SN/Aclass BaseDynInst; 621060SN/Aclass ExecContext; 632733Sktlim@umich.educlass MemInterface; 642733Sktlim@umich.educlass Checkpoint; 651060SN/Aclass Sampler; 662292SN/A 672107SN/A/** 682690Sktlim@umich.edu * CheckerCPU class. Dynamically verifies instructions as they are 692107SN/A * completed by making sure that the instruction and its results match 702690Sktlim@umich.edu * the independent execution of the benchmark inside the checker. The 712690Sktlim@umich.edu * checker verifies instructions in order, regardless of the order in 721060SN/A * which instructions complete. There are certain results that can 732292SN/A * not be verified, specifically the result of a store conditional or 742292SN/A * the values of uncached accesses. In these cases, and with 752292SN/A * instructions marked as "IsUnverifiable", the checker assumes that 762292SN/A * the value from the main CPU's execution is correct and simply 772292SN/A * copies that value. It provides a CheckerExecContext (see 782292SN/A * checker/exec_context.hh) that provides hooks for updating the 791060SN/A * Checker's state through any ExecContext accesses. This allows the 802292SN/A * checker to be able to correctly verify instructions, even with 812292SN/A * external accesses to the ExecContext that change state. 821060SN/A */ 831060SN/Aclass CheckerCPU : public BaseCPU 842292SN/A{ 852107SN/A protected: 861060SN/A typedef TheISA::MachInst MachInst; 871060SN/A typedef TheISA::MiscReg MiscReg; 881060SN/A public: 891060SN/A virtual void init(); 901060SN/A 911060SN/A struct Params : public BaseCPU::Params 922292SN/A { 931060SN/A#if FULL_SYSTEM 941060SN/A AlphaITB *itb; 952292SN/A AlphaDTB *dtb; 962292SN/A FunctionalMemory *mem; 972292SN/A#else 982292SN/A Process *process; 992292SN/A#endif 1002292SN/A bool exitOnError; 1012292SN/A bool updateOnError; 1021060SN/A }; 1032132SN/A 1041060SN/A public: 1052292SN/A CheckerCPU(Params *p); 1062292SN/A virtual ~CheckerCPU(); 1072292SN/A 1082292SN/A void setMemory(FunctionalMemory *mem); 1092292SN/A 1102292SN/A FunctionalMemory *memPtr; 1112292SN/A 1122292SN/A#if FULL_SYSTEM 1131060SN/A void setSystem(System *system); 1142132SN/A 1151060SN/A System *systemPtr; 1161060SN/A#endif 1171060SN/A public: 1181060SN/A // execution context 1192132SN/A CPUExecContext *cpuXC; 1202132SN/A 1211060SN/A ExecContext *xcProxy; 1221684SN/A 1231060SN/A AlphaITB *itb; 1241060SN/A AlphaDTB *dtb; 1251060SN/A 1261060SN/A#if FULL_SYSTEM 1272731Sktlim@umich.edu Addr dbg_vtophys(Addr addr); 1282731Sktlim@umich.edu#endif 1292731Sktlim@umich.edu 1302731Sktlim@umich.edu union Result { 1312731Sktlim@umich.edu uint64_t integer; 1322731Sktlim@umich.edu float fp; 1332731Sktlim@umich.edu double dbl; 1342731Sktlim@umich.edu }; 1352731Sktlim@umich.edu 1362731Sktlim@umich.edu Result result; 1372731Sktlim@umich.edu 1382731Sktlim@umich.edu // current instruction 1392731Sktlim@umich.edu MachInst machInst; 1402731Sktlim@umich.edu 1412731Sktlim@umich.edu // Refcounted pointer to the one memory request. 1422731Sktlim@umich.edu MemReqPtr memReq; 1432731Sktlim@umich.edu 1442731Sktlim@umich.edu StaticInstPtr curStaticInst; 1452731Sktlim@umich.edu 1462731Sktlim@umich.edu // number of simulated instructions 1472731Sktlim@umich.edu Counter numInst; 1482731Sktlim@umich.edu Counter startNumInst; 1492731Sktlim@umich.edu 1502731Sktlim@umich.edu std::queue<int> miscRegIdxs; 1512731Sktlim@umich.edu 1522292SN/A virtual Counter totalInstructions() const 1532731Sktlim@umich.edu { 1542731Sktlim@umich.edu return numInst - startNumInst; 1551060SN/A } 1561060SN/A 1571060SN/A // number of simulated loads 1581060SN/A Counter numLoad; 1591060SN/A Counter startNumLoad; 1601060SN/A 1611060SN/A virtual void serialize(std::ostream &os); 1622292SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1632292SN/A 1642292SN/A template <class T> 1652733Sktlim@umich.edu Fault read(Addr addr, T &data, unsigned flags); 1662733Sktlim@umich.edu 1671060SN/A template <class T> 1682680Sktlim@umich.edu Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1692292SN/A 1701060SN/A // These functions are only used in CPU models that split 1711060SN/A // effective address computation from the actual memory access. 1722132SN/A void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } 1731060SN/A Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); } 1742702Sktlim@umich.edu 1752669Sktlim@umich.edu void prefetch(Addr addr, unsigned flags) 1762292SN/A { 1771060SN/A // need to do this... 1781060SN/A } 1791060SN/A 1804032Sktlim@umich.edu void writeHint(Addr addr, int size, unsigned flags) 1814032Sktlim@umich.edu { 1824032Sktlim@umich.edu // need to do this... 1831060SN/A } 1841060SN/A 1851060SN/A Fault copySrcTranslate(Addr src); 1861060SN/A 1871060SN/A Fault copy(Addr dest); 1881060SN/A 1891060SN/A // The register accessor methods provide the index of the 1901060SN/A // instruction's operand (e.g., 0 or 1), not the architectural 1911060SN/A // register index, to simplify the implementation of register 1921060SN/A // renaming. We find the architectural register index by indexing 1931060SN/A // into the instruction's own operand index table. Note that a 1941060SN/A // raw pointer to the StaticInst is provided instead of a 1951464SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 1961464SN/A // long as these methods don't copy the pointer into any long-term 1972356SN/A // storage (which is pretty hard to imagine they would have reason 1981464SN/A // to do). 1991464SN/A 2001060SN/A uint64_t readIntReg(const StaticInst *si, int idx) 2011464SN/A { 2021464SN/A return cpuXC->readIntReg(si->srcRegIdx(idx)); 2031464SN/A } 2041464SN/A 2051060SN/A float readFloatRegSingle(const StaticInst *si, int idx) 2063326Sktlim@umich.edu { 2073326Sktlim@umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2083326Sktlim@umich.edu return cpuXC->readFloatRegSingle(reg_idx); 2091060SN/A } 2101060SN/A 2111060SN/A double readFloatRegDouble(const StaticInst *si, int idx) 2123965Sgblack@eecs.umich.edu { 2131060SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2141060SN/A return cpuXC->readFloatRegDouble(reg_idx); 2151060SN/A } 2161060SN/A 2171060SN/A uint64_t readFloatRegInt(const StaticInst *si, int idx) 2181060SN/A { 2192935Sksewell@umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2202935Sksewell@umich.edu return cpuXC->readFloatRegInt(reg_idx); 2212935Sksewell@umich.edu } 2221060SN/A 2231060SN/A void setIntReg(const StaticInst *si, int idx, uint64_t val) 2241060SN/A { 2253794Sgblack@eecs.umich.edu cpuXC->setIntReg(si->destRegIdx(idx), val); 2263794Sgblack@eecs.umich.edu result.integer = val; 2273794Sgblack@eecs.umich.edu } 2283794Sgblack@eecs.umich.edu 2293794Sgblack@eecs.umich.edu void setFloatRegSingle(const StaticInst *si, int idx, float val) 2303794Sgblack@eecs.umich.edu { 2313965Sgblack@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2323965Sgblack@eecs.umich.edu cpuXC->setFloatRegSingle(reg_idx, val); 2331060SN/A result.fp = val; 2341060SN/A } 2351060SN/A 2362292SN/A void setFloatRegDouble(const StaticInst *si, int idx, double val) 2372292SN/A { 2382292SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2392292SN/A cpuXC->setFloatRegDouble(reg_idx, val); 2402292SN/A result.dbl = val; 2412292SN/A } 2421060SN/A 2431060SN/A void setFloatRegInt(const StaticInst *si, int idx, uint64_t val) 2441060SN/A { 2453770Sgblack@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2463770Sgblack@eecs.umich.edu cpuXC->setFloatRegInt(reg_idx, val); 2473770Sgblack@eecs.umich.edu result.integer = val; 2483770Sgblack@eecs.umich.edu } 2493770Sgblack@eecs.umich.edu 2503770Sgblack@eecs.umich.edu uint64_t readPC() { return cpuXC->readPC(); } 2513770Sgblack@eecs.umich.edu void setNextPC(uint64_t val) { 2523770Sgblack@eecs.umich.edu cpuXC->setNextPC(val); 2533770Sgblack@eecs.umich.edu } 2543770Sgblack@eecs.umich.edu 2553770Sgblack@eecs.umich.edu MiscReg readMiscReg(int misc_reg) 2563770Sgblack@eecs.umich.edu { 2573770Sgblack@eecs.umich.edu return cpuXC->readMiscReg(misc_reg); 2583770Sgblack@eecs.umich.edu } 2593770Sgblack@eecs.umich.edu 2603770Sgblack@eecs.umich.edu MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 2613770Sgblack@eecs.umich.edu { 2623770Sgblack@eecs.umich.edu return cpuXC->readMiscRegWithEffect(misc_reg, fault); 2633770Sgblack@eecs.umich.edu } 2643770Sgblack@eecs.umich.edu 2653770Sgblack@eecs.umich.edu Fault setMiscReg(int misc_reg, const MiscReg &val) 2663770Sgblack@eecs.umich.edu { 2673770Sgblack@eecs.umich.edu result.integer = val; 2683770Sgblack@eecs.umich.edu miscRegIdxs.push(misc_reg); 2693770Sgblack@eecs.umich.edu return cpuXC->setMiscReg(misc_reg, val); 2703770Sgblack@eecs.umich.edu } 2711060SN/A 2723770Sgblack@eecs.umich.edu Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 2733770Sgblack@eecs.umich.edu { 2743770Sgblack@eecs.umich.edu miscRegIdxs.push(misc_reg); 2753770Sgblack@eecs.umich.edu return cpuXC->setMiscRegWithEffect(misc_reg, val); 2763770Sgblack@eecs.umich.edu } 2773770Sgblack@eecs.umich.edu 2783770Sgblack@eecs.umich.edu void recordPCChange(uint64_t val) { changedPC = true; } 2793770Sgblack@eecs.umich.edu void recordNextPCChange(uint64_t val) { changedNextPC = true; } 2803770Sgblack@eecs.umich.edu 2813770Sgblack@eecs.umich.edu bool translateInstReq(MemReqPtr &req); 2823770Sgblack@eecs.umich.edu void translateDataWriteReq(MemReqPtr &req); 2833770Sgblack@eecs.umich.edu void translateDataReadReq(MemReqPtr &req); 2843770Sgblack@eecs.umich.edu 2853770Sgblack@eecs.umich.edu#if FULL_SYSTEM 2863770Sgblack@eecs.umich.edu Fault hwrei() { return cpuXC->hwrei(); } 2873770Sgblack@eecs.umich.edu int readIntrFlag() { return cpuXC->readIntrFlag(); } 2883770Sgblack@eecs.umich.edu void setIntrFlag(int val) { cpuXC->setIntrFlag(val); } 2893770Sgblack@eecs.umich.edu bool inPalMode() { return cpuXC->inPalMode(); } 2903770Sgblack@eecs.umich.edu void ev5_trap(Fault fault) { fault->invoke(xcProxy); } 2913770Sgblack@eecs.umich.edu bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); } 2923770Sgblack@eecs.umich.edu#else 2933770Sgblack@eecs.umich.edu // Assume that the normal CPU's call to syscall was successful. 2943770Sgblack@eecs.umich.edu // The checker's state would have already been updated by the syscall. 2953770Sgblack@eecs.umich.edu void syscall() { } 2963770Sgblack@eecs.umich.edu#endif 2973770Sgblack@eecs.umich.edu 2983770Sgblack@eecs.umich.edu virtual void handleError() = 0; 2993770Sgblack@eecs.umich.edu 3003770Sgblack@eecs.umich.edu bool checkFlags(MemReqPtr &req); 3013770Sgblack@eecs.umich.edu 3023770Sgblack@eecs.umich.edu ExecContext *xcBase() { return xcProxy; } 3033770Sgblack@eecs.umich.edu CPUExecContext *cpuXCBase() { return cpuXC; } 3043770Sgblack@eecs.umich.edu 3053770Sgblack@eecs.umich.edu Result unverifiedResult; 3063770Sgblack@eecs.umich.edu MemReqPtr unverifiedReq; 3073770Sgblack@eecs.umich.edu 3083770Sgblack@eecs.umich.edu bool changedPC; 3093770Sgblack@eecs.umich.edu bool willChangePC; 3103770Sgblack@eecs.umich.edu uint64_t newPC; 3113770Sgblack@eecs.umich.edu bool changedNextPC; 3123770Sgblack@eecs.umich.edu bool exitOnError; 3133770Sgblack@eecs.umich.edu bool updateOnError; 3143770Sgblack@eecs.umich.edu 3153770Sgblack@eecs.umich.edu InstSeqNum youngestSN; 3163770Sgblack@eecs.umich.edu}; 3173770Sgblack@eecs.umich.edu 3183770Sgblack@eecs.umich.edu/** 3193770Sgblack@eecs.umich.edu * Templated Checker class. This Checker class is templated on the 3203770Sgblack@eecs.umich.edu * DynInstPtr of the instruction type that will be verified. Proper 3213770Sgblack@eecs.umich.edu * template instantiations of the Checker must be placed at the bottom 3223770Sgblack@eecs.umich.edu * of checker/cpu.cc. 3233770Sgblack@eecs.umich.edu */ 3243770Sgblack@eecs.umich.edutemplate <class DynInstPtr> 3253770Sgblack@eecs.umich.educlass Checker : public CheckerCPU 3263770Sgblack@eecs.umich.edu{ 3273770Sgblack@eecs.umich.edu public: 3283770Sgblack@eecs.umich.edu Checker(Params *p) 3293770Sgblack@eecs.umich.edu : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL) 3303770Sgblack@eecs.umich.edu { } 3313770Sgblack@eecs.umich.edu 3323770Sgblack@eecs.umich.edu void switchOut(Sampler *s); 3333770Sgblack@eecs.umich.edu void takeOverFrom(BaseCPU *oldCPU); 3343770Sgblack@eecs.umich.edu 3353770Sgblack@eecs.umich.edu void tick(DynInstPtr &inst); 3363770Sgblack@eecs.umich.edu 3373770Sgblack@eecs.umich.edu void validateInst(DynInstPtr &inst); 3383770Sgblack@eecs.umich.edu void validateExecution(DynInstPtr &inst); 3393770Sgblack@eecs.umich.edu void validateState(); 3403770Sgblack@eecs.umich.edu 3413770Sgblack@eecs.umich.edu virtual void handleError() 3423770Sgblack@eecs.umich.edu { 3433770Sgblack@eecs.umich.edu if (exitOnError) 3442292SN/A panic("Checker found error!"); 3452292SN/A else if (updateOnError) 3462292SN/A updateThisCycle = true; 3472292SN/A } 3483794Sgblack@eecs.umich.edu 3492292SN/A bool updateThisCycle; 3502292SN/A 3512292SN/A DynInstPtr unverifiedInst; 3523801Sgblack@eecs.umich.edu 3533794Sgblack@eecs.umich.edu std::list<DynInstPtr> instList; 3543770Sgblack@eecs.umich.edu typedef typename std::list<DynInstPtr>::iterator InstListIt; 3551060SN/A void dumpInsts(); 3562292SN/A}; 3572292SN/A 3582292SN/A#endif // __CPU_CHECKER_CPU_HH__ 3592107SN/A