cpu.hh revision 13611
12315SN/A/* 213610Sgiacomo.gabrielli@arm.com * Copyright (c) 2011, 2016-2017 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152332SN/A * Copyright (c) 2006 The Regents of The University of Michigan 162315SN/A * All rights reserved. 172315SN/A * 182315SN/A * Redistribution and use in source and binary forms, with or without 192315SN/A * modification, are permitted provided that the following conditions are 202315SN/A * met: redistributions of source code must retain the above copyright 212315SN/A * notice, this list of conditions and the following disclaimer; 222315SN/A * redistributions in binary form must reproduce the above copyright 232315SN/A * notice, this list of conditions and the following disclaimer in the 242315SN/A * documentation and/or other materials provided with the distribution; 252315SN/A * neither the name of the copyright holders nor the names of its 262315SN/A * contributors may be used to endorse or promote products derived from 272315SN/A * this software without specific prior written permission. 282315SN/A * 292315SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302315SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312315SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322315SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332315SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342315SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362315SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372315SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382315SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392315SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Kevin Lim 422315SN/A */ 432315SN/A 442315SN/A#ifndef __CPU_CHECKER_CPU_HH__ 452315SN/A#define __CPU_CHECKER_CPU_HH__ 462315SN/A 472315SN/A#include <list> 488229Snate@binkert.org#include <map> 492315SN/A#include <queue> 502315SN/A 512669Sktlim@umich.edu#include "arch/types.hh" 522315SN/A#include "base/statistics.hh" 532315SN/A#include "cpu/base.hh" 542315SN/A#include "cpu/base_dyn_inst.hh" 5510319SAndreas.Sandberg@ARM.com#include "cpu/exec_context.hh" 5612107SRekai.GonzalezAlberquilla@arm.com#include "cpu/inst_res.hh" 578229Snate@binkert.org#include "cpu/pc_event.hh" 582683Sktlim@umich.edu#include "cpu/simple_thread.hh" 592315SN/A#include "cpu/static_inst.hh" 608733Sgeoffrey.blake@arm.com#include "debug/Checker.hh" 6111608Snikos.nikoleris@arm.com#include "mem/request.hh" 628733Sgeoffrey.blake@arm.com#include "params/CheckerCPU.hh" 632315SN/A#include "sim/eventq.hh" 642315SN/A 6512406Sgabeblack@google.comclass BaseTLB; 662315SN/Atemplate <class> 672315SN/Aclass BaseDynInst; 682680Sktlim@umich.educlass ThreadContext; 692669Sktlim@umich.educlass Request; 702315SN/A 712350SN/A/** 722350SN/A * CheckerCPU class. Dynamically verifies instructions as they are 732350SN/A * completed by making sure that the instruction and its results match 742350SN/A * the independent execution of the benchmark inside the checker. The 752350SN/A * checker verifies instructions in order, regardless of the order in 762350SN/A * which instructions complete. There are certain results that can 772350SN/A * not be verified, specifically the result of a store conditional or 782350SN/A * the values of uncached accesses. In these cases, and with 792350SN/A * instructions marked as "IsUnverifiable", the checker assumes that 802350SN/A * the value from the main CPU's execution is correct and simply 812680Sktlim@umich.edu * copies that value. It provides a CheckerThreadContext (see 822683Sktlim@umich.edu * checker/thread_context.hh) that provides hooks for updating the 832680Sktlim@umich.edu * Checker's state through any ThreadContext accesses. This allows the 842350SN/A * checker to be able to correctly verify instructions, even with 852680Sktlim@umich.edu * external accesses to the ThreadContext that change state. 862350SN/A */ 8710319SAndreas.Sandberg@ARM.comclass CheckerCPU : public BaseCPU, public ExecContext 882315SN/A{ 892315SN/A protected: 902315SN/A typedef TheISA::MachInst MachInst; 9112109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 928832SAli.Saidi@ARM.com 938832SAli.Saidi@ARM.com /** id attached to all issued requests */ 948832SAli.Saidi@ARM.com MasterID masterId; 952315SN/A public: 9611169Sandreas.hansson@arm.com void init() override; 972315SN/A 985529Snate@binkert.org typedef CheckerCPUParams Params; 992315SN/A CheckerCPU(Params *p); 1002315SN/A virtual ~CheckerCPU(); 1012315SN/A 1022315SN/A void setSystem(System *system); 1032315SN/A 1049608Sandreas.hansson@arm.com void setIcachePort(MasterPort *icache_port); 1052679Sktlim@umich.edu 1069608Sandreas.hansson@arm.com void setDcachePort(MasterPort *dcache_port); 1072679Sktlim@umich.edu 10811169Sandreas.hansson@arm.com MasterPort &getDataPort() override 1098887Sgeoffrey.blake@arm.com { 1109176Sandreas.hansson@arm.com // the checker does not have ports on its own so return the 1119176Sandreas.hansson@arm.com // data port of the actual CPU core 1129176Sandreas.hansson@arm.com assert(dcachePort); 1138887Sgeoffrey.blake@arm.com return *dcachePort; 1148887Sgeoffrey.blake@arm.com } 1158887Sgeoffrey.blake@arm.com 11611169Sandreas.hansson@arm.com MasterPort &getInstPort() override 1178887Sgeoffrey.blake@arm.com { 1189176Sandreas.hansson@arm.com // the checker does not have ports on its own so return the 1199176Sandreas.hansson@arm.com // data port of the actual CPU core 1209176Sandreas.hansson@arm.com assert(icachePort); 1218887Sgeoffrey.blake@arm.com return *icachePort; 1228887Sgeoffrey.blake@arm.com } 1232679Sktlim@umich.edu 1249176Sandreas.hansson@arm.com protected: 1259176Sandreas.hansson@arm.com 1269176Sandreas.hansson@arm.com std::vector<Process*> workload; 1279176Sandreas.hansson@arm.com 1289176Sandreas.hansson@arm.com System *systemPtr; 1299176Sandreas.hansson@arm.com 1309608Sandreas.hansson@arm.com MasterPort *icachePort; 1319608Sandreas.hansson@arm.com MasterPort *dcachePort; 1322315SN/A 1332680Sktlim@umich.edu ThreadContext *tc; 1342315SN/A 13512406Sgabeblack@google.com BaseTLB *itb; 13612406Sgabeblack@google.com BaseTLB *dtb; 1372315SN/A 1382315SN/A Addr dbg_vtophys(Addr addr); 1392315SN/A 1408733Sgeoffrey.blake@arm.com // ISAs like ARM can have multiple destination registers to check, 1418733Sgeoffrey.blake@arm.com // keep them all in a std::queue 14212107SRekai.GonzalezAlberquilla@arm.com std::queue<InstResult> result; 1432315SN/A 1442315SN/A StaticInstPtr curStaticInst; 1458733Sgeoffrey.blake@arm.com StaticInstPtr curMacroStaticInst; 1462315SN/A 1472315SN/A // number of simulated instructions 1482315SN/A Counter numInst; 1492315SN/A Counter startNumInst; 1502315SN/A 1512315SN/A std::queue<int> miscRegIdxs; 1522315SN/A 1539176Sandreas.hansson@arm.com public: 1549176Sandreas.hansson@arm.com 1559176Sandreas.hansson@arm.com // Primary thread being run. 1569176Sandreas.hansson@arm.com SimpleThread *thread; 1579176Sandreas.hansson@arm.com 15812406Sgabeblack@google.com BaseTLB* getITBPtr() { return itb; } 15912406Sgabeblack@google.com BaseTLB* getDTBPtr() { return dtb; } 1608733Sgeoffrey.blake@arm.com 16111169Sandreas.hansson@arm.com virtual Counter totalInsts() const override 1628887Sgeoffrey.blake@arm.com { 1638887Sgeoffrey.blake@arm.com return 0; 1648887Sgeoffrey.blake@arm.com } 1658887Sgeoffrey.blake@arm.com 16611169Sandreas.hansson@arm.com virtual Counter totalOps() const override 1672315SN/A { 1682930Sktlim@umich.edu return 0; 1692315SN/A } 1702315SN/A 1712315SN/A // number of simulated loads 1722315SN/A Counter numLoad; 1732315SN/A Counter startNumLoad; 1742315SN/A 17511168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 17611168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 1772315SN/A 1782315SN/A // The register accessor methods provide the index of the 1792315SN/A // instruction's operand (e.g., 0 or 1), not the architectural 1802315SN/A // register index, to simplify the implementation of register 1812315SN/A // renaming. We find the architectural register index by indexing 1822315SN/A // into the instruction's own operand index table. Note that a 1832315SN/A // raw pointer to the StaticInst is provided instead of a 1842315SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 1852315SN/A // long as these methods don't copy the pointer into any long-term 1862315SN/A // storage (which is pretty hard to imagine they would have reason 1872315SN/A // to do). 1882315SN/A 18913557Sgabeblack@google.com RegVal 19013557Sgabeblack@google.com readIntRegOperand(const StaticInst *si, int idx) override 1912315SN/A { 19212106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 19312106SRekai.GonzalezAlberquilla@arm.com assert(reg.isIntReg()); 19412106SRekai.GonzalezAlberquilla@arm.com return thread->readIntReg(reg.index()); 1952315SN/A } 1962315SN/A 19713557Sgabeblack@google.com RegVal 19813557Sgabeblack@google.com readFloatRegOperandBits(const StaticInst *si, int idx) override 1992669Sktlim@umich.edu { 20012106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 20112106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 20213611Sgabeblack@google.com return thread->readFloatReg(reg.index()); 2032315SN/A } 2042315SN/A 20512109SRekai.GonzalezAlberquilla@arm.com /** 20612109SRekai.GonzalezAlberquilla@arm.com * Read source vector register operand. 20712109SRekai.GonzalezAlberquilla@arm.com */ 20813557Sgabeblack@google.com const VecRegContainer & 20913557Sgabeblack@google.com readVecRegOperand(const StaticInst *si, int idx) const override 21012109SRekai.GonzalezAlberquilla@arm.com { 21112109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 21212109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 21312109SRekai.GonzalezAlberquilla@arm.com return thread->readVecReg(reg); 21412109SRekai.GonzalezAlberquilla@arm.com } 21512109SRekai.GonzalezAlberquilla@arm.com 21612109SRekai.GonzalezAlberquilla@arm.com /** 21712109SRekai.GonzalezAlberquilla@arm.com * Read destination vector register operand for modification. 21812109SRekai.GonzalezAlberquilla@arm.com */ 21913557Sgabeblack@google.com VecRegContainer & 22013557Sgabeblack@google.com getWritableVecRegOperand(const StaticInst *si, int idx) override 22112109SRekai.GonzalezAlberquilla@arm.com { 22212109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 22312109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 22412109SRekai.GonzalezAlberquilla@arm.com return thread->getWritableVecReg(reg); 22512109SRekai.GonzalezAlberquilla@arm.com } 22612109SRekai.GonzalezAlberquilla@arm.com 22712109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 22812109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 22912109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 23012109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane8 23113557Sgabeblack@google.com readVec8BitLaneOperand(const StaticInst *si, int idx) const override 23212109SRekai.GonzalezAlberquilla@arm.com { 23312109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 23412109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 23512109SRekai.GonzalezAlberquilla@arm.com return thread->readVec8BitLaneReg(reg); 23612109SRekai.GonzalezAlberquilla@arm.com } 23712109SRekai.GonzalezAlberquilla@arm.com 23812109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 23912109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane16 24013557Sgabeblack@google.com readVec16BitLaneOperand(const StaticInst *si, int idx) const override 24112109SRekai.GonzalezAlberquilla@arm.com { 24212109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 24312109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 24412109SRekai.GonzalezAlberquilla@arm.com return thread->readVec16BitLaneReg(reg); 24512109SRekai.GonzalezAlberquilla@arm.com } 24612109SRekai.GonzalezAlberquilla@arm.com 24712109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 24812109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane32 24913557Sgabeblack@google.com readVec32BitLaneOperand(const StaticInst *si, int idx) const override 25012109SRekai.GonzalezAlberquilla@arm.com { 25112109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 25212109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 25312109SRekai.GonzalezAlberquilla@arm.com return thread->readVec32BitLaneReg(reg); 25412109SRekai.GonzalezAlberquilla@arm.com } 25512109SRekai.GonzalezAlberquilla@arm.com 25612109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 25712109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane64 25813557Sgabeblack@google.com readVec64BitLaneOperand(const StaticInst *si, int idx) const override 25912109SRekai.GonzalezAlberquilla@arm.com { 26012109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 26112109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 26212109SRekai.GonzalezAlberquilla@arm.com return thread->readVec64BitLaneReg(reg); 26312109SRekai.GonzalezAlberquilla@arm.com } 26412109SRekai.GonzalezAlberquilla@arm.com 26512109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector operand. */ 26612109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 26712109SRekai.GonzalezAlberquilla@arm.com void 26812109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(const StaticInst *si, int idx, const LD& val) 26912109SRekai.GonzalezAlberquilla@arm.com { 27012109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 27112109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 27212109SRekai.GonzalezAlberquilla@arm.com return thread->setVecLane(reg, val); 27312109SRekai.GonzalezAlberquilla@arm.com } 27412109SRekai.GonzalezAlberquilla@arm.com virtual void 27512109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 27612109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) override 27712109SRekai.GonzalezAlberquilla@arm.com { 27812109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(si, idx, val); 27912109SRekai.GonzalezAlberquilla@arm.com } 28012109SRekai.GonzalezAlberquilla@arm.com virtual void 28112109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 28212109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) override 28312109SRekai.GonzalezAlberquilla@arm.com { 28412109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(si, idx, val); 28512109SRekai.GonzalezAlberquilla@arm.com } 28612109SRekai.GonzalezAlberquilla@arm.com virtual void 28712109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 28812109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) override 28912109SRekai.GonzalezAlberquilla@arm.com { 29012109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(si, idx, val); 29112109SRekai.GonzalezAlberquilla@arm.com } 29212109SRekai.GonzalezAlberquilla@arm.com virtual void 29312109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 29412109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) override 29512109SRekai.GonzalezAlberquilla@arm.com { 29612109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(si, idx, val); 29712109SRekai.GonzalezAlberquilla@arm.com } 29812109SRekai.GonzalezAlberquilla@arm.com /** @} */ 29912109SRekai.GonzalezAlberquilla@arm.com 30013557Sgabeblack@google.com VecElem 30113557Sgabeblack@google.com readVecElemOperand(const StaticInst *si, int idx) const override 30212109SRekai.GonzalezAlberquilla@arm.com { 30312109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 30412109SRekai.GonzalezAlberquilla@arm.com return thread->readVecElem(reg); 30512109SRekai.GonzalezAlberquilla@arm.com } 30612109SRekai.GonzalezAlberquilla@arm.com 30713610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& 30813610Sgiacomo.gabrielli@arm.com readVecPredRegOperand(const StaticInst *si, int idx) const override 30913610Sgiacomo.gabrielli@arm.com { 31013610Sgiacomo.gabrielli@arm.com const RegId& reg = si->srcRegIdx(idx); 31113610Sgiacomo.gabrielli@arm.com assert(reg.isVecPredReg()); 31213610Sgiacomo.gabrielli@arm.com return thread->readVecPredReg(reg); 31313610Sgiacomo.gabrielli@arm.com } 31413610Sgiacomo.gabrielli@arm.com 31513610Sgiacomo.gabrielli@arm.com VecPredRegContainer& 31613610Sgiacomo.gabrielli@arm.com getWritableVecPredRegOperand(const StaticInst *si, int idx) override 31713610Sgiacomo.gabrielli@arm.com { 31813610Sgiacomo.gabrielli@arm.com const RegId& reg = si->destRegIdx(idx); 31913610Sgiacomo.gabrielli@arm.com assert(reg.isVecPredReg()); 32013610Sgiacomo.gabrielli@arm.com return thread->getWritableVecPredReg(reg); 32113610Sgiacomo.gabrielli@arm.com } 32213610Sgiacomo.gabrielli@arm.com 32313557Sgabeblack@google.com CCReg 32413557Sgabeblack@google.com readCCRegOperand(const StaticInst *si, int idx) override 3259920Syasuko.eckert@amd.com { 32612106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 32712106SRekai.GonzalezAlberquilla@arm.com assert(reg.isCCReg()); 32812106SRekai.GonzalezAlberquilla@arm.com return thread->readCCReg(reg.index()); 3299920Syasuko.eckert@amd.com } 3309920Syasuko.eckert@amd.com 33112107SRekai.GonzalezAlberquilla@arm.com template<typename T> 33213557Sgabeblack@google.com void 33313557Sgabeblack@google.com setScalarResult(T&& t) 3348733Sgeoffrey.blake@arm.com { 33512107SRekai.GonzalezAlberquilla@arm.com result.push(InstResult(std::forward<T>(t), 33613557Sgabeblack@google.com InstResult::ResultType::Scalar)); 3378733Sgeoffrey.blake@arm.com } 3388733Sgeoffrey.blake@arm.com 33912109SRekai.GonzalezAlberquilla@arm.com template<typename T> 34013557Sgabeblack@google.com void 34113557Sgabeblack@google.com setVecResult(T&& t) 34212109SRekai.GonzalezAlberquilla@arm.com { 34312109SRekai.GonzalezAlberquilla@arm.com result.push(InstResult(std::forward<T>(t), 34413557Sgabeblack@google.com InstResult::ResultType::VecReg)); 34512109SRekai.GonzalezAlberquilla@arm.com } 34612109SRekai.GonzalezAlberquilla@arm.com 34712109SRekai.GonzalezAlberquilla@arm.com template<typename T> 34813557Sgabeblack@google.com void 34913557Sgabeblack@google.com setVecElemResult(T&& t) 35012109SRekai.GonzalezAlberquilla@arm.com { 35112109SRekai.GonzalezAlberquilla@arm.com result.push(InstResult(std::forward<T>(t), 35213557Sgabeblack@google.com InstResult::ResultType::VecElem)); 35312109SRekai.GonzalezAlberquilla@arm.com } 35412109SRekai.GonzalezAlberquilla@arm.com 35513610Sgiacomo.gabrielli@arm.com template<typename T> 35613610Sgiacomo.gabrielli@arm.com void 35713610Sgiacomo.gabrielli@arm.com setVecPredResult(T&& t) 35813610Sgiacomo.gabrielli@arm.com { 35913610Sgiacomo.gabrielli@arm.com result.push(InstResult(std::forward<T>(t), 36013610Sgiacomo.gabrielli@arm.com InstResult::ResultType::VecPredReg)); 36113610Sgiacomo.gabrielli@arm.com } 36213610Sgiacomo.gabrielli@arm.com 36313557Sgabeblack@google.com void 36413557Sgabeblack@google.com setIntRegOperand(const StaticInst *si, int idx, RegVal val) override 3652315SN/A { 36612106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 36712106SRekai.GonzalezAlberquilla@arm.com assert(reg.isIntReg()); 36812106SRekai.GonzalezAlberquilla@arm.com thread->setIntReg(reg.index(), val); 36912107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 3702315SN/A } 3712315SN/A 37213557Sgabeblack@google.com void 37313557Sgabeblack@google.com setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override 3742315SN/A { 37512106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 37612106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 37713611Sgabeblack@google.com thread->setFloatReg(reg.index(), val); 37812107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 3792315SN/A } 3802315SN/A 38113557Sgabeblack@google.com void 38213557Sgabeblack@google.com setCCRegOperand(const StaticInst *si, int idx, CCReg val) override 3839920Syasuko.eckert@amd.com { 38412106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 38512106SRekai.GonzalezAlberquilla@arm.com assert(reg.isCCReg()); 38612106SRekai.GonzalezAlberquilla@arm.com thread->setCCReg(reg.index(), val); 38712107SRekai.GonzalezAlberquilla@arm.com setScalarResult((uint64_t)val); 3889920Syasuko.eckert@amd.com } 3899920Syasuko.eckert@amd.com 39013557Sgabeblack@google.com void 39113557Sgabeblack@google.com setVecRegOperand(const StaticInst *si, int idx, 39213557Sgabeblack@google.com const VecRegContainer& val) override 39312109SRekai.GonzalezAlberquilla@arm.com { 39412109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 39512109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 39612109SRekai.GonzalezAlberquilla@arm.com thread->setVecReg(reg, val); 39712109SRekai.GonzalezAlberquilla@arm.com setVecResult(val); 39812109SRekai.GonzalezAlberquilla@arm.com } 39912109SRekai.GonzalezAlberquilla@arm.com 40013557Sgabeblack@google.com void 40113557Sgabeblack@google.com setVecElemOperand(const StaticInst *si, int idx, 40213557Sgabeblack@google.com const VecElem val) override 40312109SRekai.GonzalezAlberquilla@arm.com { 40412109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 40512109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecElem()); 40612109SRekai.GonzalezAlberquilla@arm.com thread->setVecElem(reg, val); 40712109SRekai.GonzalezAlberquilla@arm.com setVecElemResult(val); 40812109SRekai.GonzalezAlberquilla@arm.com } 40912109SRekai.GonzalezAlberquilla@arm.com 41013610Sgiacomo.gabrielli@arm.com void setVecPredRegOperand(const StaticInst *si, int idx, 41113610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& val) override 41213610Sgiacomo.gabrielli@arm.com { 41313610Sgiacomo.gabrielli@arm.com const RegId& reg = si->destRegIdx(idx); 41413610Sgiacomo.gabrielli@arm.com assert(reg.isVecPredReg()); 41513610Sgiacomo.gabrielli@arm.com thread->setVecPredReg(reg, val); 41613610Sgiacomo.gabrielli@arm.com setVecPredResult(val); 41713610Sgiacomo.gabrielli@arm.com } 41813610Sgiacomo.gabrielli@arm.com 41913429Srekai.gonzalezalberquilla@arm.com bool readPredicate() const override { return thread->readPredicate(); } 42013429Srekai.gonzalezalberquilla@arm.com 42113557Sgabeblack@google.com void 42213557Sgabeblack@google.com setPredicate(bool val) override 4238733Sgeoffrey.blake@arm.com { 4248733Sgeoffrey.blake@arm.com thread->setPredicate(val); 4258733Sgeoffrey.blake@arm.com } 4262669Sktlim@umich.edu 42711169Sandreas.hansson@arm.com TheISA::PCState pcState() const override { return thread->pcState(); } 42813557Sgabeblack@google.com void 42913557Sgabeblack@google.com pcState(const TheISA::PCState &val) override 4308733Sgeoffrey.blake@arm.com { 4318733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Changing PC to %s, old PC %s.\n", 4328733Sgeoffrey.blake@arm.com val, thread->pcState()); 4338733Sgeoffrey.blake@arm.com thread->pcState(val); 4348733Sgeoffrey.blake@arm.com } 4358733Sgeoffrey.blake@arm.com Addr instAddr() { return thread->instAddr(); } 4368733Sgeoffrey.blake@arm.com Addr nextInstAddr() { return thread->nextInstAddr(); } 4378733Sgeoffrey.blake@arm.com MicroPC microPC() { return thread->microPC(); } 4388733Sgeoffrey.blake@arm.com ////////////////////////////////////////// 4392315SN/A 44013557Sgabeblack@google.com RegVal 44113557Sgabeblack@google.com readMiscRegNoEffect(int misc_reg) const 4424172Ssaidi@eecs.umich.edu { 4434172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 4444172Ssaidi@eecs.umich.edu } 4454172Ssaidi@eecs.umich.edu 44613557Sgabeblack@google.com RegVal 44713557Sgabeblack@google.com readMiscReg(int misc_reg) override 4482315SN/A { 4492683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 4502315SN/A } 4512315SN/A 45213557Sgabeblack@google.com void 45313582Sgabeblack@google.com setMiscRegNoEffect(int misc_reg, RegVal val) 4542315SN/A { 45513557Sgabeblack@google.com DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n", 45613557Sgabeblack@google.com misc_reg); 4574172Ssaidi@eecs.umich.edu miscRegIdxs.push(misc_reg); 4584172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(misc_reg, val); 4592315SN/A } 4602315SN/A 46113557Sgabeblack@google.com void 46213582Sgabeblack@google.com setMiscReg(int misc_reg, RegVal val) override 4632315SN/A { 46413557Sgabeblack@google.com DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", 46513557Sgabeblack@google.com misc_reg); 4662315SN/A miscRegIdxs.push(misc_reg); 4672683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 4682315SN/A } 4692315SN/A 47013557Sgabeblack@google.com RegVal 47113557Sgabeblack@google.com readMiscRegOperand(const StaticInst *si, int idx) override 4728733Sgeoffrey.blake@arm.com { 47312106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 47412106SRekai.GonzalezAlberquilla@arm.com assert(reg.isMiscReg()); 47512106SRekai.GonzalezAlberquilla@arm.com return thread->readMiscReg(reg.index()); 4768733Sgeoffrey.blake@arm.com } 4778733Sgeoffrey.blake@arm.com 47813557Sgabeblack@google.com void 47913582Sgabeblack@google.com setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override 4808733Sgeoffrey.blake@arm.com { 48112106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 48212106SRekai.GonzalezAlberquilla@arm.com assert(reg.isMiscReg()); 48312106SRekai.GonzalezAlberquilla@arm.com return this->setMiscReg(reg.index(), val); 4848733Sgeoffrey.blake@arm.com } 4858888Sgeoffrey.blake@arm.com 4868888Sgeoffrey.blake@arm.com#if THE_ISA == MIPS_ISA 48713557Sgabeblack@google.com RegVal 48813557Sgabeblack@google.com readRegOtherThread(const RegId &misc_reg, ThreadID tid) override 4898888Sgeoffrey.blake@arm.com { 4908888Sgeoffrey.blake@arm.com panic("MIPS MT not defined for CheckerCPU.\n"); 4918888Sgeoffrey.blake@arm.com return 0; 4928888Sgeoffrey.blake@arm.com } 4938888Sgeoffrey.blake@arm.com 49413557Sgabeblack@google.com void 49513557Sgabeblack@google.com setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid) override 4968888Sgeoffrey.blake@arm.com { 4978888Sgeoffrey.blake@arm.com panic("MIPS MT not defined for CheckerCPU.\n"); 4988888Sgeoffrey.blake@arm.com } 4998888Sgeoffrey.blake@arm.com#endif 5008888Sgeoffrey.blake@arm.com 5018733Sgeoffrey.blake@arm.com ///////////////////////////////////////// 5028733Sgeoffrey.blake@arm.com 50313557Sgabeblack@google.com void 50413557Sgabeblack@google.com recordPCChange(const TheISA::PCState &val) 5058733Sgeoffrey.blake@arm.com { 5068733Sgeoffrey.blake@arm.com changedPC = true; 5078733Sgeoffrey.blake@arm.com newPCState = val; 5088733Sgeoffrey.blake@arm.com } 5092315SN/A 51013557Sgabeblack@google.com void 51113557Sgabeblack@google.com demapPage(Addr vaddr, uint64_t asn) override 5125358Sgblack@eecs.umich.edu { 5135358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 5145358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 5155358Sgblack@eecs.umich.edu } 5165358Sgblack@eecs.umich.edu 51710529Smorr@cs.wisc.edu // monitor/mwait funtions 51813557Sgabeblack@google.com void armMonitor(Addr address) override { BaseCPU::armMonitor(0, address); } 51911169Sandreas.hansson@arm.com bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); } 52011169Sandreas.hansson@arm.com void mwaitAtomic(ThreadContext *tc) override 52111148Smitch.hayenga@arm.com { return BaseCPU::mwaitAtomic(0, tc, thread->dtb); } 52211169Sandreas.hansson@arm.com AddressMonitor *getAddrMonitor() override 52311169Sandreas.hansson@arm.com { return BaseCPU::getCpuAddrMonitor(0); } 52410529Smorr@cs.wisc.edu 52513557Sgabeblack@google.com void 52613557Sgabeblack@google.com demapInstPage(Addr vaddr, uint64_t asn) 5275358Sgblack@eecs.umich.edu { 5285358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 5295358Sgblack@eecs.umich.edu } 5305358Sgblack@eecs.umich.edu 53113557Sgabeblack@google.com void 53213557Sgabeblack@google.com demapDataPage(Addr vaddr, uint64_t asn) 5335358Sgblack@eecs.umich.edu { 5345358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 5355358Sgblack@eecs.umich.edu } 5365358Sgblack@eecs.umich.edu 53711169Sandreas.hansson@arm.com Fault readMem(Addr addr, uint8_t *data, unsigned size, 53811608Snikos.nikoleris@arm.com Request::Flags flags) override; 53911608Snikos.nikoleris@arm.com Fault writeMem(uint8_t *data, unsigned size, Addr addr, 54011608Snikos.nikoleris@arm.com Request::Flags flags, uint64_t *res) override; 5418733Sgeoffrey.blake@arm.com 54213557Sgabeblack@google.com unsigned int 54313557Sgabeblack@google.com readStCondFailures() const override { 54410319SAndreas.Sandberg@ARM.com return thread->readStCondFailures(); 54510319SAndreas.Sandberg@ARM.com } 54610319SAndreas.Sandberg@ARM.com 54713557Sgabeblack@google.com void setStCondFailures(unsigned int sc_failures) override {} 5488733Sgeoffrey.blake@arm.com ///////////////////////////////////////////////////// 5498733Sgeoffrey.blake@arm.com 55011169Sandreas.hansson@arm.com Fault hwrei() override { return thread->hwrei(); } 55111169Sandreas.hansson@arm.com bool simPalCheck(int palFunc) override 55211169Sandreas.hansson@arm.com { return thread->simPalCheck(palFunc); } 55311168Sandreas.hansson@arm.com void wakeup(ThreadID tid) override { } 5542315SN/A // Assume that the normal CPU's call to syscall was successful. 5552332SN/A // The checker's state would have already been updated by the syscall. 55611877Sbrandon.potter@amd.com void syscall(int64_t callnum, Fault *fault) override { } 5572315SN/A 55813557Sgabeblack@google.com void 55913557Sgabeblack@google.com handleError() 5602315SN/A { 5612315SN/A if (exitOnError) 5622732Sktlim@umich.edu dumpAndExit(); 5632315SN/A } 5642732Sktlim@umich.edu 56512749Sgiacomo.travaglini@arm.com bool checkFlags(const RequestPtr &unverified_req, Addr vAddr, 5668733Sgeoffrey.blake@arm.com Addr pAddr, int flags); 5672315SN/A 5682732Sktlim@umich.edu void dumpAndExit(); 5692732Sktlim@umich.edu 57011169Sandreas.hansson@arm.com ThreadContext *tcBase() override { return tc; } 5712683Sktlim@umich.edu SimpleThread *threadBase() { return thread; } 5722315SN/A 57312107SRekai.GonzalezAlberquilla@arm.com InstResult unverifiedResult; 57412748Sgiacomo.travaglini@arm.com RequestPtr unverifiedReq; 5752679Sktlim@umich.edu uint8_t *unverifiedMemData; 5762315SN/A 5772315SN/A bool changedPC; 5782315SN/A bool willChangePC; 5798733Sgeoffrey.blake@arm.com TheISA::PCState newPCState; 5802315SN/A bool exitOnError; 5812354SN/A bool updateOnError; 5822732Sktlim@umich.edu bool warnOnlyOnLoadError; 5832315SN/A 5842315SN/A InstSeqNum youngestSN; 5852315SN/A}; 5862315SN/A 5872350SN/A/** 5882350SN/A * Templated Checker class. This Checker class is templated on the 5892350SN/A * DynInstPtr of the instruction type that will be verified. Proper 5902350SN/A * template instantiations of the Checker must be placed at the bottom 5912350SN/A * of checker/cpu.cc. 5922350SN/A */ 5938733Sgeoffrey.blake@arm.comtemplate <class Impl> 5942315SN/Aclass Checker : public CheckerCPU 5952315SN/A{ 5968733Sgeoffrey.blake@arm.com private: 5978733Sgeoffrey.blake@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 5988733Sgeoffrey.blake@arm.com 5992315SN/A public: 6002315SN/A Checker(Params *p) 6019023Sgblack@eecs.umich.edu : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL) 6022315SN/A { } 6032315SN/A 6042840Sktlim@umich.edu void switchOut(); 6052315SN/A void takeOverFrom(BaseCPU *oldCPU); 6062315SN/A 60710379Sandreas.hansson@arm.com void advancePC(const Fault &fault); 6088733Sgeoffrey.blake@arm.com 60913429Srekai.gonzalezalberquilla@arm.com void verify(const DynInstPtr &inst); 6102315SN/A 61113429Srekai.gonzalezalberquilla@arm.com void validateInst(const DynInstPtr &inst); 61213429Srekai.gonzalezalberquilla@arm.com void validateExecution(const DynInstPtr &inst); 6132315SN/A void validateState(); 6142315SN/A 61513429Srekai.gonzalezalberquilla@arm.com void copyResult(const DynInstPtr &inst, const InstResult& mismatch_val, 61612107SRekai.GonzalezAlberquilla@arm.com int start_idx); 6178733Sgeoffrey.blake@arm.com void handlePendingInt(); 6182732Sktlim@umich.edu 6192732Sktlim@umich.edu private: 62013429Srekai.gonzalezalberquilla@arm.com void handleError(const DynInstPtr &inst) 6212732Sktlim@umich.edu { 6222360SN/A if (exitOnError) { 6232732Sktlim@umich.edu dumpAndExit(inst); 6242360SN/A } else if (updateOnError) { 6252354SN/A updateThisCycle = true; 6262360SN/A } 6272732Sktlim@umich.edu } 6282732Sktlim@umich.edu 62913429Srekai.gonzalezalberquilla@arm.com void dumpAndExit(const DynInstPtr &inst); 6302732Sktlim@umich.edu 6312354SN/A bool updateThisCycle; 6322354SN/A 6332354SN/A DynInstPtr unverifiedInst; 6342354SN/A 6352315SN/A std::list<DynInstPtr> instList; 6362315SN/A typedef typename std::list<DynInstPtr>::iterator InstListIt; 6372315SN/A void dumpInsts(); 6382315SN/A}; 6392315SN/A 6402315SN/A#endif // __CPU_CHECKER_CPU_HH__ 641