cpu.hh revision 12749
12315SN/A/* 212107SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2011, 2016 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152332SN/A * Copyright (c) 2006 The Regents of The University of Michigan 162315SN/A * All rights reserved. 172315SN/A * 182315SN/A * Redistribution and use in source and binary forms, with or without 192315SN/A * modification, are permitted provided that the following conditions are 202315SN/A * met: redistributions of source code must retain the above copyright 212315SN/A * notice, this list of conditions and the following disclaimer; 222315SN/A * redistributions in binary form must reproduce the above copyright 232315SN/A * notice, this list of conditions and the following disclaimer in the 242315SN/A * documentation and/or other materials provided with the distribution; 252315SN/A * neither the name of the copyright holders nor the names of its 262315SN/A * contributors may be used to endorse or promote products derived from 272315SN/A * this software without specific prior written permission. 282315SN/A * 292315SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302315SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312315SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322315SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332315SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342315SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362315SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372315SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382315SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392315SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Kevin Lim 422315SN/A */ 432315SN/A 442315SN/A#ifndef __CPU_CHECKER_CPU_HH__ 452315SN/A#define __CPU_CHECKER_CPU_HH__ 462315SN/A 472315SN/A#include <list> 488229Snate@binkert.org#include <map> 492315SN/A#include <queue> 502315SN/A 512669Sktlim@umich.edu#include "arch/types.hh" 522315SN/A#include "base/statistics.hh" 532315SN/A#include "cpu/base.hh" 542315SN/A#include "cpu/base_dyn_inst.hh" 5510319SAndreas.Sandberg@ARM.com#include "cpu/exec_context.hh" 5612107SRekai.GonzalezAlberquilla@arm.com#include "cpu/inst_res.hh" 578229Snate@binkert.org#include "cpu/pc_event.hh" 582683Sktlim@umich.edu#include "cpu/simple_thread.hh" 592315SN/A#include "cpu/static_inst.hh" 608733Sgeoffrey.blake@arm.com#include "debug/Checker.hh" 6111608Snikos.nikoleris@arm.com#include "mem/request.hh" 628733Sgeoffrey.blake@arm.com#include "params/CheckerCPU.hh" 632315SN/A#include "sim/eventq.hh" 642315SN/A 6512406Sgabeblack@google.comclass BaseTLB; 662315SN/Atemplate <class> 672315SN/Aclass BaseDynInst; 682680Sktlim@umich.educlass ThreadContext; 692669Sktlim@umich.educlass Request; 702315SN/A 712350SN/A/** 722350SN/A * CheckerCPU class. Dynamically verifies instructions as they are 732350SN/A * completed by making sure that the instruction and its results match 742350SN/A * the independent execution of the benchmark inside the checker. The 752350SN/A * checker verifies instructions in order, regardless of the order in 762350SN/A * which instructions complete. There are certain results that can 772350SN/A * not be verified, specifically the result of a store conditional or 782350SN/A * the values of uncached accesses. In these cases, and with 792350SN/A * instructions marked as "IsUnverifiable", the checker assumes that 802350SN/A * the value from the main CPU's execution is correct and simply 812680Sktlim@umich.edu * copies that value. It provides a CheckerThreadContext (see 822683Sktlim@umich.edu * checker/thread_context.hh) that provides hooks for updating the 832680Sktlim@umich.edu * Checker's state through any ThreadContext accesses. This allows the 842350SN/A * checker to be able to correctly verify instructions, even with 852680Sktlim@umich.edu * external accesses to the ThreadContext that change state. 862350SN/A */ 8710319SAndreas.Sandberg@ARM.comclass CheckerCPU : public BaseCPU, public ExecContext 882315SN/A{ 892315SN/A protected: 902315SN/A typedef TheISA::MachInst MachInst; 912669Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 922669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 932315SN/A typedef TheISA::MiscReg MiscReg; 9412109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 958832SAli.Saidi@ARM.com 968832SAli.Saidi@ARM.com /** id attached to all issued requests */ 978832SAli.Saidi@ARM.com MasterID masterId; 982315SN/A public: 9911169Sandreas.hansson@arm.com void init() override; 1002315SN/A 1015529Snate@binkert.org typedef CheckerCPUParams Params; 1022315SN/A CheckerCPU(Params *p); 1032315SN/A virtual ~CheckerCPU(); 1042315SN/A 1052315SN/A void setSystem(System *system); 1062315SN/A 1079608Sandreas.hansson@arm.com void setIcachePort(MasterPort *icache_port); 1082679Sktlim@umich.edu 1099608Sandreas.hansson@arm.com void setDcachePort(MasterPort *dcache_port); 1102679Sktlim@umich.edu 11111169Sandreas.hansson@arm.com MasterPort &getDataPort() override 1128887Sgeoffrey.blake@arm.com { 1139176Sandreas.hansson@arm.com // the checker does not have ports on its own so return the 1149176Sandreas.hansson@arm.com // data port of the actual CPU core 1159176Sandreas.hansson@arm.com assert(dcachePort); 1168887Sgeoffrey.blake@arm.com return *dcachePort; 1178887Sgeoffrey.blake@arm.com } 1188887Sgeoffrey.blake@arm.com 11911169Sandreas.hansson@arm.com MasterPort &getInstPort() override 1208887Sgeoffrey.blake@arm.com { 1219176Sandreas.hansson@arm.com // the checker does not have ports on its own so return the 1229176Sandreas.hansson@arm.com // data port of the actual CPU core 1239176Sandreas.hansson@arm.com assert(icachePort); 1248887Sgeoffrey.blake@arm.com return *icachePort; 1258887Sgeoffrey.blake@arm.com } 1262679Sktlim@umich.edu 1279176Sandreas.hansson@arm.com protected: 1289176Sandreas.hansson@arm.com 1299176Sandreas.hansson@arm.com std::vector<Process*> workload; 1309176Sandreas.hansson@arm.com 1319176Sandreas.hansson@arm.com System *systemPtr; 1329176Sandreas.hansson@arm.com 1339608Sandreas.hansson@arm.com MasterPort *icachePort; 1349608Sandreas.hansson@arm.com MasterPort *dcachePort; 1352315SN/A 1362680Sktlim@umich.edu ThreadContext *tc; 1372315SN/A 13812406Sgabeblack@google.com BaseTLB *itb; 13912406Sgabeblack@google.com BaseTLB *dtb; 1402315SN/A 1412315SN/A Addr dbg_vtophys(Addr addr); 1422315SN/A 1438733Sgeoffrey.blake@arm.com // ISAs like ARM can have multiple destination registers to check, 1448733Sgeoffrey.blake@arm.com // keep them all in a std::queue 14512107SRekai.GonzalezAlberquilla@arm.com std::queue<InstResult> result; 1462315SN/A 1472315SN/A StaticInstPtr curStaticInst; 1488733Sgeoffrey.blake@arm.com StaticInstPtr curMacroStaticInst; 1492315SN/A 1502315SN/A // number of simulated instructions 1512315SN/A Counter numInst; 1522315SN/A Counter startNumInst; 1532315SN/A 1542315SN/A std::queue<int> miscRegIdxs; 1552315SN/A 1569176Sandreas.hansson@arm.com public: 1579176Sandreas.hansson@arm.com 1589176Sandreas.hansson@arm.com // Primary thread being run. 1599176Sandreas.hansson@arm.com SimpleThread *thread; 1609176Sandreas.hansson@arm.com 16112406Sgabeblack@google.com BaseTLB* getITBPtr() { return itb; } 16212406Sgabeblack@google.com BaseTLB* getDTBPtr() { return dtb; } 1638733Sgeoffrey.blake@arm.com 16411169Sandreas.hansson@arm.com virtual Counter totalInsts() const override 1658887Sgeoffrey.blake@arm.com { 1668887Sgeoffrey.blake@arm.com return 0; 1678887Sgeoffrey.blake@arm.com } 1688887Sgeoffrey.blake@arm.com 16911169Sandreas.hansson@arm.com virtual Counter totalOps() const override 1702315SN/A { 1712930Sktlim@umich.edu return 0; 1722315SN/A } 1732315SN/A 1742315SN/A // number of simulated loads 1752315SN/A Counter numLoad; 1762315SN/A Counter startNumLoad; 1772315SN/A 17811168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 17911168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 1802315SN/A 1812315SN/A // The register accessor methods provide the index of the 1822315SN/A // instruction's operand (e.g., 0 or 1), not the architectural 1832315SN/A // register index, to simplify the implementation of register 1842315SN/A // renaming. We find the architectural register index by indexing 1852315SN/A // into the instruction's own operand index table. Note that a 1862315SN/A // raw pointer to the StaticInst is provided instead of a 1872315SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 1882315SN/A // long as these methods don't copy the pointer into any long-term 1892315SN/A // storage (which is pretty hard to imagine they would have reason 1902315SN/A // to do). 1912315SN/A 19211169Sandreas.hansson@arm.com IntReg readIntRegOperand(const StaticInst *si, int idx) override 1932315SN/A { 19412106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 19512106SRekai.GonzalezAlberquilla@arm.com assert(reg.isIntReg()); 19612106SRekai.GonzalezAlberquilla@arm.com return thread->readIntReg(reg.index()); 1972315SN/A } 1982315SN/A 19911169Sandreas.hansson@arm.com FloatReg readFloatRegOperand(const StaticInst *si, int idx) override 2002315SN/A { 20112106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 20212106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 20312106SRekai.GonzalezAlberquilla@arm.com return thread->readFloatReg(reg.index()); 2042315SN/A } 2052315SN/A 20611169Sandreas.hansson@arm.com FloatRegBits readFloatRegOperandBits(const StaticInst *si, 20711169Sandreas.hansson@arm.com int idx) override 2082669Sktlim@umich.edu { 20912106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 21012106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 21112106SRekai.GonzalezAlberquilla@arm.com return thread->readFloatRegBits(reg.index()); 2122315SN/A } 2132315SN/A 21412109SRekai.GonzalezAlberquilla@arm.com /** 21512109SRekai.GonzalezAlberquilla@arm.com * Read source vector register operand. 21612109SRekai.GonzalezAlberquilla@arm.com */ 21712109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& readVecRegOperand(const StaticInst *si, 21812109SRekai.GonzalezAlberquilla@arm.com int idx) const override 21912109SRekai.GonzalezAlberquilla@arm.com { 22012109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 22112109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 22212109SRekai.GonzalezAlberquilla@arm.com return thread->readVecReg(reg); 22312109SRekai.GonzalezAlberquilla@arm.com } 22412109SRekai.GonzalezAlberquilla@arm.com 22512109SRekai.GonzalezAlberquilla@arm.com /** 22612109SRekai.GonzalezAlberquilla@arm.com * Read destination vector register operand for modification. 22712109SRekai.GonzalezAlberquilla@arm.com */ 22812109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& getWritableVecRegOperand(const StaticInst *si, 22912109SRekai.GonzalezAlberquilla@arm.com int idx) override 23012109SRekai.GonzalezAlberquilla@arm.com { 23112109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 23212109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 23312109SRekai.GonzalezAlberquilla@arm.com return thread->getWritableVecReg(reg); 23412109SRekai.GonzalezAlberquilla@arm.com } 23512109SRekai.GonzalezAlberquilla@arm.com 23612109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 23712109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 23812109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 23912109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane8 24012109SRekai.GonzalezAlberquilla@arm.com readVec8BitLaneOperand(const StaticInst *si, int idx) const 24112109SRekai.GonzalezAlberquilla@arm.com override 24212109SRekai.GonzalezAlberquilla@arm.com { 24312109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 24412109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 24512109SRekai.GonzalezAlberquilla@arm.com return thread->readVec8BitLaneReg(reg); 24612109SRekai.GonzalezAlberquilla@arm.com } 24712109SRekai.GonzalezAlberquilla@arm.com 24812109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 24912109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane16 25012109SRekai.GonzalezAlberquilla@arm.com readVec16BitLaneOperand(const StaticInst *si, int idx) const 25112109SRekai.GonzalezAlberquilla@arm.com override 25212109SRekai.GonzalezAlberquilla@arm.com { 25312109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 25412109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 25512109SRekai.GonzalezAlberquilla@arm.com return thread->readVec16BitLaneReg(reg); 25612109SRekai.GonzalezAlberquilla@arm.com } 25712109SRekai.GonzalezAlberquilla@arm.com 25812109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 25912109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane32 26012109SRekai.GonzalezAlberquilla@arm.com readVec32BitLaneOperand(const StaticInst *si, int idx) const 26112109SRekai.GonzalezAlberquilla@arm.com override 26212109SRekai.GonzalezAlberquilla@arm.com { 26312109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 26412109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 26512109SRekai.GonzalezAlberquilla@arm.com return thread->readVec32BitLaneReg(reg); 26612109SRekai.GonzalezAlberquilla@arm.com } 26712109SRekai.GonzalezAlberquilla@arm.com 26812109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 26912109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane64 27012109SRekai.GonzalezAlberquilla@arm.com readVec64BitLaneOperand(const StaticInst *si, int idx) const 27112109SRekai.GonzalezAlberquilla@arm.com override 27212109SRekai.GonzalezAlberquilla@arm.com { 27312109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 27412109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 27512109SRekai.GonzalezAlberquilla@arm.com return thread->readVec64BitLaneReg(reg); 27612109SRekai.GonzalezAlberquilla@arm.com } 27712109SRekai.GonzalezAlberquilla@arm.com 27812109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector operand. */ 27912109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 28012109SRekai.GonzalezAlberquilla@arm.com void 28112109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(const StaticInst *si, int idx, const LD& val) 28212109SRekai.GonzalezAlberquilla@arm.com { 28312109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 28412109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 28512109SRekai.GonzalezAlberquilla@arm.com return thread->setVecLane(reg, val); 28612109SRekai.GonzalezAlberquilla@arm.com } 28712109SRekai.GonzalezAlberquilla@arm.com virtual void 28812109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 28912109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) override 29012109SRekai.GonzalezAlberquilla@arm.com { 29112109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(si, idx, val); 29212109SRekai.GonzalezAlberquilla@arm.com } 29312109SRekai.GonzalezAlberquilla@arm.com virtual void 29412109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 29512109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) override 29612109SRekai.GonzalezAlberquilla@arm.com { 29712109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(si, idx, val); 29812109SRekai.GonzalezAlberquilla@arm.com } 29912109SRekai.GonzalezAlberquilla@arm.com virtual void 30012109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 30112109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) override 30212109SRekai.GonzalezAlberquilla@arm.com { 30312109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(si, idx, val); 30412109SRekai.GonzalezAlberquilla@arm.com } 30512109SRekai.GonzalezAlberquilla@arm.com virtual void 30612109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 30712109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) override 30812109SRekai.GonzalezAlberquilla@arm.com { 30912109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(si, idx, val); 31012109SRekai.GonzalezAlberquilla@arm.com } 31112109SRekai.GonzalezAlberquilla@arm.com /** @} */ 31212109SRekai.GonzalezAlberquilla@arm.com 31312109SRekai.GonzalezAlberquilla@arm.com VecElem readVecElemOperand(const StaticInst *si, int idx) const override 31412109SRekai.GonzalezAlberquilla@arm.com { 31512109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 31612109SRekai.GonzalezAlberquilla@arm.com return thread->readVecElem(reg); 31712109SRekai.GonzalezAlberquilla@arm.com } 31812109SRekai.GonzalezAlberquilla@arm.com 31911169Sandreas.hansson@arm.com CCReg readCCRegOperand(const StaticInst *si, int idx) override 3209920Syasuko.eckert@amd.com { 32112106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 32212106SRekai.GonzalezAlberquilla@arm.com assert(reg.isCCReg()); 32312106SRekai.GonzalezAlberquilla@arm.com return thread->readCCReg(reg.index()); 3249920Syasuko.eckert@amd.com } 3259920Syasuko.eckert@amd.com 32612107SRekai.GonzalezAlberquilla@arm.com template<typename T> 32712107SRekai.GonzalezAlberquilla@arm.com void setScalarResult(T&& t) 3288733Sgeoffrey.blake@arm.com { 32912107SRekai.GonzalezAlberquilla@arm.com result.push(InstResult(std::forward<T>(t), 33012107SRekai.GonzalezAlberquilla@arm.com InstResult::ResultType::Scalar)); 3318733Sgeoffrey.blake@arm.com } 3328733Sgeoffrey.blake@arm.com 33312109SRekai.GonzalezAlberquilla@arm.com template<typename T> 33412109SRekai.GonzalezAlberquilla@arm.com void setVecResult(T&& t) 33512109SRekai.GonzalezAlberquilla@arm.com { 33612109SRekai.GonzalezAlberquilla@arm.com result.push(InstResult(std::forward<T>(t), 33712109SRekai.GonzalezAlberquilla@arm.com InstResult::ResultType::VecReg)); 33812109SRekai.GonzalezAlberquilla@arm.com } 33912109SRekai.GonzalezAlberquilla@arm.com 34012109SRekai.GonzalezAlberquilla@arm.com template<typename T> 34112109SRekai.GonzalezAlberquilla@arm.com void setVecElemResult(T&& t) 34212109SRekai.GonzalezAlberquilla@arm.com { 34312109SRekai.GonzalezAlberquilla@arm.com result.push(InstResult(std::forward<T>(t), 34412109SRekai.GonzalezAlberquilla@arm.com InstResult::ResultType::VecElem)); 34512109SRekai.GonzalezAlberquilla@arm.com } 34612109SRekai.GonzalezAlberquilla@arm.com 34711169Sandreas.hansson@arm.com void setIntRegOperand(const StaticInst *si, int idx, 34811169Sandreas.hansson@arm.com IntReg val) override 3492315SN/A { 35012106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 35112106SRekai.GonzalezAlberquilla@arm.com assert(reg.isIntReg()); 35212106SRekai.GonzalezAlberquilla@arm.com thread->setIntReg(reg.index(), val); 35312107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 3542315SN/A } 3552315SN/A 35611169Sandreas.hansson@arm.com void setFloatRegOperand(const StaticInst *si, int idx, 35711169Sandreas.hansson@arm.com FloatReg val) override 3582669Sktlim@umich.edu { 35912106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 36012106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 36112106SRekai.GonzalezAlberquilla@arm.com thread->setFloatReg(reg.index(), val); 36212107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 3632315SN/A } 3642315SN/A 3653735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 36611169Sandreas.hansson@arm.com FloatRegBits val) override 3672315SN/A { 36812106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 36912106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 37012106SRekai.GonzalezAlberquilla@arm.com thread->setFloatRegBits(reg.index(), val); 37112107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 3722315SN/A } 3732315SN/A 37411169Sandreas.hansson@arm.com void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override 3759920Syasuko.eckert@amd.com { 37612106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 37712106SRekai.GonzalezAlberquilla@arm.com assert(reg.isCCReg()); 37812106SRekai.GonzalezAlberquilla@arm.com thread->setCCReg(reg.index(), val); 37912107SRekai.GonzalezAlberquilla@arm.com setScalarResult((uint64_t)val); 3809920Syasuko.eckert@amd.com } 3819920Syasuko.eckert@amd.com 38212109SRekai.GonzalezAlberquilla@arm.com void setVecRegOperand(const StaticInst *si, int idx, 38312109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& val) override 38412109SRekai.GonzalezAlberquilla@arm.com { 38512109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 38612109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 38712109SRekai.GonzalezAlberquilla@arm.com thread->setVecReg(reg, val); 38812109SRekai.GonzalezAlberquilla@arm.com setVecResult(val); 38912109SRekai.GonzalezAlberquilla@arm.com } 39012109SRekai.GonzalezAlberquilla@arm.com 39112109SRekai.GonzalezAlberquilla@arm.com void setVecElemOperand(const StaticInst *si, int idx, 39212109SRekai.GonzalezAlberquilla@arm.com const VecElem val) override 39312109SRekai.GonzalezAlberquilla@arm.com { 39412109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 39512109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecElem()); 39612109SRekai.GonzalezAlberquilla@arm.com thread->setVecElem(reg, val); 39712109SRekai.GonzalezAlberquilla@arm.com setVecElemResult(val); 39812109SRekai.GonzalezAlberquilla@arm.com } 39912109SRekai.GonzalezAlberquilla@arm.com 40011169Sandreas.hansson@arm.com bool readPredicate() override { return thread->readPredicate(); } 40111169Sandreas.hansson@arm.com void setPredicate(bool val) override 4028733Sgeoffrey.blake@arm.com { 4038733Sgeoffrey.blake@arm.com thread->setPredicate(val); 4048733Sgeoffrey.blake@arm.com } 4052669Sktlim@umich.edu 40611169Sandreas.hansson@arm.com TheISA::PCState pcState() const override { return thread->pcState(); } 40711169Sandreas.hansson@arm.com void pcState(const TheISA::PCState &val) override 4088733Sgeoffrey.blake@arm.com { 4098733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Changing PC to %s, old PC %s.\n", 4108733Sgeoffrey.blake@arm.com val, thread->pcState()); 4118733Sgeoffrey.blake@arm.com thread->pcState(val); 4128733Sgeoffrey.blake@arm.com } 4138733Sgeoffrey.blake@arm.com Addr instAddr() { return thread->instAddr(); } 4148733Sgeoffrey.blake@arm.com Addr nextInstAddr() { return thread->nextInstAddr(); } 4158733Sgeoffrey.blake@arm.com MicroPC microPC() { return thread->microPC(); } 4168733Sgeoffrey.blake@arm.com ////////////////////////////////////////// 4172315SN/A 41810698Sandreas.hansson@arm.com MiscReg readMiscRegNoEffect(int misc_reg) const 4194172Ssaidi@eecs.umich.edu { 4204172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 4214172Ssaidi@eecs.umich.edu } 4224172Ssaidi@eecs.umich.edu 42311169Sandreas.hansson@arm.com MiscReg readMiscReg(int misc_reg) override 4242315SN/A { 4252683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 4262315SN/A } 4272315SN/A 4284172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 4292315SN/A { 43010034SGeoffrey.Blake@arm.com DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n", misc_reg); 4314172Ssaidi@eecs.umich.edu miscRegIdxs.push(misc_reg); 4324172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(misc_reg, val); 4332315SN/A } 4342315SN/A 43511169Sandreas.hansson@arm.com void setMiscReg(int misc_reg, const MiscReg &val) override 4362315SN/A { 43710034SGeoffrey.Blake@arm.com DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg); 4382315SN/A miscRegIdxs.push(misc_reg); 4392683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 4402315SN/A } 4412315SN/A 44211169Sandreas.hansson@arm.com MiscReg readMiscRegOperand(const StaticInst *si, int idx) override 4438733Sgeoffrey.blake@arm.com { 44412106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 44512106SRekai.GonzalezAlberquilla@arm.com assert(reg.isMiscReg()); 44612106SRekai.GonzalezAlberquilla@arm.com return thread->readMiscReg(reg.index()); 4478733Sgeoffrey.blake@arm.com } 4488733Sgeoffrey.blake@arm.com 44911169Sandreas.hansson@arm.com void setMiscRegOperand(const StaticInst *si, int idx, 45011169Sandreas.hansson@arm.com const MiscReg &val) override 4518733Sgeoffrey.blake@arm.com { 45212106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 45312106SRekai.GonzalezAlberquilla@arm.com assert(reg.isMiscReg()); 45412106SRekai.GonzalezAlberquilla@arm.com return this->setMiscReg(reg.index(), val); 4558733Sgeoffrey.blake@arm.com } 4568888Sgeoffrey.blake@arm.com 4578888Sgeoffrey.blake@arm.com#if THE_ISA == MIPS_ISA 45812106SRekai.GonzalezAlberquilla@arm.com MiscReg readRegOtherThread(const RegId& misc_reg, ThreadID tid) override 4598888Sgeoffrey.blake@arm.com { 4608888Sgeoffrey.blake@arm.com panic("MIPS MT not defined for CheckerCPU.\n"); 4618888Sgeoffrey.blake@arm.com return 0; 4628888Sgeoffrey.blake@arm.com } 4638888Sgeoffrey.blake@arm.com 46412106SRekai.GonzalezAlberquilla@arm.com void setRegOtherThread(const RegId& misc_reg, MiscReg val, 46512106SRekai.GonzalezAlberquilla@arm.com ThreadID tid) override 4668888Sgeoffrey.blake@arm.com { 4678888Sgeoffrey.blake@arm.com panic("MIPS MT not defined for CheckerCPU.\n"); 4688888Sgeoffrey.blake@arm.com } 4698888Sgeoffrey.blake@arm.com#endif 4708888Sgeoffrey.blake@arm.com 4718733Sgeoffrey.blake@arm.com ///////////////////////////////////////// 4728733Sgeoffrey.blake@arm.com 4738733Sgeoffrey.blake@arm.com void recordPCChange(const TheISA::PCState &val) 4748733Sgeoffrey.blake@arm.com { 4758733Sgeoffrey.blake@arm.com changedPC = true; 4768733Sgeoffrey.blake@arm.com newPCState = val; 4778733Sgeoffrey.blake@arm.com } 4782315SN/A 47911169Sandreas.hansson@arm.com void demapPage(Addr vaddr, uint64_t asn) override 4805358Sgblack@eecs.umich.edu { 4815358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 4825358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 4835358Sgblack@eecs.umich.edu } 4845358Sgblack@eecs.umich.edu 48510529Smorr@cs.wisc.edu // monitor/mwait funtions 48611169Sandreas.hansson@arm.com void armMonitor(Addr address) override 48711169Sandreas.hansson@arm.com { BaseCPU::armMonitor(0, address); } 48811169Sandreas.hansson@arm.com bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); } 48911169Sandreas.hansson@arm.com void mwaitAtomic(ThreadContext *tc) override 49011148Smitch.hayenga@arm.com { return BaseCPU::mwaitAtomic(0, tc, thread->dtb); } 49111169Sandreas.hansson@arm.com AddressMonitor *getAddrMonitor() override 49211169Sandreas.hansson@arm.com { return BaseCPU::getCpuAddrMonitor(0); } 49310529Smorr@cs.wisc.edu 4945358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 4955358Sgblack@eecs.umich.edu { 4965358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 4975358Sgblack@eecs.umich.edu } 4985358Sgblack@eecs.umich.edu 4995358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 5005358Sgblack@eecs.umich.edu { 5015358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 5025358Sgblack@eecs.umich.edu } 5035358Sgblack@eecs.umich.edu 50411169Sandreas.hansson@arm.com Fault readMem(Addr addr, uint8_t *data, unsigned size, 50511608Snikos.nikoleris@arm.com Request::Flags flags) override; 50611608Snikos.nikoleris@arm.com Fault writeMem(uint8_t *data, unsigned size, Addr addr, 50711608Snikos.nikoleris@arm.com Request::Flags flags, uint64_t *res) override; 5088733Sgeoffrey.blake@arm.com 50911169Sandreas.hansson@arm.com unsigned int readStCondFailures() const override { 51010319SAndreas.Sandberg@ARM.com return thread->readStCondFailures(); 51110319SAndreas.Sandberg@ARM.com } 51210319SAndreas.Sandberg@ARM.com 51311169Sandreas.hansson@arm.com void setStCondFailures(unsigned int sc_failures) override 5148733Sgeoffrey.blake@arm.com {} 5158733Sgeoffrey.blake@arm.com ///////////////////////////////////////////////////// 5168733Sgeoffrey.blake@arm.com 51711169Sandreas.hansson@arm.com Fault hwrei() override { return thread->hwrei(); } 51811169Sandreas.hansson@arm.com bool simPalCheck(int palFunc) override 51911169Sandreas.hansson@arm.com { return thread->simPalCheck(palFunc); } 52011168Sandreas.hansson@arm.com void wakeup(ThreadID tid) override { } 5212315SN/A // Assume that the normal CPU's call to syscall was successful. 5222332SN/A // The checker's state would have already been updated by the syscall. 52311877Sbrandon.potter@amd.com void syscall(int64_t callnum, Fault *fault) override { } 5242315SN/A 5252315SN/A void handleError() 5262315SN/A { 5272315SN/A if (exitOnError) 5282732Sktlim@umich.edu dumpAndExit(); 5292315SN/A } 5302732Sktlim@umich.edu 53112749Sgiacomo.travaglini@arm.com bool checkFlags(const RequestPtr &unverified_req, Addr vAddr, 5328733Sgeoffrey.blake@arm.com Addr pAddr, int flags); 5332315SN/A 5342732Sktlim@umich.edu void dumpAndExit(); 5352732Sktlim@umich.edu 53611169Sandreas.hansson@arm.com ThreadContext *tcBase() override { return tc; } 5372683Sktlim@umich.edu SimpleThread *threadBase() { return thread; } 5382315SN/A 53912107SRekai.GonzalezAlberquilla@arm.com InstResult unverifiedResult; 54012748Sgiacomo.travaglini@arm.com RequestPtr unverifiedReq; 5412679Sktlim@umich.edu uint8_t *unverifiedMemData; 5422315SN/A 5432315SN/A bool changedPC; 5442315SN/A bool willChangePC; 5458733Sgeoffrey.blake@arm.com TheISA::PCState newPCState; 5462315SN/A bool exitOnError; 5472354SN/A bool updateOnError; 5482732Sktlim@umich.edu bool warnOnlyOnLoadError; 5492315SN/A 5502315SN/A InstSeqNum youngestSN; 5512315SN/A}; 5522315SN/A 5532350SN/A/** 5542350SN/A * Templated Checker class. This Checker class is templated on the 5552350SN/A * DynInstPtr of the instruction type that will be verified. Proper 5562350SN/A * template instantiations of the Checker must be placed at the bottom 5572350SN/A * of checker/cpu.cc. 5582350SN/A */ 5598733Sgeoffrey.blake@arm.comtemplate <class Impl> 5602315SN/Aclass Checker : public CheckerCPU 5612315SN/A{ 5628733Sgeoffrey.blake@arm.com private: 5638733Sgeoffrey.blake@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 5648733Sgeoffrey.blake@arm.com 5652315SN/A public: 5662315SN/A Checker(Params *p) 5679023Sgblack@eecs.umich.edu : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL) 5682315SN/A { } 5692315SN/A 5702840Sktlim@umich.edu void switchOut(); 5712315SN/A void takeOverFrom(BaseCPU *oldCPU); 5722315SN/A 57310379Sandreas.hansson@arm.com void advancePC(const Fault &fault); 5748733Sgeoffrey.blake@arm.com 5752732Sktlim@umich.edu void verify(DynInstPtr &inst); 5762315SN/A 5772315SN/A void validateInst(DynInstPtr &inst); 5782315SN/A void validateExecution(DynInstPtr &inst); 5792315SN/A void validateState(); 5802315SN/A 58112107SRekai.GonzalezAlberquilla@arm.com void copyResult(DynInstPtr &inst, const InstResult& mismatch_val, 58212107SRekai.GonzalezAlberquilla@arm.com int start_idx); 5838733Sgeoffrey.blake@arm.com void handlePendingInt(); 5842732Sktlim@umich.edu 5852732Sktlim@umich.edu private: 5862732Sktlim@umich.edu void handleError(DynInstPtr &inst) 5872732Sktlim@umich.edu { 5882360SN/A if (exitOnError) { 5892732Sktlim@umich.edu dumpAndExit(inst); 5902360SN/A } else if (updateOnError) { 5912354SN/A updateThisCycle = true; 5922360SN/A } 5932732Sktlim@umich.edu } 5942732Sktlim@umich.edu 5952732Sktlim@umich.edu void dumpAndExit(DynInstPtr &inst); 5962732Sktlim@umich.edu 5972354SN/A bool updateThisCycle; 5982354SN/A 5992354SN/A DynInstPtr unverifiedInst; 6002354SN/A 6012315SN/A std::list<DynInstPtr> instList; 6022315SN/A typedef typename std::list<DynInstPtr>::iterator InstListIt; 6032315SN/A void dumpInsts(); 6042315SN/A}; 6052315SN/A 6062315SN/A#endif // __CPU_CHECKER_CPU_HH__ 607