cpu.hh revision 12748
12315SN/A/* 212107SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2011, 2016 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152332SN/A * Copyright (c) 2006 The Regents of The University of Michigan 162315SN/A * All rights reserved. 172315SN/A * 182315SN/A * Redistribution and use in source and binary forms, with or without 192315SN/A * modification, are permitted provided that the following conditions are 202315SN/A * met: redistributions of source code must retain the above copyright 212315SN/A * notice, this list of conditions and the following disclaimer; 222315SN/A * redistributions in binary form must reproduce the above copyright 232315SN/A * notice, this list of conditions and the following disclaimer in the 242315SN/A * documentation and/or other materials provided with the distribution; 252315SN/A * neither the name of the copyright holders nor the names of its 262315SN/A * contributors may be used to endorse or promote products derived from 272315SN/A * this software without specific prior written permission. 282315SN/A * 292315SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302315SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312315SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322315SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332315SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342315SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362315SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372315SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382315SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392315SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Kevin Lim 422315SN/A */ 432315SN/A 442315SN/A#ifndef __CPU_CHECKER_CPU_HH__ 452315SN/A#define __CPU_CHECKER_CPU_HH__ 462315SN/A 472315SN/A#include <list> 488229Snate@binkert.org#include <map> 492315SN/A#include <queue> 502315SN/A 512669Sktlim@umich.edu#include "arch/types.hh" 522315SN/A#include "base/statistics.hh" 532315SN/A#include "cpu/base.hh" 542315SN/A#include "cpu/base_dyn_inst.hh" 5510319SAndreas.Sandberg@ARM.com#include "cpu/exec_context.hh" 5612107SRekai.GonzalezAlberquilla@arm.com#include "cpu/inst_res.hh" 578229Snate@binkert.org#include "cpu/pc_event.hh" 582683Sktlim@umich.edu#include "cpu/simple_thread.hh" 592315SN/A#include "cpu/static_inst.hh" 608733Sgeoffrey.blake@arm.com#include "debug/Checker.hh" 6111608Snikos.nikoleris@arm.com#include "mem/request.hh" 628733Sgeoffrey.blake@arm.com#include "params/CheckerCPU.hh" 632315SN/A#include "sim/eventq.hh" 642315SN/A 6512406Sgabeblack@google.comclass BaseTLB; 662315SN/Atemplate <class> 672315SN/Aclass BaseDynInst; 682680Sktlim@umich.educlass ThreadContext; 692669Sktlim@umich.educlass Request; 702315SN/A 712350SN/A/** 722350SN/A * CheckerCPU class. Dynamically verifies instructions as they are 732350SN/A * completed by making sure that the instruction and its results match 742350SN/A * the independent execution of the benchmark inside the checker. The 752350SN/A * checker verifies instructions in order, regardless of the order in 762350SN/A * which instructions complete. There are certain results that can 772350SN/A * not be verified, specifically the result of a store conditional or 782350SN/A * the values of uncached accesses. In these cases, and with 792350SN/A * instructions marked as "IsUnverifiable", the checker assumes that 802350SN/A * the value from the main CPU's execution is correct and simply 812680Sktlim@umich.edu * copies that value. It provides a CheckerThreadContext (see 822683Sktlim@umich.edu * checker/thread_context.hh) that provides hooks for updating the 832680Sktlim@umich.edu * Checker's state through any ThreadContext accesses. This allows the 842350SN/A * checker to be able to correctly verify instructions, even with 852680Sktlim@umich.edu * external accesses to the ThreadContext that change state. 862350SN/A */ 8710319SAndreas.Sandberg@ARM.comclass CheckerCPU : public BaseCPU, public ExecContext 882315SN/A{ 892315SN/A protected: 902315SN/A typedef TheISA::MachInst MachInst; 912669Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 922669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 932315SN/A typedef TheISA::MiscReg MiscReg; 9412109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 958832SAli.Saidi@ARM.com 968832SAli.Saidi@ARM.com /** id attached to all issued requests */ 978832SAli.Saidi@ARM.com MasterID masterId; 982315SN/A public: 9911169Sandreas.hansson@arm.com void init() override; 1002315SN/A 1015529Snate@binkert.org typedef CheckerCPUParams Params; 1022315SN/A CheckerCPU(Params *p); 1032315SN/A virtual ~CheckerCPU(); 1042315SN/A 1052315SN/A void setSystem(System *system); 1062315SN/A 1079608Sandreas.hansson@arm.com void setIcachePort(MasterPort *icache_port); 1082679Sktlim@umich.edu 1099608Sandreas.hansson@arm.com void setDcachePort(MasterPort *dcache_port); 1102679Sktlim@umich.edu 11111169Sandreas.hansson@arm.com MasterPort &getDataPort() override 1128887Sgeoffrey.blake@arm.com { 1139176Sandreas.hansson@arm.com // the checker does not have ports on its own so return the 1149176Sandreas.hansson@arm.com // data port of the actual CPU core 1159176Sandreas.hansson@arm.com assert(dcachePort); 1168887Sgeoffrey.blake@arm.com return *dcachePort; 1178887Sgeoffrey.blake@arm.com } 1188887Sgeoffrey.blake@arm.com 11911169Sandreas.hansson@arm.com MasterPort &getInstPort() override 1208887Sgeoffrey.blake@arm.com { 1219176Sandreas.hansson@arm.com // the checker does not have ports on its own so return the 1229176Sandreas.hansson@arm.com // data port of the actual CPU core 1239176Sandreas.hansson@arm.com assert(icachePort); 1248887Sgeoffrey.blake@arm.com return *icachePort; 1258887Sgeoffrey.blake@arm.com } 1262679Sktlim@umich.edu 1279176Sandreas.hansson@arm.com protected: 1289176Sandreas.hansson@arm.com 1299176Sandreas.hansson@arm.com std::vector<Process*> workload; 1309176Sandreas.hansson@arm.com 1319176Sandreas.hansson@arm.com System *systemPtr; 1329176Sandreas.hansson@arm.com 1339608Sandreas.hansson@arm.com MasterPort *icachePort; 1349608Sandreas.hansson@arm.com MasterPort *dcachePort; 1352315SN/A 1362680Sktlim@umich.edu ThreadContext *tc; 1372315SN/A 13812406Sgabeblack@google.com BaseTLB *itb; 13912406Sgabeblack@google.com BaseTLB *dtb; 1402315SN/A 1412315SN/A Addr dbg_vtophys(Addr addr); 1422315SN/A 1438733Sgeoffrey.blake@arm.com // ISAs like ARM can have multiple destination registers to check, 1448733Sgeoffrey.blake@arm.com // keep them all in a std::queue 14512107SRekai.GonzalezAlberquilla@arm.com std::queue<InstResult> result; 1462315SN/A 1472679Sktlim@umich.edu // Pointer to the one memory request. 1482679Sktlim@umich.edu RequestPtr memReq; 1492315SN/A 1502315SN/A StaticInstPtr curStaticInst; 1518733Sgeoffrey.blake@arm.com StaticInstPtr curMacroStaticInst; 1522315SN/A 1532315SN/A // number of simulated instructions 1542315SN/A Counter numInst; 1552315SN/A Counter startNumInst; 1562315SN/A 1572315SN/A std::queue<int> miscRegIdxs; 1582315SN/A 1599176Sandreas.hansson@arm.com public: 1609176Sandreas.hansson@arm.com 1619176Sandreas.hansson@arm.com // Primary thread being run. 1629176Sandreas.hansson@arm.com SimpleThread *thread; 1639176Sandreas.hansson@arm.com 16412406Sgabeblack@google.com BaseTLB* getITBPtr() { return itb; } 16512406Sgabeblack@google.com BaseTLB* getDTBPtr() { return dtb; } 1668733Sgeoffrey.blake@arm.com 16711169Sandreas.hansson@arm.com virtual Counter totalInsts() const override 1688887Sgeoffrey.blake@arm.com { 1698887Sgeoffrey.blake@arm.com return 0; 1708887Sgeoffrey.blake@arm.com } 1718887Sgeoffrey.blake@arm.com 17211169Sandreas.hansson@arm.com virtual Counter totalOps() const override 1732315SN/A { 1742930Sktlim@umich.edu return 0; 1752315SN/A } 1762315SN/A 1772315SN/A // number of simulated loads 1782315SN/A Counter numLoad; 1792315SN/A Counter startNumLoad; 1802315SN/A 18111168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 18211168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 1832315SN/A 1842315SN/A // The register accessor methods provide the index of the 1852315SN/A // instruction's operand (e.g., 0 or 1), not the architectural 1862315SN/A // register index, to simplify the implementation of register 1872315SN/A // renaming. We find the architectural register index by indexing 1882315SN/A // into the instruction's own operand index table. Note that a 1892315SN/A // raw pointer to the StaticInst is provided instead of a 1902315SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 1912315SN/A // long as these methods don't copy the pointer into any long-term 1922315SN/A // storage (which is pretty hard to imagine they would have reason 1932315SN/A // to do). 1942315SN/A 19511169Sandreas.hansson@arm.com IntReg readIntRegOperand(const StaticInst *si, int idx) override 1962315SN/A { 19712106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 19812106SRekai.GonzalezAlberquilla@arm.com assert(reg.isIntReg()); 19912106SRekai.GonzalezAlberquilla@arm.com return thread->readIntReg(reg.index()); 2002315SN/A } 2012315SN/A 20211169Sandreas.hansson@arm.com FloatReg readFloatRegOperand(const StaticInst *si, int idx) override 2032315SN/A { 20412106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 20512106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 20612106SRekai.GonzalezAlberquilla@arm.com return thread->readFloatReg(reg.index()); 2072315SN/A } 2082315SN/A 20911169Sandreas.hansson@arm.com FloatRegBits readFloatRegOperandBits(const StaticInst *si, 21011169Sandreas.hansson@arm.com int idx) override 2112669Sktlim@umich.edu { 21212106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 21312106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 21412106SRekai.GonzalezAlberquilla@arm.com return thread->readFloatRegBits(reg.index()); 2152315SN/A } 2162315SN/A 21712109SRekai.GonzalezAlberquilla@arm.com /** 21812109SRekai.GonzalezAlberquilla@arm.com * Read source vector register operand. 21912109SRekai.GonzalezAlberquilla@arm.com */ 22012109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& readVecRegOperand(const StaticInst *si, 22112109SRekai.GonzalezAlberquilla@arm.com int idx) const override 22212109SRekai.GonzalezAlberquilla@arm.com { 22312109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 22412109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 22512109SRekai.GonzalezAlberquilla@arm.com return thread->readVecReg(reg); 22612109SRekai.GonzalezAlberquilla@arm.com } 22712109SRekai.GonzalezAlberquilla@arm.com 22812109SRekai.GonzalezAlberquilla@arm.com /** 22912109SRekai.GonzalezAlberquilla@arm.com * Read destination vector register operand for modification. 23012109SRekai.GonzalezAlberquilla@arm.com */ 23112109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& getWritableVecRegOperand(const StaticInst *si, 23212109SRekai.GonzalezAlberquilla@arm.com int idx) override 23312109SRekai.GonzalezAlberquilla@arm.com { 23412109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 23512109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 23612109SRekai.GonzalezAlberquilla@arm.com return thread->getWritableVecReg(reg); 23712109SRekai.GonzalezAlberquilla@arm.com } 23812109SRekai.GonzalezAlberquilla@arm.com 23912109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 24012109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 24112109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 24212109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane8 24312109SRekai.GonzalezAlberquilla@arm.com readVec8BitLaneOperand(const StaticInst *si, int idx) const 24412109SRekai.GonzalezAlberquilla@arm.com override 24512109SRekai.GonzalezAlberquilla@arm.com { 24612109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 24712109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 24812109SRekai.GonzalezAlberquilla@arm.com return thread->readVec8BitLaneReg(reg); 24912109SRekai.GonzalezAlberquilla@arm.com } 25012109SRekai.GonzalezAlberquilla@arm.com 25112109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 25212109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane16 25312109SRekai.GonzalezAlberquilla@arm.com readVec16BitLaneOperand(const StaticInst *si, int idx) const 25412109SRekai.GonzalezAlberquilla@arm.com override 25512109SRekai.GonzalezAlberquilla@arm.com { 25612109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 25712109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 25812109SRekai.GonzalezAlberquilla@arm.com return thread->readVec16BitLaneReg(reg); 25912109SRekai.GonzalezAlberquilla@arm.com } 26012109SRekai.GonzalezAlberquilla@arm.com 26112109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 26212109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane32 26312109SRekai.GonzalezAlberquilla@arm.com readVec32BitLaneOperand(const StaticInst *si, int idx) const 26412109SRekai.GonzalezAlberquilla@arm.com override 26512109SRekai.GonzalezAlberquilla@arm.com { 26612109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 26712109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 26812109SRekai.GonzalezAlberquilla@arm.com return thread->readVec32BitLaneReg(reg); 26912109SRekai.GonzalezAlberquilla@arm.com } 27012109SRekai.GonzalezAlberquilla@arm.com 27112109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 27212109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane64 27312109SRekai.GonzalezAlberquilla@arm.com readVec64BitLaneOperand(const StaticInst *si, int idx) const 27412109SRekai.GonzalezAlberquilla@arm.com override 27512109SRekai.GonzalezAlberquilla@arm.com { 27612109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 27712109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 27812109SRekai.GonzalezAlberquilla@arm.com return thread->readVec64BitLaneReg(reg); 27912109SRekai.GonzalezAlberquilla@arm.com } 28012109SRekai.GonzalezAlberquilla@arm.com 28112109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector operand. */ 28212109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 28312109SRekai.GonzalezAlberquilla@arm.com void 28412109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(const StaticInst *si, int idx, const LD& val) 28512109SRekai.GonzalezAlberquilla@arm.com { 28612109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 28712109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 28812109SRekai.GonzalezAlberquilla@arm.com return thread->setVecLane(reg, val); 28912109SRekai.GonzalezAlberquilla@arm.com } 29012109SRekai.GonzalezAlberquilla@arm.com virtual void 29112109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 29212109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) override 29312109SRekai.GonzalezAlberquilla@arm.com { 29412109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(si, idx, val); 29512109SRekai.GonzalezAlberquilla@arm.com } 29612109SRekai.GonzalezAlberquilla@arm.com virtual void 29712109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 29812109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) override 29912109SRekai.GonzalezAlberquilla@arm.com { 30012109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(si, idx, val); 30112109SRekai.GonzalezAlberquilla@arm.com } 30212109SRekai.GonzalezAlberquilla@arm.com virtual void 30312109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 30412109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) override 30512109SRekai.GonzalezAlberquilla@arm.com { 30612109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(si, idx, val); 30712109SRekai.GonzalezAlberquilla@arm.com } 30812109SRekai.GonzalezAlberquilla@arm.com virtual void 30912109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperand(const StaticInst *si, int idx, 31012109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) override 31112109SRekai.GonzalezAlberquilla@arm.com { 31212109SRekai.GonzalezAlberquilla@arm.com setVecLaneOperandT(si, idx, val); 31312109SRekai.GonzalezAlberquilla@arm.com } 31412109SRekai.GonzalezAlberquilla@arm.com /** @} */ 31512109SRekai.GonzalezAlberquilla@arm.com 31612109SRekai.GonzalezAlberquilla@arm.com VecElem readVecElemOperand(const StaticInst *si, int idx) const override 31712109SRekai.GonzalezAlberquilla@arm.com { 31812109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 31912109SRekai.GonzalezAlberquilla@arm.com return thread->readVecElem(reg); 32012109SRekai.GonzalezAlberquilla@arm.com } 32112109SRekai.GonzalezAlberquilla@arm.com 32211169Sandreas.hansson@arm.com CCReg readCCRegOperand(const StaticInst *si, int idx) override 3239920Syasuko.eckert@amd.com { 32412106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 32512106SRekai.GonzalezAlberquilla@arm.com assert(reg.isCCReg()); 32612106SRekai.GonzalezAlberquilla@arm.com return thread->readCCReg(reg.index()); 3279920Syasuko.eckert@amd.com } 3289920Syasuko.eckert@amd.com 32912107SRekai.GonzalezAlberquilla@arm.com template<typename T> 33012107SRekai.GonzalezAlberquilla@arm.com void setScalarResult(T&& t) 3318733Sgeoffrey.blake@arm.com { 33212107SRekai.GonzalezAlberquilla@arm.com result.push(InstResult(std::forward<T>(t), 33312107SRekai.GonzalezAlberquilla@arm.com InstResult::ResultType::Scalar)); 3348733Sgeoffrey.blake@arm.com } 3358733Sgeoffrey.blake@arm.com 33612109SRekai.GonzalezAlberquilla@arm.com template<typename T> 33712109SRekai.GonzalezAlberquilla@arm.com void setVecResult(T&& t) 33812109SRekai.GonzalezAlberquilla@arm.com { 33912109SRekai.GonzalezAlberquilla@arm.com result.push(InstResult(std::forward<T>(t), 34012109SRekai.GonzalezAlberquilla@arm.com InstResult::ResultType::VecReg)); 34112109SRekai.GonzalezAlberquilla@arm.com } 34212109SRekai.GonzalezAlberquilla@arm.com 34312109SRekai.GonzalezAlberquilla@arm.com template<typename T> 34412109SRekai.GonzalezAlberquilla@arm.com void setVecElemResult(T&& t) 34512109SRekai.GonzalezAlberquilla@arm.com { 34612109SRekai.GonzalezAlberquilla@arm.com result.push(InstResult(std::forward<T>(t), 34712109SRekai.GonzalezAlberquilla@arm.com InstResult::ResultType::VecElem)); 34812109SRekai.GonzalezAlberquilla@arm.com } 34912109SRekai.GonzalezAlberquilla@arm.com 35011169Sandreas.hansson@arm.com void setIntRegOperand(const StaticInst *si, int idx, 35111169Sandreas.hansson@arm.com IntReg val) override 3522315SN/A { 35312106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 35412106SRekai.GonzalezAlberquilla@arm.com assert(reg.isIntReg()); 35512106SRekai.GonzalezAlberquilla@arm.com thread->setIntReg(reg.index(), val); 35612107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 3572315SN/A } 3582315SN/A 35911169Sandreas.hansson@arm.com void setFloatRegOperand(const StaticInst *si, int idx, 36011169Sandreas.hansson@arm.com FloatReg val) override 3612669Sktlim@umich.edu { 36212106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 36312106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 36412106SRekai.GonzalezAlberquilla@arm.com thread->setFloatReg(reg.index(), val); 36512107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 3662315SN/A } 3672315SN/A 3683735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 36911169Sandreas.hansson@arm.com FloatRegBits val) override 3702315SN/A { 37112106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 37212106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 37312106SRekai.GonzalezAlberquilla@arm.com thread->setFloatRegBits(reg.index(), val); 37412107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 3752315SN/A } 3762315SN/A 37711169Sandreas.hansson@arm.com void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override 3789920Syasuko.eckert@amd.com { 37912106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 38012106SRekai.GonzalezAlberquilla@arm.com assert(reg.isCCReg()); 38112106SRekai.GonzalezAlberquilla@arm.com thread->setCCReg(reg.index(), val); 38212107SRekai.GonzalezAlberquilla@arm.com setScalarResult((uint64_t)val); 3839920Syasuko.eckert@amd.com } 3849920Syasuko.eckert@amd.com 38512109SRekai.GonzalezAlberquilla@arm.com void setVecRegOperand(const StaticInst *si, int idx, 38612109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& val) override 38712109SRekai.GonzalezAlberquilla@arm.com { 38812109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 38912109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecReg()); 39012109SRekai.GonzalezAlberquilla@arm.com thread->setVecReg(reg, val); 39112109SRekai.GonzalezAlberquilla@arm.com setVecResult(val); 39212109SRekai.GonzalezAlberquilla@arm.com } 39312109SRekai.GonzalezAlberquilla@arm.com 39412109SRekai.GonzalezAlberquilla@arm.com void setVecElemOperand(const StaticInst *si, int idx, 39512109SRekai.GonzalezAlberquilla@arm.com const VecElem val) override 39612109SRekai.GonzalezAlberquilla@arm.com { 39712109SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 39812109SRekai.GonzalezAlberquilla@arm.com assert(reg.isVecElem()); 39912109SRekai.GonzalezAlberquilla@arm.com thread->setVecElem(reg, val); 40012109SRekai.GonzalezAlberquilla@arm.com setVecElemResult(val); 40112109SRekai.GonzalezAlberquilla@arm.com } 40212109SRekai.GonzalezAlberquilla@arm.com 40311169Sandreas.hansson@arm.com bool readPredicate() override { return thread->readPredicate(); } 40411169Sandreas.hansson@arm.com void setPredicate(bool val) override 4058733Sgeoffrey.blake@arm.com { 4068733Sgeoffrey.blake@arm.com thread->setPredicate(val); 4078733Sgeoffrey.blake@arm.com } 4082669Sktlim@umich.edu 40911169Sandreas.hansson@arm.com TheISA::PCState pcState() const override { return thread->pcState(); } 41011169Sandreas.hansson@arm.com void pcState(const TheISA::PCState &val) override 4118733Sgeoffrey.blake@arm.com { 4128733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Changing PC to %s, old PC %s.\n", 4138733Sgeoffrey.blake@arm.com val, thread->pcState()); 4148733Sgeoffrey.blake@arm.com thread->pcState(val); 4158733Sgeoffrey.blake@arm.com } 4168733Sgeoffrey.blake@arm.com Addr instAddr() { return thread->instAddr(); } 4178733Sgeoffrey.blake@arm.com Addr nextInstAddr() { return thread->nextInstAddr(); } 4188733Sgeoffrey.blake@arm.com MicroPC microPC() { return thread->microPC(); } 4198733Sgeoffrey.blake@arm.com ////////////////////////////////////////// 4202315SN/A 42110698Sandreas.hansson@arm.com MiscReg readMiscRegNoEffect(int misc_reg) const 4224172Ssaidi@eecs.umich.edu { 4234172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 4244172Ssaidi@eecs.umich.edu } 4254172Ssaidi@eecs.umich.edu 42611169Sandreas.hansson@arm.com MiscReg readMiscReg(int misc_reg) override 4272315SN/A { 4282683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 4292315SN/A } 4302315SN/A 4314172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 4322315SN/A { 43310034SGeoffrey.Blake@arm.com DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n", misc_reg); 4344172Ssaidi@eecs.umich.edu miscRegIdxs.push(misc_reg); 4354172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(misc_reg, val); 4362315SN/A } 4372315SN/A 43811169Sandreas.hansson@arm.com void setMiscReg(int misc_reg, const MiscReg &val) override 4392315SN/A { 44010034SGeoffrey.Blake@arm.com DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg); 4412315SN/A miscRegIdxs.push(misc_reg); 4422683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 4432315SN/A } 4442315SN/A 44511169Sandreas.hansson@arm.com MiscReg readMiscRegOperand(const StaticInst *si, int idx) override 4468733Sgeoffrey.blake@arm.com { 44712106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 44812106SRekai.GonzalezAlberquilla@arm.com assert(reg.isMiscReg()); 44912106SRekai.GonzalezAlberquilla@arm.com return thread->readMiscReg(reg.index()); 4508733Sgeoffrey.blake@arm.com } 4518733Sgeoffrey.blake@arm.com 45211169Sandreas.hansson@arm.com void setMiscRegOperand(const StaticInst *si, int idx, 45311169Sandreas.hansson@arm.com const MiscReg &val) override 4548733Sgeoffrey.blake@arm.com { 45512106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 45612106SRekai.GonzalezAlberquilla@arm.com assert(reg.isMiscReg()); 45712106SRekai.GonzalezAlberquilla@arm.com return this->setMiscReg(reg.index(), val); 4588733Sgeoffrey.blake@arm.com } 4598888Sgeoffrey.blake@arm.com 4608888Sgeoffrey.blake@arm.com#if THE_ISA == MIPS_ISA 46112106SRekai.GonzalezAlberquilla@arm.com MiscReg readRegOtherThread(const RegId& misc_reg, ThreadID tid) override 4628888Sgeoffrey.blake@arm.com { 4638888Sgeoffrey.blake@arm.com panic("MIPS MT not defined for CheckerCPU.\n"); 4648888Sgeoffrey.blake@arm.com return 0; 4658888Sgeoffrey.blake@arm.com } 4668888Sgeoffrey.blake@arm.com 46712106SRekai.GonzalezAlberquilla@arm.com void setRegOtherThread(const RegId& misc_reg, MiscReg val, 46812106SRekai.GonzalezAlberquilla@arm.com ThreadID tid) override 4698888Sgeoffrey.blake@arm.com { 4708888Sgeoffrey.blake@arm.com panic("MIPS MT not defined for CheckerCPU.\n"); 4718888Sgeoffrey.blake@arm.com } 4728888Sgeoffrey.blake@arm.com#endif 4738888Sgeoffrey.blake@arm.com 4748733Sgeoffrey.blake@arm.com ///////////////////////////////////////// 4758733Sgeoffrey.blake@arm.com 4768733Sgeoffrey.blake@arm.com void recordPCChange(const TheISA::PCState &val) 4778733Sgeoffrey.blake@arm.com { 4788733Sgeoffrey.blake@arm.com changedPC = true; 4798733Sgeoffrey.blake@arm.com newPCState = val; 4808733Sgeoffrey.blake@arm.com } 4812315SN/A 48211169Sandreas.hansson@arm.com void demapPage(Addr vaddr, uint64_t asn) override 4835358Sgblack@eecs.umich.edu { 4845358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 4855358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 4865358Sgblack@eecs.umich.edu } 4875358Sgblack@eecs.umich.edu 48810529Smorr@cs.wisc.edu // monitor/mwait funtions 48911169Sandreas.hansson@arm.com void armMonitor(Addr address) override 49011169Sandreas.hansson@arm.com { BaseCPU::armMonitor(0, address); } 49111169Sandreas.hansson@arm.com bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); } 49211169Sandreas.hansson@arm.com void mwaitAtomic(ThreadContext *tc) override 49311148Smitch.hayenga@arm.com { return BaseCPU::mwaitAtomic(0, tc, thread->dtb); } 49411169Sandreas.hansson@arm.com AddressMonitor *getAddrMonitor() override 49511169Sandreas.hansson@arm.com { return BaseCPU::getCpuAddrMonitor(0); } 49610529Smorr@cs.wisc.edu 4975358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 4985358Sgblack@eecs.umich.edu { 4995358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 5005358Sgblack@eecs.umich.edu } 5015358Sgblack@eecs.umich.edu 5025358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 5035358Sgblack@eecs.umich.edu { 5045358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 5055358Sgblack@eecs.umich.edu } 5065358Sgblack@eecs.umich.edu 50711169Sandreas.hansson@arm.com Fault readMem(Addr addr, uint8_t *data, unsigned size, 50811608Snikos.nikoleris@arm.com Request::Flags flags) override; 50911608Snikos.nikoleris@arm.com Fault writeMem(uint8_t *data, unsigned size, Addr addr, 51011608Snikos.nikoleris@arm.com Request::Flags flags, uint64_t *res) override; 5118733Sgeoffrey.blake@arm.com 51211169Sandreas.hansson@arm.com unsigned int readStCondFailures() const override { 51310319SAndreas.Sandberg@ARM.com return thread->readStCondFailures(); 51410319SAndreas.Sandberg@ARM.com } 51510319SAndreas.Sandberg@ARM.com 51611169Sandreas.hansson@arm.com void setStCondFailures(unsigned int sc_failures) override 5178733Sgeoffrey.blake@arm.com {} 5188733Sgeoffrey.blake@arm.com ///////////////////////////////////////////////////// 5198733Sgeoffrey.blake@arm.com 52011169Sandreas.hansson@arm.com Fault hwrei() override { return thread->hwrei(); } 52111169Sandreas.hansson@arm.com bool simPalCheck(int palFunc) override 52211169Sandreas.hansson@arm.com { return thread->simPalCheck(palFunc); } 52311168Sandreas.hansson@arm.com void wakeup(ThreadID tid) override { } 5242315SN/A // Assume that the normal CPU's call to syscall was successful. 5252332SN/A // The checker's state would have already been updated by the syscall. 52611877Sbrandon.potter@amd.com void syscall(int64_t callnum, Fault *fault) override { } 5272315SN/A 5282315SN/A void handleError() 5292315SN/A { 5302315SN/A if (exitOnError) 5312732Sktlim@umich.edu dumpAndExit(); 5322315SN/A } 5332732Sktlim@umich.edu 53412748Sgiacomo.travaglini@arm.com bool checkFlags(RequestPtr unverified_req, Addr vAddr, 5358733Sgeoffrey.blake@arm.com Addr pAddr, int flags); 5362315SN/A 5372732Sktlim@umich.edu void dumpAndExit(); 5382732Sktlim@umich.edu 53911169Sandreas.hansson@arm.com ThreadContext *tcBase() override { return tc; } 5402683Sktlim@umich.edu SimpleThread *threadBase() { return thread; } 5412315SN/A 54212107SRekai.GonzalezAlberquilla@arm.com InstResult unverifiedResult; 54312748Sgiacomo.travaglini@arm.com RequestPtr unverifiedReq; 5442679Sktlim@umich.edu uint8_t *unverifiedMemData; 5452315SN/A 5462315SN/A bool changedPC; 5472315SN/A bool willChangePC; 5488733Sgeoffrey.blake@arm.com TheISA::PCState newPCState; 5492315SN/A bool exitOnError; 5502354SN/A bool updateOnError; 5512732Sktlim@umich.edu bool warnOnlyOnLoadError; 5522315SN/A 5532315SN/A InstSeqNum youngestSN; 5542315SN/A}; 5552315SN/A 5562350SN/A/** 5572350SN/A * Templated Checker class. This Checker class is templated on the 5582350SN/A * DynInstPtr of the instruction type that will be verified. Proper 5592350SN/A * template instantiations of the Checker must be placed at the bottom 5602350SN/A * of checker/cpu.cc. 5612350SN/A */ 5628733Sgeoffrey.blake@arm.comtemplate <class Impl> 5632315SN/Aclass Checker : public CheckerCPU 5642315SN/A{ 5658733Sgeoffrey.blake@arm.com private: 5668733Sgeoffrey.blake@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 5678733Sgeoffrey.blake@arm.com 5682315SN/A public: 5692315SN/A Checker(Params *p) 5709023Sgblack@eecs.umich.edu : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL) 5712315SN/A { } 5722315SN/A 5732840Sktlim@umich.edu void switchOut(); 5742315SN/A void takeOverFrom(BaseCPU *oldCPU); 5752315SN/A 57610379Sandreas.hansson@arm.com void advancePC(const Fault &fault); 5778733Sgeoffrey.blake@arm.com 5782732Sktlim@umich.edu void verify(DynInstPtr &inst); 5792315SN/A 5802315SN/A void validateInst(DynInstPtr &inst); 5812315SN/A void validateExecution(DynInstPtr &inst); 5822315SN/A void validateState(); 5832315SN/A 58412107SRekai.GonzalezAlberquilla@arm.com void copyResult(DynInstPtr &inst, const InstResult& mismatch_val, 58512107SRekai.GonzalezAlberquilla@arm.com int start_idx); 5868733Sgeoffrey.blake@arm.com void handlePendingInt(); 5872732Sktlim@umich.edu 5882732Sktlim@umich.edu private: 5892732Sktlim@umich.edu void handleError(DynInstPtr &inst) 5902732Sktlim@umich.edu { 5912360SN/A if (exitOnError) { 5922732Sktlim@umich.edu dumpAndExit(inst); 5932360SN/A } else if (updateOnError) { 5942354SN/A updateThisCycle = true; 5952360SN/A } 5962732Sktlim@umich.edu } 5972732Sktlim@umich.edu 5982732Sktlim@umich.edu void dumpAndExit(DynInstPtr &inst); 5992732Sktlim@umich.edu 6002354SN/A bool updateThisCycle; 6012354SN/A 6022354SN/A DynInstPtr unverifiedInst; 6032354SN/A 6042315SN/A std::list<DynInstPtr> instList; 6052315SN/A typedef typename std::list<DynInstPtr>::iterator InstListIt; 6062315SN/A void dumpInsts(); 6072315SN/A}; 6082315SN/A 6092315SN/A#endif // __CPU_CHECKER_CPU_HH__ 610