cpu.hh revision 10698
12315SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2011 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152332SN/A * Copyright (c) 2006 The Regents of The University of Michigan 162315SN/A * All rights reserved. 172315SN/A * 182315SN/A * Redistribution and use in source and binary forms, with or without 192315SN/A * modification, are permitted provided that the following conditions are 202315SN/A * met: redistributions of source code must retain the above copyright 212315SN/A * notice, this list of conditions and the following disclaimer; 222315SN/A * redistributions in binary form must reproduce the above copyright 232315SN/A * notice, this list of conditions and the following disclaimer in the 242315SN/A * documentation and/or other materials provided with the distribution; 252315SN/A * neither the name of the copyright holders nor the names of its 262315SN/A * contributors may be used to endorse or promote products derived from 272315SN/A * this software without specific prior written permission. 282315SN/A * 292315SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302315SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312315SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322315SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332315SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342315SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362315SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372315SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382315SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392315SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Kevin Lim 422315SN/A */ 432315SN/A 442315SN/A#ifndef __CPU_CHECKER_CPU_HH__ 452315SN/A#define __CPU_CHECKER_CPU_HH__ 462315SN/A 472315SN/A#include <list> 488229Snate@binkert.org#include <map> 492315SN/A#include <queue> 502315SN/A 512669Sktlim@umich.edu#include "arch/types.hh" 522315SN/A#include "base/statistics.hh" 532315SN/A#include "cpu/base.hh" 542315SN/A#include "cpu/base_dyn_inst.hh" 5510319SAndreas.Sandberg@ARM.com#include "cpu/exec_context.hh" 568229Snate@binkert.org#include "cpu/pc_event.hh" 572683Sktlim@umich.edu#include "cpu/simple_thread.hh" 582315SN/A#include "cpu/static_inst.hh" 598733Sgeoffrey.blake@arm.com#include "debug/Checker.hh" 608733Sgeoffrey.blake@arm.com#include "params/CheckerCPU.hh" 612315SN/A#include "sim/eventq.hh" 622315SN/A 632315SN/A// forward declarations 643468Sgblack@eecs.umich.edunamespace TheISA 653468Sgblack@eecs.umich.edu{ 666022Sgblack@eecs.umich.edu class TLB; 673468Sgblack@eecs.umich.edu} 682315SN/A 692315SN/Atemplate <class> 702315SN/Aclass BaseDynInst; 712680Sktlim@umich.educlass ThreadContext; 722669Sktlim@umich.educlass Request; 732315SN/A 742350SN/A/** 752350SN/A * CheckerCPU class. Dynamically verifies instructions as they are 762350SN/A * completed by making sure that the instruction and its results match 772350SN/A * the independent execution of the benchmark inside the checker. The 782350SN/A * checker verifies instructions in order, regardless of the order in 792350SN/A * which instructions complete. There are certain results that can 802350SN/A * not be verified, specifically the result of a store conditional or 812350SN/A * the values of uncached accesses. In these cases, and with 822350SN/A * instructions marked as "IsUnverifiable", the checker assumes that 832350SN/A * the value from the main CPU's execution is correct and simply 842680Sktlim@umich.edu * copies that value. It provides a CheckerThreadContext (see 852683Sktlim@umich.edu * checker/thread_context.hh) that provides hooks for updating the 862680Sktlim@umich.edu * Checker's state through any ThreadContext accesses. This allows the 872350SN/A * checker to be able to correctly verify instructions, even with 882680Sktlim@umich.edu * external accesses to the ThreadContext that change state. 892350SN/A */ 9010319SAndreas.Sandberg@ARM.comclass CheckerCPU : public BaseCPU, public ExecContext 912315SN/A{ 922315SN/A protected: 932315SN/A typedef TheISA::MachInst MachInst; 942669Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 952669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 962315SN/A typedef TheISA::MiscReg MiscReg; 978832SAli.Saidi@ARM.com 988832SAli.Saidi@ARM.com /** id attached to all issued requests */ 998832SAli.Saidi@ARM.com MasterID masterId; 1002315SN/A public: 1012315SN/A virtual void init(); 1022315SN/A 1035529Snate@binkert.org typedef CheckerCPUParams Params; 1042315SN/A CheckerCPU(Params *p); 1052315SN/A virtual ~CheckerCPU(); 1062315SN/A 1072315SN/A void setSystem(System *system); 1082315SN/A 1099608Sandreas.hansson@arm.com void setIcachePort(MasterPort *icache_port); 1102679Sktlim@umich.edu 1119608Sandreas.hansson@arm.com void setDcachePort(MasterPort *dcache_port); 1122679Sktlim@umich.edu 1139608Sandreas.hansson@arm.com MasterPort &getDataPort() 1148887Sgeoffrey.blake@arm.com { 1159176Sandreas.hansson@arm.com // the checker does not have ports on its own so return the 1169176Sandreas.hansson@arm.com // data port of the actual CPU core 1179176Sandreas.hansson@arm.com assert(dcachePort); 1188887Sgeoffrey.blake@arm.com return *dcachePort; 1198887Sgeoffrey.blake@arm.com } 1208887Sgeoffrey.blake@arm.com 1219608Sandreas.hansson@arm.com MasterPort &getInstPort() 1228887Sgeoffrey.blake@arm.com { 1239176Sandreas.hansson@arm.com // the checker does not have ports on its own so return the 1249176Sandreas.hansson@arm.com // data port of the actual CPU core 1259176Sandreas.hansson@arm.com assert(icachePort); 1268887Sgeoffrey.blake@arm.com return *icachePort; 1278887Sgeoffrey.blake@arm.com } 1282679Sktlim@umich.edu 1299176Sandreas.hansson@arm.com protected: 1309176Sandreas.hansson@arm.com 1319176Sandreas.hansson@arm.com std::vector<Process*> workload; 1329176Sandreas.hansson@arm.com 1339176Sandreas.hansson@arm.com System *systemPtr; 1349176Sandreas.hansson@arm.com 1359608Sandreas.hansson@arm.com MasterPort *icachePort; 1369608Sandreas.hansson@arm.com MasterPort *dcachePort; 1372315SN/A 1382680Sktlim@umich.edu ThreadContext *tc; 1392315SN/A 1406022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1416022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1422315SN/A 1432315SN/A Addr dbg_vtophys(Addr addr); 1442315SN/A 1452315SN/A union Result { 1462315SN/A uint64_t integer; 1472315SN/A double dbl; 1488733Sgeoffrey.blake@arm.com void set(uint64_t i) { integer = i; } 1498733Sgeoffrey.blake@arm.com void set(double d) { dbl = d; } 1508733Sgeoffrey.blake@arm.com void get(uint64_t& i) { i = integer; } 1518733Sgeoffrey.blake@arm.com void get(double& d) { d = dbl; } 1522315SN/A }; 1532315SN/A 1548733Sgeoffrey.blake@arm.com // ISAs like ARM can have multiple destination registers to check, 1558733Sgeoffrey.blake@arm.com // keep them all in a std::queue 1568733Sgeoffrey.blake@arm.com std::queue<Result> result; 1572315SN/A 1582679Sktlim@umich.edu // Pointer to the one memory request. 1592679Sktlim@umich.edu RequestPtr memReq; 1602315SN/A 1612315SN/A StaticInstPtr curStaticInst; 1628733Sgeoffrey.blake@arm.com StaticInstPtr curMacroStaticInst; 1632315SN/A 1642315SN/A // number of simulated instructions 1652315SN/A Counter numInst; 1662315SN/A Counter startNumInst; 1672315SN/A 1682315SN/A std::queue<int> miscRegIdxs; 1692315SN/A 1709176Sandreas.hansson@arm.com public: 1719176Sandreas.hansson@arm.com 1729176Sandreas.hansson@arm.com // Primary thread being run. 1739176Sandreas.hansson@arm.com SimpleThread *thread; 1749176Sandreas.hansson@arm.com 1758733Sgeoffrey.blake@arm.com TheISA::TLB* getITBPtr() { return itb; } 1768733Sgeoffrey.blake@arm.com TheISA::TLB* getDTBPtr() { return dtb; } 1778733Sgeoffrey.blake@arm.com 1788887Sgeoffrey.blake@arm.com virtual Counter totalInsts() const 1798887Sgeoffrey.blake@arm.com { 1808887Sgeoffrey.blake@arm.com return 0; 1818887Sgeoffrey.blake@arm.com } 1828887Sgeoffrey.blake@arm.com 1838887Sgeoffrey.blake@arm.com virtual Counter totalOps() const 1842315SN/A { 1852930Sktlim@umich.edu return 0; 1862315SN/A } 1872315SN/A 1882315SN/A // number of simulated loads 1892315SN/A Counter numLoad; 1902315SN/A Counter startNumLoad; 1912315SN/A 1922315SN/A virtual void serialize(std::ostream &os); 1932315SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1942315SN/A 1952315SN/A // These functions are only used in CPU models that split 1962315SN/A // effective address computation from the actual memory access. 1972315SN/A void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } 19810319SAndreas.Sandberg@ARM.com Addr getEA() const { panic("SimpleCPU::getEA() not implemented\n"); } 1992315SN/A 2002315SN/A // The register accessor methods provide the index of the 2012315SN/A // instruction's operand (e.g., 0 or 1), not the architectural 2022315SN/A // register index, to simplify the implementation of register 2032315SN/A // renaming. We find the architectural register index by indexing 2042315SN/A // into the instruction's own operand index table. Note that a 2052315SN/A // raw pointer to the StaticInst is provided instead of a 2062315SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 2072315SN/A // long as these methods don't copy the pointer into any long-term 2082315SN/A // storage (which is pretty hard to imagine they would have reason 2092315SN/A // to do). 2102315SN/A 21110319SAndreas.Sandberg@ARM.com IntReg readIntRegOperand(const StaticInst *si, int idx) 2122315SN/A { 2132683Sktlim@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 2142315SN/A } 2152315SN/A 2163735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx) 2172315SN/A { 2189918Ssteve.reinhardt@amd.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; 2192683Sktlim@umich.edu return thread->readFloatReg(reg_idx); 2202315SN/A } 2212315SN/A 2223735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 2232669Sktlim@umich.edu { 2249918Ssteve.reinhardt@amd.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; 2252683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx); 2262315SN/A } 2272315SN/A 22810319SAndreas.Sandberg@ARM.com CCReg readCCRegOperand(const StaticInst *si, int idx) 2299920Syasuko.eckert@amd.com { 2309920Syasuko.eckert@amd.com int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base; 2319920Syasuko.eckert@amd.com return thread->readCCReg(reg_idx); 2329920Syasuko.eckert@amd.com } 2339920Syasuko.eckert@amd.com 2348733Sgeoffrey.blake@arm.com template <class T> 2358733Sgeoffrey.blake@arm.com void setResult(T t) 2368733Sgeoffrey.blake@arm.com { 2378733Sgeoffrey.blake@arm.com Result instRes; 2388733Sgeoffrey.blake@arm.com instRes.set(t); 2398733Sgeoffrey.blake@arm.com result.push(instRes); 2408733Sgeoffrey.blake@arm.com } 2418733Sgeoffrey.blake@arm.com 24210319SAndreas.Sandberg@ARM.com void setIntRegOperand(const StaticInst *si, int idx, IntReg val) 2432315SN/A { 2442683Sktlim@umich.edu thread->setIntReg(si->destRegIdx(idx), val); 2458733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 2462315SN/A } 2472315SN/A 2483735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 2492669Sktlim@umich.edu { 2509918Ssteve.reinhardt@amd.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; 2512683Sktlim@umich.edu thread->setFloatReg(reg_idx, val); 2528733Sgeoffrey.blake@arm.com setResult<double>(val); 2532315SN/A } 2542315SN/A 2553735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 2563735Sstever@eecs.umich.edu FloatRegBits val) 2572315SN/A { 2589918Ssteve.reinhardt@amd.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; 2592683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val); 2608733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 2612315SN/A } 2622315SN/A 26310319SAndreas.Sandberg@ARM.com void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 2649920Syasuko.eckert@amd.com { 2659920Syasuko.eckert@amd.com int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base; 2669920Syasuko.eckert@amd.com thread->setCCReg(reg_idx, val); 2679920Syasuko.eckert@amd.com setResult<uint64_t>(val); 2689920Syasuko.eckert@amd.com } 2699920Syasuko.eckert@amd.com 2708733Sgeoffrey.blake@arm.com bool readPredicate() { return thread->readPredicate(); } 2718733Sgeoffrey.blake@arm.com void setPredicate(bool val) 2728733Sgeoffrey.blake@arm.com { 2738733Sgeoffrey.blake@arm.com thread->setPredicate(val); 2748733Sgeoffrey.blake@arm.com } 2752669Sktlim@umich.edu 27610319SAndreas.Sandberg@ARM.com TheISA::PCState pcState() const { return thread->pcState(); } 2778733Sgeoffrey.blake@arm.com void pcState(const TheISA::PCState &val) 2788733Sgeoffrey.blake@arm.com { 2798733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Changing PC to %s, old PC %s.\n", 2808733Sgeoffrey.blake@arm.com val, thread->pcState()); 2818733Sgeoffrey.blake@arm.com thread->pcState(val); 2828733Sgeoffrey.blake@arm.com } 2838733Sgeoffrey.blake@arm.com Addr instAddr() { return thread->instAddr(); } 2848733Sgeoffrey.blake@arm.com Addr nextInstAddr() { return thread->nextInstAddr(); } 2858733Sgeoffrey.blake@arm.com MicroPC microPC() { return thread->microPC(); } 2868733Sgeoffrey.blake@arm.com ////////////////////////////////////////// 2872315SN/A 28810698Sandreas.hansson@arm.com MiscReg readMiscRegNoEffect(int misc_reg) const 2894172Ssaidi@eecs.umich.edu { 2904172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 2914172Ssaidi@eecs.umich.edu } 2924172Ssaidi@eecs.umich.edu 2932315SN/A MiscReg readMiscReg(int misc_reg) 2942315SN/A { 2952683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 2962315SN/A } 2972315SN/A 2984172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 2992315SN/A { 30010034SGeoffrey.Blake@arm.com DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n", misc_reg); 3014172Ssaidi@eecs.umich.edu miscRegIdxs.push(misc_reg); 3024172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(misc_reg, val); 3032315SN/A } 3042315SN/A 3053468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 3062315SN/A { 30710034SGeoffrey.Blake@arm.com DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg); 3082315SN/A miscRegIdxs.push(misc_reg); 3092683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 3102315SN/A } 3112315SN/A 3128733Sgeoffrey.blake@arm.com MiscReg readMiscRegOperand(const StaticInst *si, int idx) 3138733Sgeoffrey.blake@arm.com { 3149918Ssteve.reinhardt@amd.com int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base; 3158733Sgeoffrey.blake@arm.com return thread->readMiscReg(reg_idx); 3168733Sgeoffrey.blake@arm.com } 3178733Sgeoffrey.blake@arm.com 3188733Sgeoffrey.blake@arm.com void setMiscRegOperand( 3198733Sgeoffrey.blake@arm.com const StaticInst *si, int idx, const MiscReg &val) 3208733Sgeoffrey.blake@arm.com { 3219918Ssteve.reinhardt@amd.com int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base; 32210034SGeoffrey.Blake@arm.com return this->setMiscReg(reg_idx, val); 3238733Sgeoffrey.blake@arm.com } 3248888Sgeoffrey.blake@arm.com 3258888Sgeoffrey.blake@arm.com#if THE_ISA == MIPS_ISA 32610319SAndreas.Sandberg@ARM.com MiscReg readRegOtherThread(int misc_reg, ThreadID tid) 3278888Sgeoffrey.blake@arm.com { 3288888Sgeoffrey.blake@arm.com panic("MIPS MT not defined for CheckerCPU.\n"); 3298888Sgeoffrey.blake@arm.com return 0; 3308888Sgeoffrey.blake@arm.com } 3318888Sgeoffrey.blake@arm.com 33210319SAndreas.Sandberg@ARM.com void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid) 3338888Sgeoffrey.blake@arm.com { 3348888Sgeoffrey.blake@arm.com panic("MIPS MT not defined for CheckerCPU.\n"); 3358888Sgeoffrey.blake@arm.com } 3368888Sgeoffrey.blake@arm.com#endif 3378888Sgeoffrey.blake@arm.com 3388733Sgeoffrey.blake@arm.com ///////////////////////////////////////// 3398733Sgeoffrey.blake@arm.com 3408733Sgeoffrey.blake@arm.com void recordPCChange(const TheISA::PCState &val) 3418733Sgeoffrey.blake@arm.com { 3428733Sgeoffrey.blake@arm.com changedPC = true; 3438733Sgeoffrey.blake@arm.com newPCState = val; 3448733Sgeoffrey.blake@arm.com } 3452315SN/A 3465358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 3475358Sgblack@eecs.umich.edu { 3485358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3495358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3505358Sgblack@eecs.umich.edu } 3515358Sgblack@eecs.umich.edu 35210529Smorr@cs.wisc.edu // monitor/mwait funtions 35310529Smorr@cs.wisc.edu virtual void armMonitor(Addr address) { BaseCPU::armMonitor(address); } 35410529Smorr@cs.wisc.edu bool mwait(PacketPtr pkt) { return BaseCPU::mwait(pkt); } 35510529Smorr@cs.wisc.edu void mwaitAtomic(ThreadContext *tc) 35610529Smorr@cs.wisc.edu { return BaseCPU::mwaitAtomic(tc, thread->dtb); } 35710529Smorr@cs.wisc.edu AddressMonitor *getAddrMonitor() { return BaseCPU::getCpuAddrMonitor(); } 35810529Smorr@cs.wisc.edu 3595358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 3605358Sgblack@eecs.umich.edu { 3615358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3625358Sgblack@eecs.umich.edu } 3635358Sgblack@eecs.umich.edu 3645358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 3655358Sgblack@eecs.umich.edu { 3665358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3675358Sgblack@eecs.umich.edu } 3685358Sgblack@eecs.umich.edu 3698733Sgeoffrey.blake@arm.com Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 3708733Sgeoffrey.blake@arm.com Fault writeMem(uint8_t *data, unsigned size, 3718733Sgeoffrey.blake@arm.com Addr addr, unsigned flags, uint64_t *res); 3728733Sgeoffrey.blake@arm.com 37310319SAndreas.Sandberg@ARM.com unsigned int readStCondFailures() const { 37410319SAndreas.Sandberg@ARM.com return thread->readStCondFailures(); 37510319SAndreas.Sandberg@ARM.com } 37610319SAndreas.Sandberg@ARM.com 37710319SAndreas.Sandberg@ARM.com void setStCondFailures(unsigned int sc_failures) 3788733Sgeoffrey.blake@arm.com {} 3798733Sgeoffrey.blake@arm.com ///////////////////////////////////////////////////// 3808733Sgeoffrey.blake@arm.com 3815702Ssaidi@eecs.umich.edu Fault hwrei() { return thread->hwrei(); } 3825702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 3838733Sgeoffrey.blake@arm.com void wakeup() { } 3842315SN/A // Assume that the normal CPU's call to syscall was successful. 3852332SN/A // The checker's state would have already been updated by the syscall. 38610319SAndreas.Sandberg@ARM.com void syscall(int64_t callnum) { } 3872315SN/A 3882315SN/A void handleError() 3892315SN/A { 3902315SN/A if (exitOnError) 3912732Sktlim@umich.edu dumpAndExit(); 3922315SN/A } 3932732Sktlim@umich.edu 3948733Sgeoffrey.blake@arm.com bool checkFlags(Request *unverified_req, Addr vAddr, 3958733Sgeoffrey.blake@arm.com Addr pAddr, int flags); 3962315SN/A 3972732Sktlim@umich.edu void dumpAndExit(); 3982732Sktlim@umich.edu 3992680Sktlim@umich.edu ThreadContext *tcBase() { return tc; } 4002683Sktlim@umich.edu SimpleThread *threadBase() { return thread; } 4012315SN/A 4022315SN/A Result unverifiedResult; 4032669Sktlim@umich.edu Request *unverifiedReq; 4042679Sktlim@umich.edu uint8_t *unverifiedMemData; 4052315SN/A 4062315SN/A bool changedPC; 4072315SN/A bool willChangePC; 4088733Sgeoffrey.blake@arm.com TheISA::PCState newPCState; 4092315SN/A bool exitOnError; 4102354SN/A bool updateOnError; 4112732Sktlim@umich.edu bool warnOnlyOnLoadError; 4122315SN/A 4132315SN/A InstSeqNum youngestSN; 4142315SN/A}; 4152315SN/A 4162350SN/A/** 4172350SN/A * Templated Checker class. This Checker class is templated on the 4182350SN/A * DynInstPtr of the instruction type that will be verified. Proper 4192350SN/A * template instantiations of the Checker must be placed at the bottom 4202350SN/A * of checker/cpu.cc. 4212350SN/A */ 4228733Sgeoffrey.blake@arm.comtemplate <class Impl> 4232315SN/Aclass Checker : public CheckerCPU 4242315SN/A{ 4258733Sgeoffrey.blake@arm.com private: 4268733Sgeoffrey.blake@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 4278733Sgeoffrey.blake@arm.com 4282315SN/A public: 4292315SN/A Checker(Params *p) 4309023Sgblack@eecs.umich.edu : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL) 4312315SN/A { } 4322315SN/A 4332840Sktlim@umich.edu void switchOut(); 4342315SN/A void takeOverFrom(BaseCPU *oldCPU); 4352315SN/A 43610379Sandreas.hansson@arm.com void advancePC(const Fault &fault); 4378733Sgeoffrey.blake@arm.com 4382732Sktlim@umich.edu void verify(DynInstPtr &inst); 4392315SN/A 4402315SN/A void validateInst(DynInstPtr &inst); 4412315SN/A void validateExecution(DynInstPtr &inst); 4422315SN/A void validateState(); 4432315SN/A 4448733Sgeoffrey.blake@arm.com void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx); 4458733Sgeoffrey.blake@arm.com void handlePendingInt(); 4462732Sktlim@umich.edu 4472732Sktlim@umich.edu private: 4482732Sktlim@umich.edu void handleError(DynInstPtr &inst) 4492732Sktlim@umich.edu { 4502360SN/A if (exitOnError) { 4512732Sktlim@umich.edu dumpAndExit(inst); 4522360SN/A } else if (updateOnError) { 4532354SN/A updateThisCycle = true; 4542360SN/A } 4552732Sktlim@umich.edu } 4562732Sktlim@umich.edu 4572732Sktlim@umich.edu void dumpAndExit(DynInstPtr &inst); 4582732Sktlim@umich.edu 4592354SN/A bool updateThisCycle; 4602354SN/A 4612354SN/A DynInstPtr unverifiedInst; 4622354SN/A 4632315SN/A std::list<DynInstPtr> instList; 4642315SN/A typedef typename std::list<DynInstPtr>::iterator InstListIt; 4652315SN/A void dumpInsts(); 4662315SN/A}; 4672315SN/A 4682315SN/A#endif // __CPU_CHECKER_CPU_HH__ 469