cpu.hh revision 10034
12315SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2011 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152332SN/A * Copyright (c) 2006 The Regents of The University of Michigan 162315SN/A * All rights reserved. 172315SN/A * 182315SN/A * Redistribution and use in source and binary forms, with or without 192315SN/A * modification, are permitted provided that the following conditions are 202315SN/A * met: redistributions of source code must retain the above copyright 212315SN/A * notice, this list of conditions and the following disclaimer; 222315SN/A * redistributions in binary form must reproduce the above copyright 232315SN/A * notice, this list of conditions and the following disclaimer in the 242315SN/A * documentation and/or other materials provided with the distribution; 252315SN/A * neither the name of the copyright holders nor the names of its 262315SN/A * contributors may be used to endorse or promote products derived from 272315SN/A * this software without specific prior written permission. 282315SN/A * 292315SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302315SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312315SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322315SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332315SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342315SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362315SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372315SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382315SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392315SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Kevin Lim 422315SN/A */ 432315SN/A 442315SN/A#ifndef __CPU_CHECKER_CPU_HH__ 452315SN/A#define __CPU_CHECKER_CPU_HH__ 462315SN/A 472315SN/A#include <list> 488229Snate@binkert.org#include <map> 492315SN/A#include <queue> 502315SN/A 512669Sktlim@umich.edu#include "arch/types.hh" 522315SN/A#include "base/statistics.hh" 532315SN/A#include "cpu/base.hh" 542315SN/A#include "cpu/base_dyn_inst.hh" 558229Snate@binkert.org#include "cpu/pc_event.hh" 562683Sktlim@umich.edu#include "cpu/simple_thread.hh" 572315SN/A#include "cpu/static_inst.hh" 588733Sgeoffrey.blake@arm.com#include "debug/Checker.hh" 598733Sgeoffrey.blake@arm.com#include "params/CheckerCPU.hh" 602315SN/A#include "sim/eventq.hh" 612315SN/A 622315SN/A// forward declarations 633468Sgblack@eecs.umich.edunamespace TheISA 643468Sgblack@eecs.umich.edu{ 656022Sgblack@eecs.umich.edu class TLB; 663468Sgblack@eecs.umich.edu} 672315SN/A 682315SN/Atemplate <class> 692315SN/Aclass BaseDynInst; 702680Sktlim@umich.educlass ThreadContext; 712669Sktlim@umich.educlass Request; 722315SN/A 732350SN/A/** 742350SN/A * CheckerCPU class. Dynamically verifies instructions as they are 752350SN/A * completed by making sure that the instruction and its results match 762350SN/A * the independent execution of the benchmark inside the checker. The 772350SN/A * checker verifies instructions in order, regardless of the order in 782350SN/A * which instructions complete. There are certain results that can 792350SN/A * not be verified, specifically the result of a store conditional or 802350SN/A * the values of uncached accesses. In these cases, and with 812350SN/A * instructions marked as "IsUnverifiable", the checker assumes that 822350SN/A * the value from the main CPU's execution is correct and simply 832680Sktlim@umich.edu * copies that value. It provides a CheckerThreadContext (see 842683Sktlim@umich.edu * checker/thread_context.hh) that provides hooks for updating the 852680Sktlim@umich.edu * Checker's state through any ThreadContext accesses. This allows the 862350SN/A * checker to be able to correctly verify instructions, even with 872680Sktlim@umich.edu * external accesses to the ThreadContext that change state. 882350SN/A */ 892315SN/Aclass CheckerCPU : public BaseCPU 902315SN/A{ 912315SN/A protected: 922315SN/A typedef TheISA::MachInst MachInst; 932669Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 942669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 952315SN/A typedef TheISA::MiscReg MiscReg; 968832SAli.Saidi@ARM.com 978832SAli.Saidi@ARM.com /** id attached to all issued requests */ 988832SAli.Saidi@ARM.com MasterID masterId; 992315SN/A public: 1002315SN/A virtual void init(); 1012315SN/A 1025529Snate@binkert.org typedef CheckerCPUParams Params; 1032315SN/A CheckerCPU(Params *p); 1042315SN/A virtual ~CheckerCPU(); 1052315SN/A 1062315SN/A void setSystem(System *system); 1072315SN/A 1089608Sandreas.hansson@arm.com void setIcachePort(MasterPort *icache_port); 1092679Sktlim@umich.edu 1109608Sandreas.hansson@arm.com void setDcachePort(MasterPort *dcache_port); 1112679Sktlim@umich.edu 1129608Sandreas.hansson@arm.com MasterPort &getDataPort() 1138887Sgeoffrey.blake@arm.com { 1149176Sandreas.hansson@arm.com // the checker does not have ports on its own so return the 1159176Sandreas.hansson@arm.com // data port of the actual CPU core 1169176Sandreas.hansson@arm.com assert(dcachePort); 1178887Sgeoffrey.blake@arm.com return *dcachePort; 1188887Sgeoffrey.blake@arm.com } 1198887Sgeoffrey.blake@arm.com 1209608Sandreas.hansson@arm.com MasterPort &getInstPort() 1218887Sgeoffrey.blake@arm.com { 1229176Sandreas.hansson@arm.com // the checker does not have ports on its own so return the 1239176Sandreas.hansson@arm.com // data port of the actual CPU core 1249176Sandreas.hansson@arm.com assert(icachePort); 1258887Sgeoffrey.blake@arm.com return *icachePort; 1268887Sgeoffrey.blake@arm.com } 1272679Sktlim@umich.edu 1289176Sandreas.hansson@arm.com protected: 1299176Sandreas.hansson@arm.com 1309176Sandreas.hansson@arm.com std::vector<Process*> workload; 1319176Sandreas.hansson@arm.com 1329176Sandreas.hansson@arm.com System *systemPtr; 1339176Sandreas.hansson@arm.com 1349608Sandreas.hansson@arm.com MasterPort *icachePort; 1359608Sandreas.hansson@arm.com MasterPort *dcachePort; 1362315SN/A 1372680Sktlim@umich.edu ThreadContext *tc; 1382315SN/A 1396022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1406022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1412315SN/A 1422315SN/A Addr dbg_vtophys(Addr addr); 1432315SN/A 1442315SN/A union Result { 1452315SN/A uint64_t integer; 1462315SN/A double dbl; 1478733Sgeoffrey.blake@arm.com void set(uint64_t i) { integer = i; } 1488733Sgeoffrey.blake@arm.com void set(double d) { dbl = d; } 1498733Sgeoffrey.blake@arm.com void get(uint64_t& i) { i = integer; } 1508733Sgeoffrey.blake@arm.com void get(double& d) { d = dbl; } 1512315SN/A }; 1522315SN/A 1538733Sgeoffrey.blake@arm.com // ISAs like ARM can have multiple destination registers to check, 1548733Sgeoffrey.blake@arm.com // keep them all in a std::queue 1558733Sgeoffrey.blake@arm.com std::queue<Result> result; 1562315SN/A 1572679Sktlim@umich.edu // Pointer to the one memory request. 1582679Sktlim@umich.edu RequestPtr memReq; 1592315SN/A 1602315SN/A StaticInstPtr curStaticInst; 1618733Sgeoffrey.blake@arm.com StaticInstPtr curMacroStaticInst; 1622315SN/A 1632315SN/A // number of simulated instructions 1642315SN/A Counter numInst; 1652315SN/A Counter startNumInst; 1662315SN/A 1672315SN/A std::queue<int> miscRegIdxs; 1682315SN/A 1699176Sandreas.hansson@arm.com public: 1709176Sandreas.hansson@arm.com 1719176Sandreas.hansson@arm.com // Primary thread being run. 1729176Sandreas.hansson@arm.com SimpleThread *thread; 1739176Sandreas.hansson@arm.com 1748733Sgeoffrey.blake@arm.com TheISA::TLB* getITBPtr() { return itb; } 1758733Sgeoffrey.blake@arm.com TheISA::TLB* getDTBPtr() { return dtb; } 1768733Sgeoffrey.blake@arm.com 1778887Sgeoffrey.blake@arm.com virtual Counter totalInsts() const 1788887Sgeoffrey.blake@arm.com { 1798887Sgeoffrey.blake@arm.com return 0; 1808887Sgeoffrey.blake@arm.com } 1818887Sgeoffrey.blake@arm.com 1828887Sgeoffrey.blake@arm.com virtual Counter totalOps() const 1832315SN/A { 1842930Sktlim@umich.edu return 0; 1852315SN/A } 1862315SN/A 1872315SN/A // number of simulated loads 1882315SN/A Counter numLoad; 1892315SN/A Counter startNumLoad; 1902315SN/A 1912315SN/A virtual void serialize(std::ostream &os); 1922315SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1932315SN/A 1942315SN/A // These functions are only used in CPU models that split 1952315SN/A // effective address computation from the actual memory access. 1962315SN/A void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } 1975543Ssaidi@eecs.umich.edu Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); } 1982315SN/A 1992315SN/A // The register accessor methods provide the index of the 2002315SN/A // instruction's operand (e.g., 0 or 1), not the architectural 2012315SN/A // register index, to simplify the implementation of register 2022315SN/A // renaming. We find the architectural register index by indexing 2032315SN/A // into the instruction's own operand index table. Note that a 2042315SN/A // raw pointer to the StaticInst is provided instead of a 2052315SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 2062315SN/A // long as these methods don't copy the pointer into any long-term 2072315SN/A // storage (which is pretty hard to imagine they would have reason 2082315SN/A // to do). 2092315SN/A 2103735Sstever@eecs.umich.edu uint64_t readIntRegOperand(const StaticInst *si, int idx) 2112315SN/A { 2122683Sktlim@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 2132315SN/A } 2142315SN/A 2153735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx) 2162315SN/A { 2179918Ssteve.reinhardt@amd.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; 2182683Sktlim@umich.edu return thread->readFloatReg(reg_idx); 2192315SN/A } 2202315SN/A 2213735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 2222669Sktlim@umich.edu { 2239918Ssteve.reinhardt@amd.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; 2242683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx); 2252315SN/A } 2262315SN/A 2279920Syasuko.eckert@amd.com uint64_t readCCRegOperand(const StaticInst *si, int idx) 2289920Syasuko.eckert@amd.com { 2299920Syasuko.eckert@amd.com int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base; 2309920Syasuko.eckert@amd.com return thread->readCCReg(reg_idx); 2319920Syasuko.eckert@amd.com } 2329920Syasuko.eckert@amd.com 2338733Sgeoffrey.blake@arm.com template <class T> 2348733Sgeoffrey.blake@arm.com void setResult(T t) 2358733Sgeoffrey.blake@arm.com { 2368733Sgeoffrey.blake@arm.com Result instRes; 2378733Sgeoffrey.blake@arm.com instRes.set(t); 2388733Sgeoffrey.blake@arm.com result.push(instRes); 2398733Sgeoffrey.blake@arm.com } 2408733Sgeoffrey.blake@arm.com 2413735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 2422315SN/A { 2432683Sktlim@umich.edu thread->setIntReg(si->destRegIdx(idx), val); 2448733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 2452315SN/A } 2462315SN/A 2473735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 2482669Sktlim@umich.edu { 2499918Ssteve.reinhardt@amd.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; 2502683Sktlim@umich.edu thread->setFloatReg(reg_idx, val); 2518733Sgeoffrey.blake@arm.com setResult<double>(val); 2522315SN/A } 2532315SN/A 2543735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 2553735Sstever@eecs.umich.edu FloatRegBits val) 2562315SN/A { 2579918Ssteve.reinhardt@amd.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; 2582683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val); 2598733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 2602315SN/A } 2612315SN/A 2629920Syasuko.eckert@amd.com void setCCRegOperand(const StaticInst *si, int idx, uint64_t val) 2639920Syasuko.eckert@amd.com { 2649920Syasuko.eckert@amd.com int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base; 2659920Syasuko.eckert@amd.com thread->setCCReg(reg_idx, val); 2669920Syasuko.eckert@amd.com setResult<uint64_t>(val); 2679920Syasuko.eckert@amd.com } 2689920Syasuko.eckert@amd.com 2698733Sgeoffrey.blake@arm.com bool readPredicate() { return thread->readPredicate(); } 2708733Sgeoffrey.blake@arm.com void setPredicate(bool val) 2718733Sgeoffrey.blake@arm.com { 2728733Sgeoffrey.blake@arm.com thread->setPredicate(val); 2738733Sgeoffrey.blake@arm.com } 2742669Sktlim@umich.edu 2758733Sgeoffrey.blake@arm.com TheISA::PCState pcState() { return thread->pcState(); } 2768733Sgeoffrey.blake@arm.com void pcState(const TheISA::PCState &val) 2778733Sgeoffrey.blake@arm.com { 2788733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Changing PC to %s, old PC %s.\n", 2798733Sgeoffrey.blake@arm.com val, thread->pcState()); 2808733Sgeoffrey.blake@arm.com thread->pcState(val); 2818733Sgeoffrey.blake@arm.com } 2828733Sgeoffrey.blake@arm.com Addr instAddr() { return thread->instAddr(); } 2838733Sgeoffrey.blake@arm.com Addr nextInstAddr() { return thread->nextInstAddr(); } 2848733Sgeoffrey.blake@arm.com MicroPC microPC() { return thread->microPC(); } 2858733Sgeoffrey.blake@arm.com ////////////////////////////////////////// 2862315SN/A 2874172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 2884172Ssaidi@eecs.umich.edu { 2894172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 2904172Ssaidi@eecs.umich.edu } 2914172Ssaidi@eecs.umich.edu 2922315SN/A MiscReg readMiscReg(int misc_reg) 2932315SN/A { 2942683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 2952315SN/A } 2962315SN/A 2974172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 2982315SN/A { 29910034SGeoffrey.Blake@arm.com DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n", misc_reg); 3004172Ssaidi@eecs.umich.edu miscRegIdxs.push(misc_reg); 3014172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(misc_reg, val); 3022315SN/A } 3032315SN/A 3043468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 3052315SN/A { 30610034SGeoffrey.Blake@arm.com DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg); 3072315SN/A miscRegIdxs.push(misc_reg); 3082683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 3092315SN/A } 3102315SN/A 3118733Sgeoffrey.blake@arm.com MiscReg readMiscRegOperand(const StaticInst *si, int idx) 3128733Sgeoffrey.blake@arm.com { 3139918Ssteve.reinhardt@amd.com int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base; 3148733Sgeoffrey.blake@arm.com return thread->readMiscReg(reg_idx); 3158733Sgeoffrey.blake@arm.com } 3168733Sgeoffrey.blake@arm.com 3178733Sgeoffrey.blake@arm.com void setMiscRegOperand( 3188733Sgeoffrey.blake@arm.com const StaticInst *si, int idx, const MiscReg &val) 3198733Sgeoffrey.blake@arm.com { 3209918Ssteve.reinhardt@amd.com int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base; 32110034SGeoffrey.Blake@arm.com return this->setMiscReg(reg_idx, val); 3228733Sgeoffrey.blake@arm.com } 3238888Sgeoffrey.blake@arm.com 3248888Sgeoffrey.blake@arm.com#if THE_ISA == MIPS_ISA 3258888Sgeoffrey.blake@arm.com uint64_t readRegOtherThread(int misc_reg) 3268888Sgeoffrey.blake@arm.com { 3278888Sgeoffrey.blake@arm.com panic("MIPS MT not defined for CheckerCPU.\n"); 3288888Sgeoffrey.blake@arm.com return 0; 3298888Sgeoffrey.blake@arm.com } 3308888Sgeoffrey.blake@arm.com 3318888Sgeoffrey.blake@arm.com void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val) 3328888Sgeoffrey.blake@arm.com { 3338888Sgeoffrey.blake@arm.com panic("MIPS MT not defined for CheckerCPU.\n"); 3348888Sgeoffrey.blake@arm.com } 3358888Sgeoffrey.blake@arm.com#endif 3368888Sgeoffrey.blake@arm.com 3378733Sgeoffrey.blake@arm.com ///////////////////////////////////////// 3388733Sgeoffrey.blake@arm.com 3398733Sgeoffrey.blake@arm.com void recordPCChange(const TheISA::PCState &val) 3408733Sgeoffrey.blake@arm.com { 3418733Sgeoffrey.blake@arm.com changedPC = true; 3428733Sgeoffrey.blake@arm.com newPCState = val; 3438733Sgeoffrey.blake@arm.com } 3442315SN/A 3455358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 3465358Sgblack@eecs.umich.edu { 3475358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3485358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3495358Sgblack@eecs.umich.edu } 3505358Sgblack@eecs.umich.edu 3515358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 3525358Sgblack@eecs.umich.edu { 3535358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3545358Sgblack@eecs.umich.edu } 3555358Sgblack@eecs.umich.edu 3565358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 3575358Sgblack@eecs.umich.edu { 3585358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3595358Sgblack@eecs.umich.edu } 3605358Sgblack@eecs.umich.edu 3618733Sgeoffrey.blake@arm.com Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 3628733Sgeoffrey.blake@arm.com Fault writeMem(uint8_t *data, unsigned size, 3638733Sgeoffrey.blake@arm.com Addr addr, unsigned flags, uint64_t *res); 3648733Sgeoffrey.blake@arm.com 3658733Sgeoffrey.blake@arm.com void setStCondFailures(unsigned sc_failures) 3668733Sgeoffrey.blake@arm.com {} 3678733Sgeoffrey.blake@arm.com ///////////////////////////////////////////////////// 3688733Sgeoffrey.blake@arm.com 3695702Ssaidi@eecs.umich.edu Fault hwrei() { return thread->hwrei(); } 3705702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 3718733Sgeoffrey.blake@arm.com void wakeup() { } 3722315SN/A // Assume that the normal CPU's call to syscall was successful. 3732332SN/A // The checker's state would have already been updated by the syscall. 3742669Sktlim@umich.edu void syscall(uint64_t callnum) { } 3752315SN/A 3762315SN/A void handleError() 3772315SN/A { 3782315SN/A if (exitOnError) 3792732Sktlim@umich.edu dumpAndExit(); 3802315SN/A } 3812732Sktlim@umich.edu 3828733Sgeoffrey.blake@arm.com bool checkFlags(Request *unverified_req, Addr vAddr, 3838733Sgeoffrey.blake@arm.com Addr pAddr, int flags); 3842315SN/A 3852732Sktlim@umich.edu void dumpAndExit(); 3862732Sktlim@umich.edu 3872680Sktlim@umich.edu ThreadContext *tcBase() { return tc; } 3882683Sktlim@umich.edu SimpleThread *threadBase() { return thread; } 3892315SN/A 3902315SN/A Result unverifiedResult; 3912669Sktlim@umich.edu Request *unverifiedReq; 3922679Sktlim@umich.edu uint8_t *unverifiedMemData; 3932315SN/A 3942315SN/A bool changedPC; 3952315SN/A bool willChangePC; 3968733Sgeoffrey.blake@arm.com TheISA::PCState newPCState; 3972315SN/A bool exitOnError; 3982354SN/A bool updateOnError; 3992732Sktlim@umich.edu bool warnOnlyOnLoadError; 4002315SN/A 4012315SN/A InstSeqNum youngestSN; 4022315SN/A}; 4032315SN/A 4042350SN/A/** 4052350SN/A * Templated Checker class. This Checker class is templated on the 4062350SN/A * DynInstPtr of the instruction type that will be verified. Proper 4072350SN/A * template instantiations of the Checker must be placed at the bottom 4082350SN/A * of checker/cpu.cc. 4092350SN/A */ 4108733Sgeoffrey.blake@arm.comtemplate <class Impl> 4112315SN/Aclass Checker : public CheckerCPU 4122315SN/A{ 4138733Sgeoffrey.blake@arm.com private: 4148733Sgeoffrey.blake@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 4158733Sgeoffrey.blake@arm.com 4162315SN/A public: 4172315SN/A Checker(Params *p) 4189023Sgblack@eecs.umich.edu : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL) 4192315SN/A { } 4202315SN/A 4212840Sktlim@umich.edu void switchOut(); 4222315SN/A void takeOverFrom(BaseCPU *oldCPU); 4232315SN/A 4248733Sgeoffrey.blake@arm.com void advancePC(Fault fault); 4258733Sgeoffrey.blake@arm.com 4262732Sktlim@umich.edu void verify(DynInstPtr &inst); 4272315SN/A 4282315SN/A void validateInst(DynInstPtr &inst); 4292315SN/A void validateExecution(DynInstPtr &inst); 4302315SN/A void validateState(); 4312315SN/A 4328733Sgeoffrey.blake@arm.com void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx); 4338733Sgeoffrey.blake@arm.com void handlePendingInt(); 4342732Sktlim@umich.edu 4352732Sktlim@umich.edu private: 4362732Sktlim@umich.edu void handleError(DynInstPtr &inst) 4372732Sktlim@umich.edu { 4382360SN/A if (exitOnError) { 4392732Sktlim@umich.edu dumpAndExit(inst); 4402360SN/A } else if (updateOnError) { 4412354SN/A updateThisCycle = true; 4422360SN/A } 4432732Sktlim@umich.edu } 4442732Sktlim@umich.edu 4452732Sktlim@umich.edu void dumpAndExit(DynInstPtr &inst); 4462732Sktlim@umich.edu 4472354SN/A bool updateThisCycle; 4482354SN/A 4492354SN/A DynInstPtr unverifiedInst; 4502354SN/A 4512315SN/A std::list<DynInstPtr> instList; 4522315SN/A typedef typename std::list<DynInstPtr>::iterator InstListIt; 4532315SN/A void dumpInsts(); 4542315SN/A}; 4552315SN/A 4562315SN/A#endif // __CPU_CHECKER_CPU_HH__ 457