cpu.cc revision 9176
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Geoffrey Blake 42 */ 43 44#include <list> 45#include <string> 46 47#include "arch/kernel_stats.hh" 48#include "arch/vtophys.hh" 49#include "cpu/checker/cpu.hh" 50#include "cpu/base.hh" 51#include "cpu/simple_thread.hh" 52#include "cpu/static_inst.hh" 53#include "cpu/thread_context.hh" 54#include "params/CheckerCPU.hh" 55#include "sim/full_system.hh" 56#include "sim/tlb.hh" 57 58using namespace std; 59using namespace TheISA; 60 61void 62CheckerCPU::init() 63{ 64 masterId = systemPtr->getMasterId(name()); 65} 66 67CheckerCPU::CheckerCPU(Params *p) 68 : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL), 69 tc(NULL), thread(NULL) 70{ 71 memReq = NULL; 72 curStaticInst = NULL; 73 curMacroStaticInst = NULL; 74 75 numInst = 0; 76 startNumInst = 0; 77 numLoad = 0; 78 startNumLoad = 0; 79 youngestSN = 0; 80 81 changedPC = willChangePC = changedNextPC = false; 82 83 exitOnError = p->exitOnError; 84 warnOnlyOnLoadError = p->warnOnlyOnLoadError; 85 itb = p->itb; 86 dtb = p->dtb; 87 workload = p->workload; 88 89 updateOnError = true; 90} 91 92CheckerCPU::~CheckerCPU() 93{ 94} 95 96void 97CheckerCPU::setSystem(System *system) 98{ 99 systemPtr = system; 100 101 if (FullSystem) { 102 thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false); 103 } else { 104 thread = new SimpleThread(this, 0, systemPtr, 105 workload.size() ? workload[0] : NULL, 106 itb, dtb); 107 } 108 109 tc = thread->getTC(); 110 threadContexts.push_back(tc); 111 thread->kernelStats = NULL; 112 // Thread should never be null after this 113 assert(thread != NULL); 114} 115 116void 117CheckerCPU::setIcachePort(CpuPort *icache_port) 118{ 119 icachePort = icache_port; 120} 121 122void 123CheckerCPU::setDcachePort(CpuPort *dcache_port) 124{ 125 dcachePort = dcache_port; 126} 127 128void 129CheckerCPU::serialize(ostream &os) 130{ 131} 132 133void 134CheckerCPU::unserialize(Checkpoint *cp, const string §ion) 135{ 136} 137 138Fault 139CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags) 140{ 141 Fault fault = NoFault; 142 unsigned blockSize = dcachePort->peerBlockSize(); 143 int fullSize = size; 144 Addr secondAddr = roundDown(addr + size - 1, blockSize); 145 bool checked_flags = false; 146 bool flags_match = true; 147 Addr pAddr = 0x0; 148 149 150 if (secondAddr > addr) 151 size = secondAddr - addr; 152 153 // Need to account for multiple accesses like the Atomic and TimingSimple 154 while (1) { 155 memReq = new Request(); 156 memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr()); 157 158 // translate to physical address 159 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read); 160 161 if (!checked_flags && fault == NoFault && unverifiedReq) { 162 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(), 163 memReq->getPaddr(), memReq->getFlags()); 164 pAddr = memReq->getPaddr(); 165 checked_flags = true; 166 } 167 168 // Now do the access 169 if (fault == NoFault && 170 !memReq->getFlags().isSet(Request::NO_ACCESS)) { 171 PacketPtr pkt = new Packet(memReq, 172 memReq->isLLSC() ? 173 MemCmd::LoadLockedReq : 174 MemCmd::ReadReq); 175 176 pkt->dataStatic(data); 177 178 if (!(memReq->isUncacheable() || memReq->isMmappedIpr())) { 179 // Access memory to see if we have the same data 180 dcachePort->sendFunctional(pkt); 181 } else { 182 // Assume the data is correct if it's an uncached access 183 memcpy(data, unverifiedMemData, size); 184 } 185 186 delete memReq; 187 memReq = NULL; 188 delete pkt; 189 } 190 191 if (fault != NoFault) { 192 if (memReq->isPrefetch()) { 193 fault = NoFault; 194 } 195 delete memReq; 196 memReq = NULL; 197 break; 198 } 199 200 if (memReq != NULL) { 201 delete memReq; 202 } 203 204 //If we don't need to access a second cache line, stop now. 205 if (secondAddr <= addr) 206 { 207 break; 208 } 209 210 // Setup for accessing next cache line 211 data += size; 212 unverifiedMemData += size; 213 size = addr + fullSize - secondAddr; 214 addr = secondAddr; 215 } 216 217 if (!flags_match) { 218 warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n", 219 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(), 220 unverifiedReq->getFlags(), addr, pAddr, flags); 221 handleError(); 222 } 223 224 return fault; 225} 226 227Fault 228CheckerCPU::writeMem(uint8_t *data, unsigned size, 229 Addr addr, unsigned flags, uint64_t *res) 230{ 231 Fault fault = NoFault; 232 bool checked_flags = false; 233 bool flags_match = true; 234 Addr pAddr = 0x0; 235 236 unsigned blockSize = dcachePort->peerBlockSize(); 237 int fullSize = size; 238 239 Addr secondAddr = roundDown(addr + size - 1, blockSize); 240 241 if (secondAddr > addr) 242 size = secondAddr - addr; 243 244 // Need to account for a multiple access like Atomic and Timing CPUs 245 while (1) { 246 memReq = new Request(); 247 memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr()); 248 249 // translate to physical address 250 fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write); 251 252 if (!checked_flags && fault == NoFault && unverifiedReq) { 253 flags_match = checkFlags(unverifiedReq, memReq->getVaddr(), 254 memReq->getPaddr(), memReq->getFlags()); 255 pAddr = memReq->getPaddr(); 256 checked_flags = true; 257 } 258 259 /* 260 * We don't actually check memory for the store because there 261 * is no guarantee it has left the lsq yet, and therefore we 262 * can't verify the memory on stores without lsq snooping 263 * enabled. This is left as future work for the Checker: LSQ snooping 264 * and memory validation after stores have committed. 265 */ 266 bool was_prefetch = memReq->isPrefetch(); 267 268 delete memReq; 269 270 //If we don't need to access a second cache line, stop now. 271 if (fault != NoFault || secondAddr <= addr) 272 { 273 if (fault != NoFault && was_prefetch) { 274 fault = NoFault; 275 } 276 break; 277 } 278 279 //Update size and access address 280 size = addr + fullSize - secondAddr; 281 //And access the right address. 282 addr = secondAddr; 283 } 284 285 if (!flags_match) { 286 warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n", 287 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(), 288 unverifiedReq->getFlags(), addr, pAddr, flags); 289 handleError(); 290 } 291 292 // Assume the result was the same as the one passed in. This checker 293 // doesn't check if the SC should succeed or fail, it just checks the 294 // value. 295 if (unverifiedReq && res && unverifiedReq->extraDataValid()) 296 *res = unverifiedReq->getExtraData(); 297 298 // Entire purpose here is to make sure we are getting the 299 // same data to send to the mem system as the CPU did. 300 // Cannot check this is actually what went to memory because 301 // there stores can be in ld/st queue or coherent operations 302 // overwriting values. 303 bool extraData; 304 if (unverifiedReq) { 305 extraData = unverifiedReq->extraDataValid() ? 306 unverifiedReq->getExtraData() : 1; 307 } 308 309 if (unverifiedReq && unverifiedMemData && 310 memcmp(data, unverifiedMemData, fullSize) && extraData) { 311 warn("%lli: Store value does not match value sent to memory!\ 312 data: %#x inst_data: %#x", curTick(), data, 313 unverifiedMemData); 314 handleError(); 315 } 316 317 return fault; 318} 319 320Addr 321CheckerCPU::dbg_vtophys(Addr addr) 322{ 323 return vtophys(tc, addr); 324} 325 326/** 327 * Checks if the flags set by the Checker and Checkee match. 328 */ 329bool 330CheckerCPU::checkFlags(Request *unverified_req, Addr vAddr, 331 Addr pAddr, int flags) 332{ 333 Addr unverifiedVAddr = unverified_req->getVaddr(); 334 Addr unverifiedPAddr = unverified_req->getPaddr(); 335 int unverifiedFlags = unverified_req->getFlags(); 336 337 if (unverifiedVAddr != vAddr || 338 unverifiedPAddr != pAddr || 339 unverifiedFlags != flags) { 340 return false; 341 } 342 343 return true; 344} 345 346void 347CheckerCPU::dumpAndExit() 348{ 349 warn("%lli: Checker PC:%s", 350 curTick(), thread->pcState()); 351 panic("Checker found an error!"); 352} 353