cpu.cc revision 11435
12789Sktlim@umich.edu/* 29814Sandreas.hansson@arm.com * Copyright (c) 2011,2013 ARM Limited 38733Sgeoffrey.blake@arm.com * All rights reserved 48733Sgeoffrey.blake@arm.com * 58733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 68733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 78733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 88733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 98733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 108733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 118733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 128733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 138733Sgeoffrey.blake@arm.com * 142789Sktlim@umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 152789Sktlim@umich.edu * All rights reserved. 162789Sktlim@umich.edu * 172789Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 182789Sktlim@umich.edu * modification, are permitted provided that the following conditions are 192789Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 202789Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 212789Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 222789Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 232789Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 242789Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 252789Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 262789Sktlim@umich.edu * this software without specific prior written permission. 272789Sktlim@umich.edu * 282789Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292789Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302789Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312789Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322789Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332789Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342789Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352789Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362789Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372789Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382789Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392789Sktlim@umich.edu * 402789Sktlim@umich.edu * Authors: Kevin Lim 418733Sgeoffrey.blake@arm.com * Geoffrey Blake 422789Sktlim@umich.edu */ 432789Sktlim@umich.edu 442789Sktlim@umich.edu#include <list> 452789Sktlim@umich.edu#include <string> 462789Sktlim@umich.edu 4710687SAndreas.Sandberg@ARM.com#include "arch/generic/tlb.hh" 488793Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 498793Sgblack@eecs.umich.edu#include "arch/vtophys.hh" 508229Snate@binkert.org#include "cpu/checker/cpu.hh" 512789Sktlim@umich.edu#include "cpu/base.hh" 522789Sktlim@umich.edu#include "cpu/simple_thread.hh" 533348Sbinkertn@umich.edu#include "cpu/static_inst.hh" 542789Sktlim@umich.edu#include "cpu/thread_context.hh" 558733Sgeoffrey.blake@arm.com#include "params/CheckerCPU.hh" 568887Sgeoffrey.blake@arm.com#include "sim/full_system.hh" 572789Sktlim@umich.edu 582789Sktlim@umich.eduusing namespace std; 598733Sgeoffrey.blake@arm.comusing namespace TheISA; 602789Sktlim@umich.edu 612789Sktlim@umich.eduvoid 622789Sktlim@umich.eduCheckerCPU::init() 632789Sktlim@umich.edu{ 648832SAli.Saidi@ARM.com masterId = systemPtr->getMasterId(name()); 652789Sktlim@umich.edu} 662789Sktlim@umich.edu 672789Sktlim@umich.eduCheckerCPU::CheckerCPU(Params *p) 689176Sandreas.hansson@arm.com : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL), 699176Sandreas.hansson@arm.com tc(NULL), thread(NULL) 702789Sktlim@umich.edu{ 712789Sktlim@umich.edu memReq = NULL; 728733Sgeoffrey.blake@arm.com curStaticInst = NULL; 738733Sgeoffrey.blake@arm.com curMacroStaticInst = NULL; 742789Sktlim@umich.edu 752789Sktlim@umich.edu numInst = 0; 762789Sktlim@umich.edu startNumInst = 0; 772789Sktlim@umich.edu numLoad = 0; 782789Sktlim@umich.edu startNumLoad = 0; 792789Sktlim@umich.edu youngestSN = 0; 802789Sktlim@umich.edu 8110034SGeoffrey.Blake@arm.com changedPC = willChangePC = false; 822789Sktlim@umich.edu 832789Sktlim@umich.edu exitOnError = p->exitOnError; 842789Sktlim@umich.edu warnOnlyOnLoadError = p->warnOnlyOnLoadError; 852789Sktlim@umich.edu itb = p->itb; 862789Sktlim@umich.edu dtb = p->dtb; 878733Sgeoffrey.blake@arm.com workload = p->workload; 882789Sktlim@umich.edu 898733Sgeoffrey.blake@arm.com updateOnError = true; 902789Sktlim@umich.edu} 912789Sktlim@umich.edu 922789Sktlim@umich.eduCheckerCPU::~CheckerCPU() 932789Sktlim@umich.edu{ 942789Sktlim@umich.edu} 952789Sktlim@umich.edu 962789Sktlim@umich.eduvoid 972789Sktlim@umich.eduCheckerCPU::setSystem(System *system) 982789Sktlim@umich.edu{ 999384SAndreas.Sandberg@arm.com const Params *p(dynamic_cast<const Params *>(_params)); 1009384SAndreas.Sandberg@arm.com 1012789Sktlim@umich.edu systemPtr = system; 1022789Sktlim@umich.edu 1038887Sgeoffrey.blake@arm.com if (FullSystem) { 1049384SAndreas.Sandberg@arm.com thread = new SimpleThread(this, 0, systemPtr, itb, dtb, 1059384SAndreas.Sandberg@arm.com p->isa[0], false); 1068887Sgeoffrey.blake@arm.com } else { 1078887Sgeoffrey.blake@arm.com thread = new SimpleThread(this, 0, systemPtr, 1088887Sgeoffrey.blake@arm.com workload.size() ? workload[0] : NULL, 1099384SAndreas.Sandberg@arm.com itb, dtb, p->isa[0]); 1108887Sgeoffrey.blake@arm.com } 1112789Sktlim@umich.edu 1122789Sktlim@umich.edu tc = thread->getTC(); 1132789Sktlim@umich.edu threadContexts.push_back(tc); 1142789Sktlim@umich.edu thread->kernelStats = NULL; 1158887Sgeoffrey.blake@arm.com // Thread should never be null after this 1168887Sgeoffrey.blake@arm.com assert(thread != NULL); 1172789Sktlim@umich.edu} 1182789Sktlim@umich.edu 1192789Sktlim@umich.eduvoid 1209608Sandreas.hansson@arm.comCheckerCPU::setIcachePort(MasterPort *icache_port) 1212789Sktlim@umich.edu{ 1222789Sktlim@umich.edu icachePort = icache_port; 1232789Sktlim@umich.edu} 1242789Sktlim@umich.edu 1252789Sktlim@umich.eduvoid 1269608Sandreas.hansson@arm.comCheckerCPU::setDcachePort(MasterPort *dcache_port) 1272789Sktlim@umich.edu{ 1282789Sktlim@umich.edu dcachePort = dcache_port; 1292789Sktlim@umich.edu} 1302789Sktlim@umich.edu 1312789Sktlim@umich.eduvoid 13210905Sandreas.sandberg@arm.comCheckerCPU::serialize(ostream &os) const 1332789Sktlim@umich.edu{ 1342789Sktlim@umich.edu} 1352789Sktlim@umich.edu 1362789Sktlim@umich.eduvoid 13710905Sandreas.sandberg@arm.comCheckerCPU::unserialize(CheckpointIn &cp) 1382789Sktlim@umich.edu{ 1392789Sktlim@umich.edu} 1402789Sktlim@umich.edu 1412789Sktlim@umich.eduFault 1428733Sgeoffrey.blake@arm.comCheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags) 1432789Sktlim@umich.edu{ 1448733Sgeoffrey.blake@arm.com Fault fault = NoFault; 1458733Sgeoffrey.blake@arm.com int fullSize = size; 1469814Sandreas.hansson@arm.com Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 1478733Sgeoffrey.blake@arm.com bool checked_flags = false; 1488733Sgeoffrey.blake@arm.com bool flags_match = true; 1498733Sgeoffrey.blake@arm.com Addr pAddr = 0x0; 1502789Sktlim@umich.edu 1512789Sktlim@umich.edu 1528733Sgeoffrey.blake@arm.com if (secondAddr > addr) 1538733Sgeoffrey.blake@arm.com size = secondAddr - addr; 1542789Sktlim@umich.edu 1558733Sgeoffrey.blake@arm.com // Need to account for multiple accesses like the Atomic and TimingSimple 1568733Sgeoffrey.blake@arm.com while (1) { 15710653Sandreas.hansson@arm.com memReq = new Request(0, addr, size, flags, masterId, 15811435Smitch.hayenga@arm.com thread->pcState().instAddr(), tc->contextId()); 1592789Sktlim@umich.edu 1608733Sgeoffrey.blake@arm.com // translate to physical address 1618733Sgeoffrey.blake@arm.com fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read); 1622789Sktlim@umich.edu 1638733Sgeoffrey.blake@arm.com if (!checked_flags && fault == NoFault && unverifiedReq) { 1648733Sgeoffrey.blake@arm.com flags_match = checkFlags(unverifiedReq, memReq->getVaddr(), 1658733Sgeoffrey.blake@arm.com memReq->getPaddr(), memReq->getFlags()); 1668733Sgeoffrey.blake@arm.com pAddr = memReq->getPaddr(); 1678733Sgeoffrey.blake@arm.com checked_flags = true; 1688733Sgeoffrey.blake@arm.com } 1698733Sgeoffrey.blake@arm.com 1708733Sgeoffrey.blake@arm.com // Now do the access 1718733Sgeoffrey.blake@arm.com if (fault == NoFault && 1728733Sgeoffrey.blake@arm.com !memReq->getFlags().isSet(Request::NO_ACCESS)) { 17310342SCurtis.Dunham@arm.com PacketPtr pkt = Packet::createRead(memReq); 1748733Sgeoffrey.blake@arm.com 1758733Sgeoffrey.blake@arm.com pkt->dataStatic(data); 1768733Sgeoffrey.blake@arm.com 1778733Sgeoffrey.blake@arm.com if (!(memReq->isUncacheable() || memReq->isMmappedIpr())) { 1788733Sgeoffrey.blake@arm.com // Access memory to see if we have the same data 1798733Sgeoffrey.blake@arm.com dcachePort->sendFunctional(pkt); 1808733Sgeoffrey.blake@arm.com } else { 1818733Sgeoffrey.blake@arm.com // Assume the data is correct if it's an uncached access 1828733Sgeoffrey.blake@arm.com memcpy(data, unverifiedMemData, size); 1838733Sgeoffrey.blake@arm.com } 1848733Sgeoffrey.blake@arm.com 1858733Sgeoffrey.blake@arm.com delete memReq; 1868733Sgeoffrey.blake@arm.com memReq = NULL; 1878733Sgeoffrey.blake@arm.com delete pkt; 1888733Sgeoffrey.blake@arm.com } 1898733Sgeoffrey.blake@arm.com 1908733Sgeoffrey.blake@arm.com if (fault != NoFault) { 1918733Sgeoffrey.blake@arm.com if (memReq->isPrefetch()) { 1928733Sgeoffrey.blake@arm.com fault = NoFault; 1938733Sgeoffrey.blake@arm.com } 1948733Sgeoffrey.blake@arm.com delete memReq; 1958733Sgeoffrey.blake@arm.com memReq = NULL; 1968733Sgeoffrey.blake@arm.com break; 1978733Sgeoffrey.blake@arm.com } 1988733Sgeoffrey.blake@arm.com 1998733Sgeoffrey.blake@arm.com if (memReq != NULL) { 2008733Sgeoffrey.blake@arm.com delete memReq; 2018733Sgeoffrey.blake@arm.com } 2028733Sgeoffrey.blake@arm.com 2038733Sgeoffrey.blake@arm.com //If we don't need to access a second cache line, stop now. 2048733Sgeoffrey.blake@arm.com if (secondAddr <= addr) 2058733Sgeoffrey.blake@arm.com { 2068733Sgeoffrey.blake@arm.com break; 2078733Sgeoffrey.blake@arm.com } 2088733Sgeoffrey.blake@arm.com 2098733Sgeoffrey.blake@arm.com // Setup for accessing next cache line 2108733Sgeoffrey.blake@arm.com data += size; 2118733Sgeoffrey.blake@arm.com unverifiedMemData += size; 2128733Sgeoffrey.blake@arm.com size = addr + fullSize - secondAddr; 2138733Sgeoffrey.blake@arm.com addr = secondAddr; 2142789Sktlim@umich.edu } 2152789Sktlim@umich.edu 2168733Sgeoffrey.blake@arm.com if (!flags_match) { 2178733Sgeoffrey.blake@arm.com warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n", 2188733Sgeoffrey.blake@arm.com curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(), 2198733Sgeoffrey.blake@arm.com unverifiedReq->getFlags(), addr, pAddr, flags); 2208733Sgeoffrey.blake@arm.com handleError(); 2218733Sgeoffrey.blake@arm.com } 2222789Sktlim@umich.edu 2238733Sgeoffrey.blake@arm.com return fault; 2242789Sktlim@umich.edu} 2252789Sktlim@umich.edu 2268733Sgeoffrey.blake@arm.comFault 2278733Sgeoffrey.blake@arm.comCheckerCPU::writeMem(uint8_t *data, unsigned size, 2288733Sgeoffrey.blake@arm.com Addr addr, unsigned flags, uint64_t *res) 2298733Sgeoffrey.blake@arm.com{ 2308733Sgeoffrey.blake@arm.com Fault fault = NoFault; 2318733Sgeoffrey.blake@arm.com bool checked_flags = false; 2328733Sgeoffrey.blake@arm.com bool flags_match = true; 2338733Sgeoffrey.blake@arm.com Addr pAddr = 0x0; 23410505SAli.Saidi@ARM.com static uint8_t zero_data[64] = {}; 2352789Sktlim@umich.edu 2368733Sgeoffrey.blake@arm.com int fullSize = size; 2372789Sktlim@umich.edu 2389814Sandreas.hansson@arm.com Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 2392789Sktlim@umich.edu 2408733Sgeoffrey.blake@arm.com if (secondAddr > addr) 2418733Sgeoffrey.blake@arm.com size = secondAddr - addr; 2422789Sktlim@umich.edu 2438733Sgeoffrey.blake@arm.com // Need to account for a multiple access like Atomic and Timing CPUs 2448733Sgeoffrey.blake@arm.com while (1) { 24510653Sandreas.hansson@arm.com memReq = new Request(0, addr, size, flags, masterId, 24611435Smitch.hayenga@arm.com thread->pcState().instAddr(), tc->contextId()); 2472789Sktlim@umich.edu 2488733Sgeoffrey.blake@arm.com // translate to physical address 2498733Sgeoffrey.blake@arm.com fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write); 2502789Sktlim@umich.edu 2518733Sgeoffrey.blake@arm.com if (!checked_flags && fault == NoFault && unverifiedReq) { 2528733Sgeoffrey.blake@arm.com flags_match = checkFlags(unverifiedReq, memReq->getVaddr(), 2538733Sgeoffrey.blake@arm.com memReq->getPaddr(), memReq->getFlags()); 2548733Sgeoffrey.blake@arm.com pAddr = memReq->getPaddr(); 2558733Sgeoffrey.blake@arm.com checked_flags = true; 2568733Sgeoffrey.blake@arm.com } 2578733Sgeoffrey.blake@arm.com 2588733Sgeoffrey.blake@arm.com /* 2598733Sgeoffrey.blake@arm.com * We don't actually check memory for the store because there 2608733Sgeoffrey.blake@arm.com * is no guarantee it has left the lsq yet, and therefore we 2618733Sgeoffrey.blake@arm.com * can't verify the memory on stores without lsq snooping 2628733Sgeoffrey.blake@arm.com * enabled. This is left as future work for the Checker: LSQ snooping 2638733Sgeoffrey.blake@arm.com * and memory validation after stores have committed. 2648733Sgeoffrey.blake@arm.com */ 2658990SAli.Saidi@ARM.com bool was_prefetch = memReq->isPrefetch(); 2668733Sgeoffrey.blake@arm.com 2678733Sgeoffrey.blake@arm.com delete memReq; 2688733Sgeoffrey.blake@arm.com 2698733Sgeoffrey.blake@arm.com //If we don't need to access a second cache line, stop now. 2708733Sgeoffrey.blake@arm.com if (fault != NoFault || secondAddr <= addr) 2718733Sgeoffrey.blake@arm.com { 2728990SAli.Saidi@ARM.com if (fault != NoFault && was_prefetch) { 2738733Sgeoffrey.blake@arm.com fault = NoFault; 2748733Sgeoffrey.blake@arm.com } 2758733Sgeoffrey.blake@arm.com break; 2768733Sgeoffrey.blake@arm.com } 2778733Sgeoffrey.blake@arm.com 2788733Sgeoffrey.blake@arm.com //Update size and access address 2798733Sgeoffrey.blake@arm.com size = addr + fullSize - secondAddr; 2808733Sgeoffrey.blake@arm.com //And access the right address. 2818733Sgeoffrey.blake@arm.com addr = secondAddr; 2828733Sgeoffrey.blake@arm.com } 2838733Sgeoffrey.blake@arm.com 2848733Sgeoffrey.blake@arm.com if (!flags_match) { 2858733Sgeoffrey.blake@arm.com warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n", 2868733Sgeoffrey.blake@arm.com curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(), 2878733Sgeoffrey.blake@arm.com unverifiedReq->getFlags(), addr, pAddr, flags); 2888733Sgeoffrey.blake@arm.com handleError(); 2898733Sgeoffrey.blake@arm.com } 2908733Sgeoffrey.blake@arm.com 2918733Sgeoffrey.blake@arm.com // Assume the result was the same as the one passed in. This checker 2928733Sgeoffrey.blake@arm.com // doesn't check if the SC should succeed or fail, it just checks the 2938733Sgeoffrey.blake@arm.com // value. 2948733Sgeoffrey.blake@arm.com if (unverifiedReq && res && unverifiedReq->extraDataValid()) 2958733Sgeoffrey.blake@arm.com *res = unverifiedReq->getExtraData(); 2968733Sgeoffrey.blake@arm.com 2978733Sgeoffrey.blake@arm.com // Entire purpose here is to make sure we are getting the 2988733Sgeoffrey.blake@arm.com // same data to send to the mem system as the CPU did. 2998733Sgeoffrey.blake@arm.com // Cannot check this is actually what went to memory because 3008733Sgeoffrey.blake@arm.com // there stores can be in ld/st queue or coherent operations 3018733Sgeoffrey.blake@arm.com // overwriting values. 30210416Sandreas.hansson@arm.com bool extraData = false; 3038733Sgeoffrey.blake@arm.com if (unverifiedReq) { 3048733Sgeoffrey.blake@arm.com extraData = unverifiedReq->extraDataValid() ? 30510416Sandreas.hansson@arm.com unverifiedReq->getExtraData() : true; 3068733Sgeoffrey.blake@arm.com } 3078733Sgeoffrey.blake@arm.com 30810505SAli.Saidi@ARM.com // If the request is to ZERO a cache block, there is no data to check 30910505SAli.Saidi@ARM.com // against, but it's all zero. We need something to compare to, so use a 31010505SAli.Saidi@ARM.com // const set of zeros. 31110505SAli.Saidi@ARM.com if (flags & Request::CACHE_BLOCK_ZERO) { 31210505SAli.Saidi@ARM.com assert(!data); 31310505SAli.Saidi@ARM.com assert(sizeof(zero_data) <= fullSize); 31410505SAli.Saidi@ARM.com data = zero_data; 31510505SAli.Saidi@ARM.com } 31610505SAli.Saidi@ARM.com 3178733Sgeoffrey.blake@arm.com if (unverifiedReq && unverifiedMemData && 3188733Sgeoffrey.blake@arm.com memcmp(data, unverifiedMemData, fullSize) && extraData) { 31910367SAndrew.Bardsley@arm.com warn("%lli: Store value does not match value sent to memory! " 32010367SAndrew.Bardsley@arm.com "data: %#x inst_data: %#x", curTick(), data, 3218733Sgeoffrey.blake@arm.com unverifiedMemData); 3228733Sgeoffrey.blake@arm.com handleError(); 3238733Sgeoffrey.blake@arm.com } 3248733Sgeoffrey.blake@arm.com 3258733Sgeoffrey.blake@arm.com return fault; 3262789Sktlim@umich.edu} 3272789Sktlim@umich.edu 3282789Sktlim@umich.eduAddr 3292789Sktlim@umich.eduCheckerCPU::dbg_vtophys(Addr addr) 3302789Sktlim@umich.edu{ 3312789Sktlim@umich.edu return vtophys(tc, addr); 3322789Sktlim@umich.edu} 3332789Sktlim@umich.edu 3348733Sgeoffrey.blake@arm.com/** 3358733Sgeoffrey.blake@arm.com * Checks if the flags set by the Checker and Checkee match. 3368733Sgeoffrey.blake@arm.com */ 3372789Sktlim@umich.edubool 3388733Sgeoffrey.blake@arm.comCheckerCPU::checkFlags(Request *unverified_req, Addr vAddr, 3398733Sgeoffrey.blake@arm.com Addr pAddr, int flags) 3402789Sktlim@umich.edu{ 3418733Sgeoffrey.blake@arm.com Addr unverifiedVAddr = unverified_req->getVaddr(); 3428733Sgeoffrey.blake@arm.com Addr unverifiedPAddr = unverified_req->getPaddr(); 3438733Sgeoffrey.blake@arm.com int unverifiedFlags = unverified_req->getFlags(); 3448733Sgeoffrey.blake@arm.com 3458733Sgeoffrey.blake@arm.com if (unverifiedVAddr != vAddr || 3468733Sgeoffrey.blake@arm.com unverifiedPAddr != pAddr || 3478733Sgeoffrey.blake@arm.com unverifiedFlags != flags) { 3482789Sktlim@umich.edu return false; 3492789Sktlim@umich.edu } 3508733Sgeoffrey.blake@arm.com 3518733Sgeoffrey.blake@arm.com return true; 3522789Sktlim@umich.edu} 3532789Sktlim@umich.edu 3542789Sktlim@umich.eduvoid 3552789Sktlim@umich.eduCheckerCPU::dumpAndExit() 3562789Sktlim@umich.edu{ 3578733Sgeoffrey.blake@arm.com warn("%lli: Checker PC:%s", 3588733Sgeoffrey.blake@arm.com curTick(), thread->pcState()); 3592789Sktlim@umich.edu panic("Checker found an error!"); 3602789Sktlim@umich.edu} 361