base_dyn_inst_impl.hh revision 9046:a1104cc13db2 
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#include <iostream>
44#include <set>
45#include <sstream>
46#include <string>
47
48#include "base/cprintf.hh"
49#include "base/trace.hh"
50#include "config/the_isa.hh"
51#include "cpu/base_dyn_inst.hh"
52#include "cpu/exetrace.hh"
53#include "debug/DynInst.hh"
54#include "debug/IQ.hh"
55#include "mem/request.hh"
56#include "sim/faults.hh"
57
58template <class Impl>
59BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
60                               StaticInstPtr _macroop,
61                               TheISA::PCState _pc, TheISA::PCState _predPC,
62                               InstSeqNum seq_num, ImplCPU *cpu)
63  : staticInst(_staticInst), cpu(cpu), traceData(NULL), macroop(_macroop)
64{
65    seqNum = seq_num;
66
67    pc = _pc;
68    predPC = _predPC;
69
70    initVars();
71}
72
73template <class Impl>
74BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
75                               StaticInstPtr _macroop)
76    : staticInst(_staticInst), traceData(NULL), macroop(_macroop)
77{
78    seqNum = 0;
79    initVars();
80}
81
82template <class Impl>
83void
84BaseDynInst<Impl>::initVars()
85{
86    memData = NULL;
87    effAddr = 0;
88    physEffAddr = 0;
89    readyRegs = 0;
90
91    status.reset();
92
93    instFlags.reset();
94    instFlags[RecordResult] = true;
95    instFlags[Predicate] = true;
96
97    lqIdx = -1;
98    sqIdx = -1;
99
100    // Eventually make this a parameter.
101    threadNumber = 0;
102
103    // Also make this a parameter, or perhaps get it from xc or cpu.
104    asid = 0;
105
106    // Initialize the fault to be NoFault.
107    fault = NoFault;
108
109#ifndef NDEBUG
110    ++cpu->instcount;
111
112    if (cpu->instcount > 1500) {
113#ifdef DEBUG
114        cpu->dumpInsts();
115        dumpSNList();
116#endif
117        assert(cpu->instcount <= 1500);
118    }
119
120    DPRINTF(DynInst,
121        "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
122        seqNum, cpu->name(), cpu->instcount);
123#endif
124
125#ifdef DEBUG
126    cpu->snList.insert(seqNum);
127#endif
128
129    reqToVerify = NULL;
130}
131
132template <class Impl>
133BaseDynInst<Impl>::~BaseDynInst()
134{
135    if (memData) {
136        delete [] memData;
137    }
138
139    if (traceData) {
140        delete traceData;
141    }
142
143    fault = NoFault;
144
145#ifndef NDEBUG
146    --cpu->instcount;
147
148    DPRINTF(DynInst,
149        "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
150        seqNum, cpu->name(), cpu->instcount);
151#endif
152#ifdef DEBUG
153    cpu->snList.erase(seqNum);
154#endif
155
156    if (reqToVerify)
157        delete reqToVerify;
158}
159
160#ifdef DEBUG
161template <class Impl>
162void
163BaseDynInst<Impl>::dumpSNList()
164{
165    std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
166
167    int count = 0;
168    while (sn_it != cpu->snList.end()) {
169        cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
170        count++;
171        sn_it++;
172    }
173}
174#endif
175
176template <class Impl>
177void
178BaseDynInst<Impl>::dump()
179{
180    cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
181    std::cout << staticInst->disassemble(pc.instAddr());
182    cprintf("'\n");
183}
184
185template <class Impl>
186void
187BaseDynInst<Impl>::dump(std::string &outstring)
188{
189    std::ostringstream s;
190    s << "T" << threadNumber << " : 0x" << pc.instAddr() << " "
191      << staticInst->disassemble(pc.instAddr());
192
193    outstring = s.str();
194}
195
196template <class Impl>
197void
198BaseDynInst<Impl>::markSrcRegReady()
199{
200    DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
201            seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
202    if (++readyRegs == numSrcRegs()) {
203        setCanIssue();
204    }
205}
206
207template <class Impl>
208void
209BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
210{
211    _readySrcRegIdx[src_idx] = true;
212
213    markSrcRegReady();
214}
215
216template <class Impl>
217bool
218BaseDynInst<Impl>::eaSrcsReady()
219{
220    // For now I am assuming that src registers 1..n-1 are the ones that the
221    // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
222    // stored)
223
224    for (int i = 1; i < numSrcRegs(); ++i) {
225        if (!_readySrcRegIdx[i])
226            return false;
227    }
228
229    return true;
230}
231