base_dyn_inst_impl.hh revision 8502:f1fc7102c970 
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#include <iostream>
44#include <set>
45#include <sstream>
46#include <string>
47
48#include "base/cprintf.hh"
49#include "base/trace.hh"
50#include "config/the_isa.hh"
51#include "cpu/base_dyn_inst.hh"
52#include "cpu/exetrace.hh"
53#include "debug/DynInst.hh"
54#include "debug/IQ.hh"
55#include "mem/request.hh"
56#include "sim/faults.hh"
57
58#define NOHASH
59#ifndef NOHASH
60
61#include "base/hashmap.hh"
62
63unsigned int MyHashFunc(const BaseDynInst *addr)
64{
65    unsigned a = (unsigned)addr;
66    unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
67
68    return hash;
69}
70
71typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
72my_hash_t;
73
74my_hash_t thishash;
75#endif
76
77template <class Impl>
78BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
79                               StaticInstPtr _macroop,
80                               TheISA::PCState _pc, TheISA::PCState _predPC,
81                               InstSeqNum seq_num, ImplCPU *cpu)
82  : staticInst(_staticInst), macroop(_macroop), traceData(NULL), cpu(cpu)
83{
84    seqNum = seq_num;
85
86    pc = _pc;
87    predPC = _predPC;
88    predTaken = false;
89
90    initVars();
91}
92
93template <class Impl>
94BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
95                               StaticInstPtr _macroop)
96    : staticInst(_staticInst), macroop(_macroop), traceData(NULL)
97{
98    seqNum = 0;
99    initVars();
100}
101
102template <class Impl>
103void
104BaseDynInst<Impl>::initVars()
105{
106    memData = NULL;
107    effAddr = 0;
108    effAddrValid = false;
109    physEffAddr = 0;
110
111    translationStarted = false;
112    translationCompleted = false;
113
114    isUncacheable = false;
115    reqMade = false;
116    readyRegs = 0;
117
118    instResult.integer = 0;
119    recordResult = true;
120
121    status.reset();
122
123    eaCalcDone = false;
124    memOpDone = false;
125    predicate = true;
126
127    lqIdx = -1;
128    sqIdx = -1;
129
130    // Eventually make this a parameter.
131    threadNumber = 0;
132
133    // Also make this a parameter, or perhaps get it from xc or cpu.
134    asid = 0;
135
136    // Initialize the fault to be NoFault.
137    fault = NoFault;
138
139#ifndef NDEBUG
140    ++cpu->instcount;
141
142    if (cpu->instcount > 1500) {
143#ifdef DEBUG
144        cpu->dumpInsts();
145        dumpSNList();
146#endif
147        assert(cpu->instcount <= 1500);
148    }
149
150    DPRINTF(DynInst,
151        "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
152        seqNum, cpu->name(), cpu->instcount);
153#endif
154
155#ifdef DEBUG
156    cpu->snList.insert(seqNum);
157#endif
158}
159
160template <class Impl>
161BaseDynInst<Impl>::~BaseDynInst()
162{
163    if (memData) {
164        delete [] memData;
165    }
166
167    if (traceData) {
168        delete traceData;
169    }
170
171    fault = NoFault;
172
173#ifndef NDEBUG
174    --cpu->instcount;
175
176    DPRINTF(DynInst,
177        "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
178        seqNum, cpu->name(), cpu->instcount);
179#endif
180#ifdef DEBUG
181    cpu->snList.erase(seqNum);
182#endif
183}
184
185#ifdef DEBUG
186template <class Impl>
187void
188BaseDynInst<Impl>::dumpSNList()
189{
190    std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
191
192    int count = 0;
193    while (sn_it != cpu->snList.end()) {
194        cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
195        count++;
196        sn_it++;
197    }
198}
199#endif
200
201template <class Impl>
202void
203BaseDynInst<Impl>::dump()
204{
205    cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
206    std::cout << staticInst->disassemble(pc.instAddr());
207    cprintf("'\n");
208}
209
210template <class Impl>
211void
212BaseDynInst<Impl>::dump(std::string &outstring)
213{
214    std::ostringstream s;
215    s << "T" << threadNumber << " : 0x" << pc.instAddr() << " "
216      << staticInst->disassemble(pc.instAddr());
217
218    outstring = s.str();
219}
220
221template <class Impl>
222void
223BaseDynInst<Impl>::markSrcRegReady()
224{
225    DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
226            seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
227    if (++readyRegs == numSrcRegs()) {
228        setCanIssue();
229    }
230}
231
232template <class Impl>
233void
234BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
235{
236    _readySrcRegIdx[src_idx] = true;
237
238    markSrcRegReady();
239}
240
241template <class Impl>
242bool
243BaseDynInst<Impl>::eaSrcsReady()
244{
245    // For now I am assuming that src registers 1..n-1 are the ones that the
246    // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
247    // stored)
248
249    for (int i = 1; i < numSrcRegs(); ++i) {
250        if (!_readySrcRegIdx[i])
251            return false;
252    }
253
254    return true;
255}
256