base_dyn_inst_impl.hh revision 6658:f4de76601762
17118Sgblack@eecs.umich.edu/*
27118Sgblack@eecs.umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan
37118Sgblack@eecs.umich.edu * All rights reserved.
47118Sgblack@eecs.umich.edu *
57118Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without
67118Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are
77118Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright
87118Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer;
97118Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright
107118Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the
117118Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution;
127118Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its
137118Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from
147118Sgblack@eecs.umich.edu * this software without specific prior written permission.
156253Sgblack@eecs.umich.edu *
166253Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
176253Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
186253Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
196253Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
206253Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
216253Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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236253Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
246253Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
256253Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
266253Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
276253Sgblack@eecs.umich.edu *
286253Sgblack@eecs.umich.edu * Authors: Kevin Lim
296253Sgblack@eecs.umich.edu */
306253Sgblack@eecs.umich.edu
316253Sgblack@eecs.umich.edu#include <iostream>
326253Sgblack@eecs.umich.edu#include <set>
336253Sgblack@eecs.umich.edu#include <string>
346253Sgblack@eecs.umich.edu#include <sstream>
356253Sgblack@eecs.umich.edu
366253Sgblack@eecs.umich.edu#include "base/cprintf.hh"
376253Sgblack@eecs.umich.edu#include "base/trace.hh"
386253Sgblack@eecs.umich.edu#include "config/the_isa.hh"
396253Sgblack@eecs.umich.edu#include "cpu/base_dyn_inst.hh"
406253Sgblack@eecs.umich.edu#include "cpu/exetrace.hh"
416253Sgblack@eecs.umich.edu#include "mem/request.hh"
426253Sgblack@eecs.umich.edu#include "sim/faults.hh"
436253Sgblack@eecs.umich.edu
446253Sgblack@eecs.umich.edu#define NOHASH
456253Sgblack@eecs.umich.edu#ifndef NOHASH
466253Sgblack@eecs.umich.edu
476253Sgblack@eecs.umich.edu#include "base/hashmap.hh"
486253Sgblack@eecs.umich.edu
497118Sgblack@eecs.umich.eduunsigned int MyHashFunc(const BaseDynInst *addr)
507205Sgblack@eecs.umich.edu{
517205Sgblack@eecs.umich.edu    unsigned a = (unsigned)addr;
527205Sgblack@eecs.umich.edu    unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
537205Sgblack@eecs.umich.edu
547205Sgblack@eecs.umich.edu    return hash;
557205Sgblack@eecs.umich.edu}
567205Sgblack@eecs.umich.edu
577205Sgblack@eecs.umich.edutypedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
587205Sgblack@eecs.umich.edumy_hash_t;
597205Sgblack@eecs.umich.edu
607205Sgblack@eecs.umich.edumy_hash_t thishash;
617205Sgblack@eecs.umich.edu#endif
627205Sgblack@eecs.umich.edu
637205Sgblack@eecs.umich.edutemplate <class Impl>
647205Sgblack@eecs.umich.eduBaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
657205Sgblack@eecs.umich.edu                               Addr inst_PC, Addr inst_NPC,
667720Sgblack@eecs.umich.edu                               Addr inst_MicroPC,
677720Sgblack@eecs.umich.edu                               Addr pred_PC, Addr pred_NPC,
687720Sgblack@eecs.umich.edu                               Addr pred_MicroPC,
697720Sgblack@eecs.umich.edu                               InstSeqNum seq_num, ImplCPU *cpu)
707720Sgblack@eecs.umich.edu  : staticInst(_staticInst), traceData(NULL), cpu(cpu)
717720Sgblack@eecs.umich.edu{
727720Sgblack@eecs.umich.edu    seqNum = seq_num;
737720Sgblack@eecs.umich.edu
747720Sgblack@eecs.umich.edu    bool nextIsMicro =
757720Sgblack@eecs.umich.edu        staticInst->isMicroop() && !staticInst->isLastMicroop();
767720Sgblack@eecs.umich.edu
777720Sgblack@eecs.umich.edu    PC = inst_PC;
787720Sgblack@eecs.umich.edu    microPC = inst_MicroPC;
797720Sgblack@eecs.umich.edu    if (nextIsMicro) {
807720Sgblack@eecs.umich.edu        nextPC = inst_PC;
817720Sgblack@eecs.umich.edu        nextNPC = inst_NPC;
827720Sgblack@eecs.umich.edu        nextMicroPC = microPC + 1;
837720Sgblack@eecs.umich.edu    } else {
847720Sgblack@eecs.umich.edu        nextPC = inst_NPC;
857720Sgblack@eecs.umich.edu        nextNPC = nextPC + sizeof(TheISA::MachInst);
867291Sgblack@eecs.umich.edu        nextMicroPC = 0;
877720Sgblack@eecs.umich.edu    }
887291Sgblack@eecs.umich.edu    predPC = pred_PC;
897291Sgblack@eecs.umich.edu    predNPC = pred_NPC;
907291Sgblack@eecs.umich.edu    predMicroPC = pred_MicroPC;
917291Sgblack@eecs.umich.edu    predTaken = false;
927291Sgblack@eecs.umich.edu
937291Sgblack@eecs.umich.edu    initVars();
947291Sgblack@eecs.umich.edu}
957291Sgblack@eecs.umich.edu
967291Sgblack@eecs.umich.edutemplate <class Impl>
977291Sgblack@eecs.umich.eduBaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst inst,
987291Sgblack@eecs.umich.edu                               Addr inst_PC, Addr inst_NPC,
997291Sgblack@eecs.umich.edu                               Addr inst_MicroPC,
1008140SMatt.Horsnell@arm.com                               Addr pred_PC, Addr pred_NPC,
1018140SMatt.Horsnell@arm.com                               Addr pred_MicroPC,
1027646Sgene.wu@arm.com                               InstSeqNum seq_num, ImplCPU *cpu)
1037646Sgene.wu@arm.com  : staticInst(inst, inst_PC), traceData(NULL), cpu(cpu)
1047291Sgblack@eecs.umich.edu{
1057291Sgblack@eecs.umich.edu    seqNum = seq_num;
1067291Sgblack@eecs.umich.edu
1077720Sgblack@eecs.umich.edu    bool nextIsMicro =
1088140SMatt.Horsnell@arm.com        staticInst->isMicroop() && !staticInst->isLastMicroop();
1098140SMatt.Horsnell@arm.com
1108140SMatt.Horsnell@arm.com    PC = inst_PC;
1118140SMatt.Horsnell@arm.com    microPC = inst_MicroPC;
1127291Sgblack@eecs.umich.edu    if (nextIsMicro) {
1137291Sgblack@eecs.umich.edu        nextPC = inst_PC;
1147646Sgene.wu@arm.com        nextNPC = inst_NPC;
1157646Sgene.wu@arm.com        nextMicroPC = microPC + 1;
1167646Sgene.wu@arm.com    } else {
1177747SAli.Saidi@ARM.com        nextPC = inst_NPC;
1187646Sgene.wu@arm.com        nextNPC = nextPC + sizeof(TheISA::MachInst);
1197646Sgene.wu@arm.com        nextMicroPC = 0;
1207646Sgene.wu@arm.com    }
1217720Sgblack@eecs.umich.edu    predPC = pred_PC;
1227646Sgene.wu@arm.com    predNPC = pred_NPC;
1237646Sgene.wu@arm.com    predMicroPC = pred_MicroPC;
1247646Sgene.wu@arm.com    predTaken = false;
1257646Sgene.wu@arm.com
1267646Sgene.wu@arm.com    initVars();
1277291Sgblack@eecs.umich.edu}
1287291Sgblack@eecs.umich.edu
1297291Sgblack@eecs.umich.edutemplate <class Impl>
1307312Sgblack@eecs.umich.eduBaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
1317720Sgblack@eecs.umich.edu    : staticInst(_staticInst), traceData(NULL)
1327312Sgblack@eecs.umich.edu{
1337312Sgblack@eecs.umich.edu    seqNum = 0;
1347312Sgblack@eecs.umich.edu    initVars();
1357312Sgblack@eecs.umich.edu}
1367312Sgblack@eecs.umich.edu
1377312Sgblack@eecs.umich.edutemplate <class Impl>
1387312Sgblack@eecs.umich.eduvoid
1397312Sgblack@eecs.umich.eduBaseDynInst<Impl>::initVars()
1407312Sgblack@eecs.umich.edu{
1417312Sgblack@eecs.umich.edu    memData = NULL;
1427312Sgblack@eecs.umich.edu    effAddr = 0;
1437312Sgblack@eecs.umich.edu    effAddrValid = false;
1447646Sgene.wu@arm.com    physEffAddr = 0;
1457646Sgene.wu@arm.com
1467646Sgene.wu@arm.com    isUncacheable = false;
1477312Sgblack@eecs.umich.edu    reqMade = false;
1487312Sgblack@eecs.umich.edu    readyRegs = 0;
1497312Sgblack@eecs.umich.edu
1507720Sgblack@eecs.umich.edu    instResult.integer = 0;
1517646Sgene.wu@arm.com    recordResult = true;
1527312Sgblack@eecs.umich.edu
1537312Sgblack@eecs.umich.edu    status.reset();
1547646Sgene.wu@arm.com
1557646Sgene.wu@arm.com    eaCalcDone = false;
1567646Sgene.wu@arm.com    memOpDone = false;
1577845SAli.Saidi@ARM.com
1587646Sgene.wu@arm.com    lqIdx = -1;
1597646Sgene.wu@arm.com    sqIdx = -1;
1607646Sgene.wu@arm.com
1617720Sgblack@eecs.umich.edu    // Eventually make this a parameter.
1627646Sgene.wu@arm.com    threadNumber = 0;
1637646Sgene.wu@arm.com
1647646Sgene.wu@arm.com    // Also make this a parameter, or perhaps get it from xc or cpu.
1657646Sgene.wu@arm.com    asid = 0;
1667646Sgene.wu@arm.com
1677312Sgblack@eecs.umich.edu    // Initialize the fault to be NoFault.
1687312Sgblack@eecs.umich.edu    fault = NoFault;
1697312Sgblack@eecs.umich.edu
1707720Sgblack@eecs.umich.edu#ifndef NDEBUG
1717118Sgblack@eecs.umich.edu    ++cpu->instcount;
1727118Sgblack@eecs.umich.edu
1737118Sgblack@eecs.umich.edu    if (cpu->instcount > 1500) {
1747118Sgblack@eecs.umich.edu#ifdef DEBUG
1757118Sgblack@eecs.umich.edu        cpu->dumpInsts();
1767118Sgblack@eecs.umich.edu        dumpSNList();
1777118Sgblack@eecs.umich.edu#endif
1787118Sgblack@eecs.umich.edu        assert(cpu->instcount <= 1500);
1797118Sgblack@eecs.umich.edu    }
1807118Sgblack@eecs.umich.edu
1817118Sgblack@eecs.umich.edu    DPRINTF(DynInst,
1827118Sgblack@eecs.umich.edu        "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
1837118Sgblack@eecs.umich.edu        seqNum, cpu->name(), cpu->instcount);
1847646Sgene.wu@arm.com#endif
1857646Sgene.wu@arm.com
1867646Sgene.wu@arm.com#ifdef DEBUG
1877118Sgblack@eecs.umich.edu    cpu->snList.insert(seqNum);
1887132Sgblack@eecs.umich.edu#endif
1897132Sgblack@eecs.umich.edu}
1907720Sgblack@eecs.umich.edu
1917646Sgene.wu@arm.comtemplate <class Impl>
1927118Sgblack@eecs.umich.eduBaseDynInst<Impl>::~BaseDynInst()
1937118Sgblack@eecs.umich.edu{
1947646Sgene.wu@arm.com    if (memData) {
1957646Sgene.wu@arm.com        delete [] memData;
1967646Sgene.wu@arm.com    }
1977646Sgene.wu@arm.com
1987646Sgene.wu@arm.com    if (traceData) {
1997646Sgene.wu@arm.com        delete traceData;
2007646Sgene.wu@arm.com    }
2017720Sgblack@eecs.umich.edu
2027646Sgene.wu@arm.com    fault = NoFault;
2037646Sgene.wu@arm.com
2047646Sgene.wu@arm.com#ifndef NDEBUG
2057646Sgene.wu@arm.com    --cpu->instcount;
2067646Sgene.wu@arm.com
2077118Sgblack@eecs.umich.edu    DPRINTF(DynInst,
2087118Sgblack@eecs.umich.edu        "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
2097118Sgblack@eecs.umich.edu        seqNum, cpu->name(), cpu->instcount);
2107118Sgblack@eecs.umich.edu#endif
2117279Sgblack@eecs.umich.edu#ifdef DEBUG
2127279Sgblack@eecs.umich.edu    cpu->snList.erase(seqNum);
2137279Sgblack@eecs.umich.edu#endif
2147279Sgblack@eecs.umich.edu}
2157279Sgblack@eecs.umich.edu
2167279Sgblack@eecs.umich.edu#ifdef DEBUG
2177118Sgblack@eecs.umich.edutemplate <class Impl>
2187118Sgblack@eecs.umich.eduvoid
2197118Sgblack@eecs.umich.eduBaseDynInst<Impl>::dumpSNList()
2207118Sgblack@eecs.umich.edu{
2217132Sgblack@eecs.umich.edu    std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
2227118Sgblack@eecs.umich.edu
2237118Sgblack@eecs.umich.edu    int count = 0;
2247118Sgblack@eecs.umich.edu    while (sn_it != cpu->snList.end()) {
2257118Sgblack@eecs.umich.edu        cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
2267132Sgblack@eecs.umich.edu        count++;
2277132Sgblack@eecs.umich.edu        sn_it++;
2287132Sgblack@eecs.umich.edu    }
2297118Sgblack@eecs.umich.edu}
2307118Sgblack@eecs.umich.edu#endif
2317118Sgblack@eecs.umich.edu
2327118Sgblack@eecs.umich.edutemplate <class Impl>
2337118Sgblack@eecs.umich.eduvoid
2347118Sgblack@eecs.umich.eduBaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
2357118Sgblack@eecs.umich.edu{
2367118Sgblack@eecs.umich.edu    // This is the "functional" implementation of prefetch.  Not much
2377118Sgblack@eecs.umich.edu    // happens here since prefetches don't affect the architectural
2387118Sgblack@eecs.umich.edu    // state.
2397118Sgblack@eecs.umich.edu/*
2407118Sgblack@eecs.umich.edu    // Generate a MemReq so we can translate the effective address.
2417303Sgblack@eecs.umich.edu    MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags);
2427303Sgblack@eecs.umich.edu    req->asid = asid;
2437303Sgblack@eecs.umich.edu
2447303Sgblack@eecs.umich.edu    // Prefetches never cause faults.
2457303Sgblack@eecs.umich.edu    fault = NoFault;
2467303Sgblack@eecs.umich.edu
2477303Sgblack@eecs.umich.edu    // note this is a local, not BaseDynInst::fault
2487303Sgblack@eecs.umich.edu    Fault trans_fault = cpu->translateDataReadReq(req);
2497303Sgblack@eecs.umich.edu
2507303Sgblack@eecs.umich.edu    if (trans_fault == NoFault && !(req->isUncacheable())) {
2517303Sgblack@eecs.umich.edu        // It's a valid address to cacheable space.  Record key MemReq
2527303Sgblack@eecs.umich.edu        // parameters so we can generate another one just like it for
2537303Sgblack@eecs.umich.edu        // the timing access without calling translate() again (which
2547303Sgblack@eecs.umich.edu        // might mess up the TLB).
2557303Sgblack@eecs.umich.edu        effAddr = req->vaddr;
2567303Sgblack@eecs.umich.edu        physEffAddr = req->paddr;
2577303Sgblack@eecs.umich.edu        memReqFlags = req->flags;
2587303Sgblack@eecs.umich.edu    } else {
2597303Sgblack@eecs.umich.edu        // Bogus address (invalid or uncacheable space).  Mark it by
2607303Sgblack@eecs.umich.edu        // setting the eff_addr to InvalidAddr.
2617303Sgblack@eecs.umich.edu        effAddr = physEffAddr = MemReq::inval_addr;
2627279Sgblack@eecs.umich.edu    }
2637279Sgblack@eecs.umich.edu
2647279Sgblack@eecs.umich.edu    if (traceData) {
2657279Sgblack@eecs.umich.edu        traceData->setAddr(addr);
2667279Sgblack@eecs.umich.edu    }
2677279Sgblack@eecs.umich.edu*/
2687279Sgblack@eecs.umich.edu}
2697279Sgblack@eecs.umich.edu
2707279Sgblack@eecs.umich.edutemplate <class Impl>
2717279Sgblack@eecs.umich.eduvoid
2727279Sgblack@eecs.umich.eduBaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
2737279Sgblack@eecs.umich.edu{
2747279Sgblack@eecs.umich.edu    // Not currently supported.
2757279Sgblack@eecs.umich.edu}
2767279Sgblack@eecs.umich.edu
2777279Sgblack@eecs.umich.edu/**
2787279Sgblack@eecs.umich.edu * @todo Need to find a way to get the cache block size here.
2797279Sgblack@eecs.umich.edu */
2807279Sgblack@eecs.umich.edutemplate <class Impl>
2817279Sgblack@eecs.umich.eduFault
2827279Sgblack@eecs.umich.eduBaseDynInst<Impl>::copySrcTranslate(Addr src)
2837279Sgblack@eecs.umich.edu{
2847303Sgblack@eecs.umich.edu    // Not currently supported.
2857303Sgblack@eecs.umich.edu    return NoFault;
2867303Sgblack@eecs.umich.edu}
2877303Sgblack@eecs.umich.edu
2887303Sgblack@eecs.umich.edu/**
2897303Sgblack@eecs.umich.edu * @todo Need to find a way to get the cache block size here.
2907303Sgblack@eecs.umich.edu */
2917303Sgblack@eecs.umich.edutemplate <class Impl>
2927303Sgblack@eecs.umich.eduFault
2937303Sgblack@eecs.umich.eduBaseDynInst<Impl>::copy(Addr dest)
2947303Sgblack@eecs.umich.edu{
2957303Sgblack@eecs.umich.edu    // Not currently supported.
2967303Sgblack@eecs.umich.edu    return NoFault;
2977303Sgblack@eecs.umich.edu}
2987303Sgblack@eecs.umich.edu
2997303Sgblack@eecs.umich.edutemplate <class Impl>
3007303Sgblack@eecs.umich.eduvoid
3017303Sgblack@eecs.umich.eduBaseDynInst<Impl>::dump()
3027303Sgblack@eecs.umich.edu{
3037303Sgblack@eecs.umich.edu    cprintf("T%d : %#08d `", threadNumber, PC);
3047303Sgblack@eecs.umich.edu    std::cout << staticInst->disassemble(PC);
3057118Sgblack@eecs.umich.edu    cprintf("'\n");
3067132Sgblack@eecs.umich.edu}
3077118Sgblack@eecs.umich.edu
3087118Sgblack@eecs.umich.edutemplate <class Impl>
3097118Sgblack@eecs.umich.eduvoid
3107118Sgblack@eecs.umich.eduBaseDynInst<Impl>::dump(std::string &outstring)
3117118Sgblack@eecs.umich.edu{
3127118Sgblack@eecs.umich.edu    std::ostringstream s;
3137132Sgblack@eecs.umich.edu    s << "T" << threadNumber << " : 0x" << PC << " "
3147132Sgblack@eecs.umich.edu      << staticInst->disassemble(PC);
3157132Sgblack@eecs.umich.edu
3167132Sgblack@eecs.umich.edu    outstring = s.str();
3177132Sgblack@eecs.umich.edu}
3187118Sgblack@eecs.umich.edu
3197118Sgblack@eecs.umich.edutemplate <class Impl>
3207118Sgblack@eecs.umich.eduvoid
3217428Sgblack@eecs.umich.eduBaseDynInst<Impl>::markSrcRegReady()
3227118Sgblack@eecs.umich.edu{
3237118Sgblack@eecs.umich.edu    if (++readyRegs == numSrcRegs()) {
3247279Sgblack@eecs.umich.edu        setCanIssue();
3257279Sgblack@eecs.umich.edu    }
3267279Sgblack@eecs.umich.edu}
3277279Sgblack@eecs.umich.edu
3287279Sgblack@eecs.umich.edutemplate <class Impl>
3297279Sgblack@eecs.umich.eduvoid
3307279Sgblack@eecs.umich.eduBaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
3317279Sgblack@eecs.umich.edu{
3327279Sgblack@eecs.umich.edu    _readySrcRegIdx[src_idx] = true;
3337279Sgblack@eecs.umich.edu
3347279Sgblack@eecs.umich.edu    markSrcRegReady();
3357279Sgblack@eecs.umich.edu}
3367279Sgblack@eecs.umich.edu
3377279Sgblack@eecs.umich.edutemplate <class Impl>
3387279Sgblack@eecs.umich.edubool
3397279Sgblack@eecs.umich.eduBaseDynInst<Impl>::eaSrcsReady()
3407279Sgblack@eecs.umich.edu{
3417279Sgblack@eecs.umich.edu    // For now I am assuming that src registers 1..n-1 are the ones that the
3427279Sgblack@eecs.umich.edu    // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
3437279Sgblack@eecs.umich.edu    // stored)
3447279Sgblack@eecs.umich.edu
3457279Sgblack@eecs.umich.edu    for (int i = 1; i < numSrcRegs(); ++i) {
3467279Sgblack@eecs.umich.edu        if (!_readySrcRegIdx[i])
3477279Sgblack@eecs.umich.edu            return false;
3487118Sgblack@eecs.umich.edu    }
3497132Sgblack@eecs.umich.edu
3507118Sgblack@eecs.umich.edu    return true;
3517118Sgblack@eecs.umich.edu}
3527132Sgblack@eecs.umich.edu