base_dyn_inst_impl.hh revision 6658:f4de76601762 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <iostream>
32#include <set>
33#include <string>
34#include <sstream>
35
36#include "base/cprintf.hh"
37#include "base/trace.hh"
38#include "config/the_isa.hh"
39#include "cpu/base_dyn_inst.hh"
40#include "cpu/exetrace.hh"
41#include "mem/request.hh"
42#include "sim/faults.hh"
43
44#define NOHASH
45#ifndef NOHASH
46
47#include "base/hashmap.hh"
48
49unsigned int MyHashFunc(const BaseDynInst *addr)
50{
51    unsigned a = (unsigned)addr;
52    unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
53
54    return hash;
55}
56
57typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
58my_hash_t;
59
60my_hash_t thishash;
61#endif
62
63template <class Impl>
64BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
65                               Addr inst_PC, Addr inst_NPC,
66                               Addr inst_MicroPC,
67                               Addr pred_PC, Addr pred_NPC,
68                               Addr pred_MicroPC,
69                               InstSeqNum seq_num, ImplCPU *cpu)
70  : staticInst(_staticInst), traceData(NULL), cpu(cpu)
71{
72    seqNum = seq_num;
73
74    bool nextIsMicro =
75        staticInst->isMicroop() && !staticInst->isLastMicroop();
76
77    PC = inst_PC;
78    microPC = inst_MicroPC;
79    if (nextIsMicro) {
80        nextPC = inst_PC;
81        nextNPC = inst_NPC;
82        nextMicroPC = microPC + 1;
83    } else {
84        nextPC = inst_NPC;
85        nextNPC = nextPC + sizeof(TheISA::MachInst);
86        nextMicroPC = 0;
87    }
88    predPC = pred_PC;
89    predNPC = pred_NPC;
90    predMicroPC = pred_MicroPC;
91    predTaken = false;
92
93    initVars();
94}
95
96template <class Impl>
97BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst inst,
98                               Addr inst_PC, Addr inst_NPC,
99                               Addr inst_MicroPC,
100                               Addr pred_PC, Addr pred_NPC,
101                               Addr pred_MicroPC,
102                               InstSeqNum seq_num, ImplCPU *cpu)
103  : staticInst(inst, inst_PC), traceData(NULL), cpu(cpu)
104{
105    seqNum = seq_num;
106
107    bool nextIsMicro =
108        staticInst->isMicroop() && !staticInst->isLastMicroop();
109
110    PC = inst_PC;
111    microPC = inst_MicroPC;
112    if (nextIsMicro) {
113        nextPC = inst_PC;
114        nextNPC = inst_NPC;
115        nextMicroPC = microPC + 1;
116    } else {
117        nextPC = inst_NPC;
118        nextNPC = nextPC + sizeof(TheISA::MachInst);
119        nextMicroPC = 0;
120    }
121    predPC = pred_PC;
122    predNPC = pred_NPC;
123    predMicroPC = pred_MicroPC;
124    predTaken = false;
125
126    initVars();
127}
128
129template <class Impl>
130BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
131    : staticInst(_staticInst), traceData(NULL)
132{
133    seqNum = 0;
134    initVars();
135}
136
137template <class Impl>
138void
139BaseDynInst<Impl>::initVars()
140{
141    memData = NULL;
142    effAddr = 0;
143    effAddrValid = false;
144    physEffAddr = 0;
145
146    isUncacheable = false;
147    reqMade = false;
148    readyRegs = 0;
149
150    instResult.integer = 0;
151    recordResult = true;
152
153    status.reset();
154
155    eaCalcDone = false;
156    memOpDone = false;
157
158    lqIdx = -1;
159    sqIdx = -1;
160
161    // Eventually make this a parameter.
162    threadNumber = 0;
163
164    // Also make this a parameter, or perhaps get it from xc or cpu.
165    asid = 0;
166
167    // Initialize the fault to be NoFault.
168    fault = NoFault;
169
170#ifndef NDEBUG
171    ++cpu->instcount;
172
173    if (cpu->instcount > 1500) {
174#ifdef DEBUG
175        cpu->dumpInsts();
176        dumpSNList();
177#endif
178        assert(cpu->instcount <= 1500);
179    }
180
181    DPRINTF(DynInst,
182        "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
183        seqNum, cpu->name(), cpu->instcount);
184#endif
185
186#ifdef DEBUG
187    cpu->snList.insert(seqNum);
188#endif
189}
190
191template <class Impl>
192BaseDynInst<Impl>::~BaseDynInst()
193{
194    if (memData) {
195        delete [] memData;
196    }
197
198    if (traceData) {
199        delete traceData;
200    }
201
202    fault = NoFault;
203
204#ifndef NDEBUG
205    --cpu->instcount;
206
207    DPRINTF(DynInst,
208        "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
209        seqNum, cpu->name(), cpu->instcount);
210#endif
211#ifdef DEBUG
212    cpu->snList.erase(seqNum);
213#endif
214}
215
216#ifdef DEBUG
217template <class Impl>
218void
219BaseDynInst<Impl>::dumpSNList()
220{
221    std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
222
223    int count = 0;
224    while (sn_it != cpu->snList.end()) {
225        cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
226        count++;
227        sn_it++;
228    }
229}
230#endif
231
232template <class Impl>
233void
234BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
235{
236    // This is the "functional" implementation of prefetch.  Not much
237    // happens here since prefetches don't affect the architectural
238    // state.
239/*
240    // Generate a MemReq so we can translate the effective address.
241    MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags);
242    req->asid = asid;
243
244    // Prefetches never cause faults.
245    fault = NoFault;
246
247    // note this is a local, not BaseDynInst::fault
248    Fault trans_fault = cpu->translateDataReadReq(req);
249
250    if (trans_fault == NoFault && !(req->isUncacheable())) {
251        // It's a valid address to cacheable space.  Record key MemReq
252        // parameters so we can generate another one just like it for
253        // the timing access without calling translate() again (which
254        // might mess up the TLB).
255        effAddr = req->vaddr;
256        physEffAddr = req->paddr;
257        memReqFlags = req->flags;
258    } else {
259        // Bogus address (invalid or uncacheable space).  Mark it by
260        // setting the eff_addr to InvalidAddr.
261        effAddr = physEffAddr = MemReq::inval_addr;
262    }
263
264    if (traceData) {
265        traceData->setAddr(addr);
266    }
267*/
268}
269
270template <class Impl>
271void
272BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
273{
274    // Not currently supported.
275}
276
277/**
278 * @todo Need to find a way to get the cache block size here.
279 */
280template <class Impl>
281Fault
282BaseDynInst<Impl>::copySrcTranslate(Addr src)
283{
284    // Not currently supported.
285    return NoFault;
286}
287
288/**
289 * @todo Need to find a way to get the cache block size here.
290 */
291template <class Impl>
292Fault
293BaseDynInst<Impl>::copy(Addr dest)
294{
295    // Not currently supported.
296    return NoFault;
297}
298
299template <class Impl>
300void
301BaseDynInst<Impl>::dump()
302{
303    cprintf("T%d : %#08d `", threadNumber, PC);
304    std::cout << staticInst->disassemble(PC);
305    cprintf("'\n");
306}
307
308template <class Impl>
309void
310BaseDynInst<Impl>::dump(std::string &outstring)
311{
312    std::ostringstream s;
313    s << "T" << threadNumber << " : 0x" << PC << " "
314      << staticInst->disassemble(PC);
315
316    outstring = s.str();
317}
318
319template <class Impl>
320void
321BaseDynInst<Impl>::markSrcRegReady()
322{
323    if (++readyRegs == numSrcRegs()) {
324        setCanIssue();
325    }
326}
327
328template <class Impl>
329void
330BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
331{
332    _readySrcRegIdx[src_idx] = true;
333
334    markSrcRegReady();
335}
336
337template <class Impl>
338bool
339BaseDynInst<Impl>::eaSrcsReady()
340{
341    // For now I am assuming that src registers 1..n-1 are the ones that the
342    // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
343    // stored)
344
345    for (int i = 1; i < numSrcRegs(); ++i) {
346        if (!_readySrcRegIdx[i])
347            return false;
348    }
349
350    return true;
351}
352