base_dyn_inst_impl.hh revision 13590:d7e018859709 
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_BASE_DYN_INST_IMPL_HH__
44#define __CPU_BASE_DYN_INST_IMPL_HH__
45
46#include <iostream>
47#include <set>
48#include <sstream>
49#include <string>
50
51#include "base/cprintf.hh"
52#include "base/trace.hh"
53#include "config/the_isa.hh"
54#include "cpu/base_dyn_inst.hh"
55#include "cpu/exetrace.hh"
56#include "debug/DynInst.hh"
57#include "debug/IQ.hh"
58#include "mem/request.hh"
59#include "sim/faults.hh"
60
61template <class Impl>
62BaseDynInst<Impl>::BaseDynInst(const StaticInstPtr &_staticInst,
63                               const StaticInstPtr &_macroop,
64                               TheISA::PCState _pc, TheISA::PCState _predPC,
65                               InstSeqNum seq_num, ImplCPU *cpu)
66  : staticInst(_staticInst), cpu(cpu),
67    thread(nullptr),
68    traceData(nullptr),
69    macroop(_macroop),
70    memData(nullptr),
71    savedReq(nullptr),
72    reqToVerify(nullptr)
73{
74    seqNum = seq_num;
75
76    pc = _pc;
77    predPC = _predPC;
78
79    initVars();
80}
81
82template <class Impl>
83BaseDynInst<Impl>::BaseDynInst(const StaticInstPtr &_staticInst,
84                               const StaticInstPtr &_macroop)
85    : staticInst(_staticInst), traceData(NULL), macroop(_macroop)
86{
87    seqNum = 0;
88    initVars();
89}
90
91template <class Impl>
92void
93BaseDynInst<Impl>::initVars()
94{
95    memData = NULL;
96    effAddr = 0;
97    physEffAddr = 0;
98    readyRegs = 0;
99    memReqFlags = 0;
100
101    status.reset();
102
103    instFlags.reset();
104    instFlags[RecordResult] = true;
105    instFlags[Predicate] = true;
106
107    lqIdx = -1;
108    sqIdx = -1;
109
110    // Eventually make this a parameter.
111    threadNumber = 0;
112
113    // Also make this a parameter, or perhaps get it from xc or cpu.
114    asid = 0;
115
116    // Initialize the fault to be NoFault.
117    fault = NoFault;
118
119#ifndef NDEBUG
120    ++cpu->instcount;
121
122    if (cpu->instcount > 1500) {
123#ifdef DEBUG
124        cpu->dumpInsts();
125        dumpSNList();
126#endif
127        assert(cpu->instcount <= 1500);
128    }
129
130    DPRINTF(DynInst,
131        "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
132        seqNum, cpu->name(), cpu->instcount);
133#endif
134
135#ifdef DEBUG
136    cpu->snList.insert(seqNum);
137#endif
138
139}
140
141template <class Impl>
142BaseDynInst<Impl>::~BaseDynInst()
143{
144    if (memData) {
145        delete [] memData;
146    }
147
148    if (traceData) {
149        delete traceData;
150    }
151
152    fault = NoFault;
153
154#ifndef NDEBUG
155    --cpu->instcount;
156
157    DPRINTF(DynInst,
158        "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
159        seqNum, cpu->name(), cpu->instcount);
160#endif
161#ifdef DEBUG
162    cpu->snList.erase(seqNum);
163#endif
164
165}
166
167#ifdef DEBUG
168template <class Impl>
169void
170BaseDynInst<Impl>::dumpSNList()
171{
172    std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
173
174    int count = 0;
175    while (sn_it != cpu->snList.end()) {
176        cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
177        count++;
178        sn_it++;
179    }
180}
181#endif
182
183template <class Impl>
184void
185BaseDynInst<Impl>::dump()
186{
187    cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
188    std::cout << staticInst->disassemble(pc.instAddr());
189    cprintf("'\n");
190}
191
192template <class Impl>
193void
194BaseDynInst<Impl>::dump(std::string &outstring)
195{
196    std::ostringstream s;
197    s << "T" << threadNumber << " : 0x" << pc.instAddr() << " "
198      << staticInst->disassemble(pc.instAddr());
199
200    outstring = s.str();
201}
202
203template <class Impl>
204void
205BaseDynInst<Impl>::markSrcRegReady()
206{
207    DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
208            seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
209    if (++readyRegs == numSrcRegs()) {
210        setCanIssue();
211    }
212}
213
214template <class Impl>
215void
216BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
217{
218    _readySrcRegIdx[src_idx] = true;
219
220    markSrcRegReady();
221}
222
223template <class Impl>
224bool
225BaseDynInst<Impl>::eaSrcsReady() const
226{
227    // For now I am assuming that src registers 1..n-1 are the ones that the
228    // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
229    // stored)
230
231    for (int i = 1; i < numSrcRegs(); ++i) {
232        if (!_readySrcRegIdx[i])
233            return false;
234    }
235
236    return true;
237}
238
239#endif//__CPU_BASE_DYN_INST_IMPL_HH__
240