base_dyn_inst_impl.hh revision 13453:4a7a060ea26e 
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_BASE_DYN_INST_IMPL_HH__
44#define __CPU_BASE_DYN_INST_IMPL_HH__
45
46#include <iostream>
47#include <set>
48#include <sstream>
49#include <string>
50
51#include "base/cprintf.hh"
52#include "base/trace.hh"
53#include "config/the_isa.hh"
54#include "cpu/base_dyn_inst.hh"
55#include "cpu/exetrace.hh"
56#include "debug/DynInst.hh"
57#include "debug/IQ.hh"
58#include "mem/request.hh"
59#include "sim/faults.hh"
60
61template <class Impl>
62BaseDynInst<Impl>::BaseDynInst(const StaticInstPtr &_staticInst,
63                               const StaticInstPtr &_macroop,
64                               TheISA::PCState _pc, TheISA::PCState _predPC,
65                               InstSeqNum seq_num, ImplCPU *cpu)
66  : staticInst(_staticInst), cpu(cpu),
67    thread(nullptr),
68    traceData(nullptr),
69    macroop(_macroop),
70    memData(nullptr),
71    savedReq(nullptr),
72    savedSreqLow(nullptr),
73    savedSreqHigh(nullptr),
74    reqToVerify(nullptr)
75{
76    seqNum = seq_num;
77
78    pc = _pc;
79    predPC = _predPC;
80
81    initVars();
82}
83
84template <class Impl>
85BaseDynInst<Impl>::BaseDynInst(const StaticInstPtr &_staticInst,
86                               const StaticInstPtr &_macroop)
87    : staticInst(_staticInst), traceData(NULL), macroop(_macroop)
88{
89    seqNum = 0;
90    initVars();
91}
92
93template <class Impl>
94void
95BaseDynInst<Impl>::initVars()
96{
97    memData = NULL;
98    effAddr = 0;
99    physEffAddrLow = 0;
100    physEffAddrHigh = 0;
101    readyRegs = 0;
102    memReqFlags = 0;
103
104    status.reset();
105
106    instFlags.reset();
107    instFlags[RecordResult] = true;
108    instFlags[Predicate] = true;
109
110    lqIdx = -1;
111    sqIdx = -1;
112
113    // Eventually make this a parameter.
114    threadNumber = 0;
115
116    // Also make this a parameter, or perhaps get it from xc or cpu.
117    asid = 0;
118
119    // Initialize the fault to be NoFault.
120    fault = NoFault;
121
122#ifndef NDEBUG
123    ++cpu->instcount;
124
125    if (cpu->instcount > 1500) {
126#ifdef DEBUG
127        cpu->dumpInsts();
128        dumpSNList();
129#endif
130        assert(cpu->instcount <= 1500);
131    }
132
133    DPRINTF(DynInst,
134        "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
135        seqNum, cpu->name(), cpu->instcount);
136#endif
137
138#ifdef DEBUG
139    cpu->snList.insert(seqNum);
140#endif
141
142}
143
144template <class Impl>
145BaseDynInst<Impl>::~BaseDynInst()
146{
147    if (memData) {
148        delete [] memData;
149    }
150
151    if (traceData) {
152        delete traceData;
153    }
154
155    fault = NoFault;
156
157#ifndef NDEBUG
158    --cpu->instcount;
159
160    DPRINTF(DynInst,
161        "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
162        seqNum, cpu->name(), cpu->instcount);
163#endif
164#ifdef DEBUG
165    cpu->snList.erase(seqNum);
166#endif
167
168}
169
170#ifdef DEBUG
171template <class Impl>
172void
173BaseDynInst<Impl>::dumpSNList()
174{
175    std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
176
177    int count = 0;
178    while (sn_it != cpu->snList.end()) {
179        cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
180        count++;
181        sn_it++;
182    }
183}
184#endif
185
186template <class Impl>
187void
188BaseDynInst<Impl>::dump()
189{
190    cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
191    std::cout << staticInst->disassemble(pc.instAddr());
192    cprintf("'\n");
193}
194
195template <class Impl>
196void
197BaseDynInst<Impl>::dump(std::string &outstring)
198{
199    std::ostringstream s;
200    s << "T" << threadNumber << " : 0x" << pc.instAddr() << " "
201      << staticInst->disassemble(pc.instAddr());
202
203    outstring = s.str();
204}
205
206template <class Impl>
207void
208BaseDynInst<Impl>::markSrcRegReady()
209{
210    DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
211            seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
212    if (++readyRegs == numSrcRegs()) {
213        setCanIssue();
214    }
215}
216
217template <class Impl>
218void
219BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
220{
221    _readySrcRegIdx[src_idx] = true;
222
223    markSrcRegReady();
224}
225
226template <class Impl>
227bool
228BaseDynInst<Impl>::eaSrcsReady() const
229{
230    // For now I am assuming that src registers 1..n-1 are the ones that the
231    // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
232    // stored)
233
234    for (int i = 1; i < numSrcRegs(); ++i) {
235        if (!_readySrcRegIdx[i])
236            return false;
237    }
238
239    return true;
240}
241
242#endif//__CPU_BASE_DYN_INST_IMPL_HH__
243