base_dyn_inst.hh revision 9044
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * Copyright (c) 2009 The University of Edinburgh 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Timothy M. Jones 43 */ 44 45#ifndef __CPU_BASE_DYN_INST_HH__ 46#define __CPU_BASE_DYN_INST_HH__ 47 48#include <bitset> 49#include <list> 50#include <string> 51#include <queue> 52 53#include "arch/utility.hh" 54#include "base/trace.hh" 55#include "config/the_isa.hh" 56#include "cpu/checker/cpu.hh" 57#include "cpu/o3/comm.hh" 58#include "cpu/exetrace.hh" 59#include "cpu/inst_seq.hh" 60#include "cpu/op_class.hh" 61#include "cpu/static_inst.hh" 62#include "cpu/translation.hh" 63#include "mem/packet.hh" 64#include "sim/byteswap.hh" 65#include "sim/fault_fwd.hh" 66#include "sim/system.hh" 67#include "sim/tlb.hh" 68 69/** 70 * @file 71 * Defines a dynamic instruction context. 72 */ 73 74template <class Impl> 75class BaseDynInst : public RefCounted 76{ 77 public: 78 // Typedef for the CPU. 79 typedef typename Impl::CPUType ImplCPU; 80 typedef typename ImplCPU::ImplState ImplState; 81 82 // Logical register index type. 83 typedef TheISA::RegIndex RegIndex; 84 // Integer register type. 85 typedef TheISA::IntReg IntReg; 86 // Floating point register type. 87 typedef TheISA::FloatReg FloatReg; 88 89 // The DynInstPtr type. 90 typedef typename Impl::DynInstPtr DynInstPtr; 91 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 92 93 // The list of instructions iterator type. 94 typedef typename std::list<DynInstPtr>::iterator ListIt; 95 96 enum { 97 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 98 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs 99 }; 100 101 /** The StaticInst used by this BaseDynInst. */ 102 StaticInstPtr staticInst; 103 StaticInstPtr macroop; 104 105 //////////////////////////////////////////// 106 // 107 // INSTRUCTION EXECUTION 108 // 109 //////////////////////////////////////////// 110 /** InstRecord that tracks this instructions. */ 111 Trace::InstRecord *traceData; 112 113 void demapPage(Addr vaddr, uint64_t asn) 114 { 115 cpu->demapPage(vaddr, asn); 116 } 117 void demapInstPage(Addr vaddr, uint64_t asn) 118 { 119 cpu->demapPage(vaddr, asn); 120 } 121 void demapDataPage(Addr vaddr, uint64_t asn) 122 { 123 cpu->demapPage(vaddr, asn); 124 } 125 126 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 127 128 Fault writeMem(uint8_t *data, unsigned size, 129 Addr addr, unsigned flags, uint64_t *res); 130 131 /** Splits a request in two if it crosses a dcache block. */ 132 void splitRequest(RequestPtr req, RequestPtr &sreqLow, 133 RequestPtr &sreqHigh); 134 135 /** Initiate a DTB address translation. */ 136 void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 137 RequestPtr sreqHigh, uint64_t *res, 138 BaseTLB::Mode mode); 139 140 /** Finish a DTB address translation. */ 141 void finishTranslation(WholeTranslationState *state); 142 143 /** True if the DTB address translation has started. */ 144 bool translationStarted; 145 146 /** True if the DTB address translation has completed. */ 147 bool translationCompleted; 148 149 /** True if this address was found to match a previous load and they issued 150 * out of order. If that happend, then it's only a problem if an incoming 151 * snoop invalidate modifies the line, in which case we need to squash. 152 * If nothing modified the line the order doesn't matter. 153 */ 154 bool possibleLoadViolation; 155 156 /** True if the address hit a external snoop while sitting in the LSQ. 157 * If this is true and a older instruction sees it, this instruction must 158 * reexecute 159 */ 160 bool hitExternalSnoop; 161 162 /** 163 * Returns true if the DTB address translation is being delayed due to a hw 164 * page table walk. 165 */ 166 bool isTranslationDelayed() const 167 { 168 return (translationStarted && !translationCompleted); 169 } 170 171 /** 172 * Saved memory requests (needed when the DTB address translation is 173 * delayed due to a hw page table walk). 174 */ 175 RequestPtr savedReq; 176 RequestPtr savedSreqLow; 177 RequestPtr savedSreqHigh; 178 179 // Need a copy of main request pointer to verify on writes. 180 RequestPtr reqToVerify; 181 182 /** @todo: Consider making this private. */ 183 public: 184 /** The sequence number of the instruction. */ 185 InstSeqNum seqNum; 186 187 enum Status { 188 IqEntry, /// Instruction is in the IQ 189 RobEntry, /// Instruction is in the ROB 190 LsqEntry, /// Instruction is in the LSQ 191 Completed, /// Instruction has completed 192 ResultReady, /// Instruction has its result 193 CanIssue, /// Instruction can issue and execute 194 Issued, /// Instruction has issued 195 Executed, /// Instruction has executed 196 CanCommit, /// Instruction can commit 197 AtCommit, /// Instruction has reached commit 198 Committed, /// Instruction has committed 199 Squashed, /// Instruction is squashed 200 SquashedInIQ, /// Instruction is squashed in the IQ 201 SquashedInLSQ, /// Instruction is squashed in the LSQ 202 SquashedInROB, /// Instruction is squashed in the ROB 203 RecoverInst, /// Is a recover instruction 204 BlockingInst, /// Is a blocking instruction 205 ThreadsyncWait, /// Is a thread synchronization instruction 206 SerializeBefore, /// Needs to serialize on 207 /// instructions ahead of it 208 SerializeAfter, /// Needs to serialize instructions behind it 209 SerializeHandled, /// Serialization has been handled 210 NumStatus 211 }; 212 213 /** The status of this BaseDynInst. Several bits can be set. */ 214 std::bitset<NumStatus> status; 215 216 /** The thread this instruction is from. */ 217 ThreadID threadNumber; 218 219 /** data address space ID, for loads & stores. */ 220 short asid; 221 222 /** How many source registers are ready. */ 223 unsigned readyRegs; 224 225 /** Pointer to the Impl's CPU object. */ 226 ImplCPU *cpu; 227 228 /** Pointer to the thread state. */ 229 ImplState *thread; 230 231 /** The kind of fault this instruction has generated. */ 232 Fault fault; 233 234 /** Pointer to the data for the memory access. */ 235 uint8_t *memData; 236 237 /** The effective virtual address (lds & stores only). */ 238 Addr effAddr; 239 240 /** The size of the request */ 241 Addr effSize; 242 243 /** Is the effective virtual address valid. */ 244 bool effAddrValid; 245 246 /** The effective physical address. */ 247 Addr physEffAddr; 248 249 /** The memory request flags (from translation). */ 250 unsigned memReqFlags; 251 252 union Result { 253 uint64_t integer; 254 double dbl; 255 void set(uint64_t i) { integer = i; } 256 void set(double d) { dbl = d; } 257 void get(uint64_t& i) { i = integer; } 258 void get(double& d) { d = dbl; } 259 }; 260 261 /** The result of the instruction; assumes an instruction can have many 262 * destination registers. 263 */ 264 std::queue<Result> instResult; 265 266 /** Records changes to result? */ 267 bool recordResult; 268 269 /** Did this instruction execute, or is it predicated false */ 270 bool predicate; 271 272 protected: 273 /** PC state for this instruction. */ 274 TheISA::PCState pc; 275 276 /** Predicted PC state after this instruction. */ 277 TheISA::PCState predPC; 278 279 /** If this is a branch that was predicted taken */ 280 bool predTaken; 281 282 public: 283 284#ifdef DEBUG 285 void dumpSNList(); 286#endif 287 288 /** Whether or not the source register is ready. 289 * @todo: Not sure this should be here vs the derived class. 290 */ 291 bool _readySrcRegIdx[MaxInstSrcRegs]; 292 293 protected: 294 /** Flattened register index of the destination registers of this 295 * instruction. 296 */ 297 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 298 299 /** Flattened register index of the source registers of this 300 * instruction. 301 */ 302 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 303 304 /** Physical register index of the destination registers of this 305 * instruction. 306 */ 307 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 308 309 /** Physical register index of the source registers of this 310 * instruction. 311 */ 312 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 313 314 /** Physical register index of the previous producers of the 315 * architected destinations. 316 */ 317 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 318 319 public: 320 321 /** Returns the physical register index of the i'th destination 322 * register. 323 */ 324 PhysRegIndex renamedDestRegIdx(int idx) const 325 { 326 return _destRegIdx[idx]; 327 } 328 329 /** Returns the physical register index of the i'th source register. */ 330 PhysRegIndex renamedSrcRegIdx(int idx) const 331 { 332 return _srcRegIdx[idx]; 333 } 334 335 /** Returns the flattened register index of the i'th destination 336 * register. 337 */ 338 TheISA::RegIndex flattenedDestRegIdx(int idx) const 339 { 340 return _flatDestRegIdx[idx]; 341 } 342 343 /** Returns the flattened register index of the i'th source register */ 344 TheISA::RegIndex flattenedSrcRegIdx(int idx) const 345 { 346 return _flatSrcRegIdx[idx]; 347 } 348 349 /** Returns the physical register index of the previous physical register 350 * that remapped to the same logical register index. 351 */ 352 PhysRegIndex prevDestRegIdx(int idx) const 353 { 354 return _prevDestRegIdx[idx]; 355 } 356 357 /** Renames a destination register to a physical register. Also records 358 * the previous physical register that the logical register mapped to. 359 */ 360 void renameDestReg(int idx, 361 PhysRegIndex renamed_dest, 362 PhysRegIndex previous_rename) 363 { 364 _destRegIdx[idx] = renamed_dest; 365 _prevDestRegIdx[idx] = previous_rename; 366 } 367 368 /** Renames a source logical register to the physical register which 369 * has/will produce that logical register's result. 370 * @todo: add in whether or not the source register is ready. 371 */ 372 void renameSrcReg(int idx, PhysRegIndex renamed_src) 373 { 374 _srcRegIdx[idx] = renamed_src; 375 } 376 377 /** Flattens a source architectural register index into a logical index. 378 */ 379 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 380 { 381 _flatSrcRegIdx[idx] = flattened_src; 382 } 383 384 /** Flattens a destination architectural register index into a logical 385 * index. 386 */ 387 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 388 { 389 _flatDestRegIdx[idx] = flattened_dest; 390 } 391 /** BaseDynInst constructor given a binary instruction. 392 * @param staticInst A StaticInstPtr to the underlying instruction. 393 * @param pc The PC state for the instruction. 394 * @param predPC The predicted next PC state for the instruction. 395 * @param seq_num The sequence number of the instruction. 396 * @param cpu Pointer to the instruction's CPU. 397 */ 398 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop, 399 TheISA::PCState pc, TheISA::PCState predPC, 400 InstSeqNum seq_num, ImplCPU *cpu); 401 402 /** BaseDynInst constructor given a StaticInst pointer. 403 * @param _staticInst The StaticInst for this BaseDynInst. 404 */ 405 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop); 406 407 /** BaseDynInst destructor. */ 408 ~BaseDynInst(); 409 410 private: 411 /** Function to initialize variables in the constructors. */ 412 void initVars(); 413 414 public: 415 /** Dumps out contents of this BaseDynInst. */ 416 void dump(); 417 418 /** Dumps out contents of this BaseDynInst into given string. */ 419 void dump(std::string &outstring); 420 421 /** Read this CPU's ID. */ 422 int cpuId() { return cpu->cpuId(); } 423 424 /** Read this CPU's data requestor ID */ 425 MasterID masterId() { return cpu->dataMasterId(); } 426 427 /** Read this context's system-wide ID **/ 428 int contextId() { return thread->contextId(); } 429 430 /** Returns the fault type. */ 431 Fault getFault() { return fault; } 432 433 /** Checks whether or not this instruction has had its branch target 434 * calculated yet. For now it is not utilized and is hacked to be 435 * always false. 436 * @todo: Actually use this instruction. 437 */ 438 bool doneTargCalc() { return false; } 439 440 /** Set the predicted target of this current instruction. */ 441 void setPredTarg(const TheISA::PCState &_predPC) 442 { 443 predPC = _predPC; 444 } 445 446 const TheISA::PCState &readPredTarg() { return predPC; } 447 448 /** Returns the predicted PC immediately after the branch. */ 449 Addr predInstAddr() { return predPC.instAddr(); } 450 451 /** Returns the predicted PC two instructions after the branch */ 452 Addr predNextInstAddr() { return predPC.nextInstAddr(); } 453 454 /** Returns the predicted micro PC after the branch */ 455 Addr predMicroPC() { return predPC.microPC(); } 456 457 /** Returns whether the instruction was predicted taken or not. */ 458 bool readPredTaken() 459 { 460 return predTaken; 461 } 462 463 void setPredTaken(bool predicted_taken) 464 { 465 predTaken = predicted_taken; 466 } 467 468 /** Returns whether the instruction mispredicted. */ 469 bool mispredicted() 470 { 471 TheISA::PCState tempPC = pc; 472 TheISA::advancePC(tempPC, staticInst); 473 return !(tempPC == predPC); 474 } 475 476 // 477 // Instruction types. Forward checks to StaticInst object. 478 // 479 bool isNop() const { return staticInst->isNop(); } 480 bool isMemRef() const { return staticInst->isMemRef(); } 481 bool isLoad() const { return staticInst->isLoad(); } 482 bool isStore() const { return staticInst->isStore(); } 483 bool isStoreConditional() const 484 { return staticInst->isStoreConditional(); } 485 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 486 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 487 bool isInteger() const { return staticInst->isInteger(); } 488 bool isFloating() const { return staticInst->isFloating(); } 489 bool isControl() const { return staticInst->isControl(); } 490 bool isCall() const { return staticInst->isCall(); } 491 bool isReturn() const { return staticInst->isReturn(); } 492 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 493 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 494 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 495 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 496 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 497 bool isThreadSync() const { return staticInst->isThreadSync(); } 498 bool isSerializing() const { return staticInst->isSerializing(); } 499 bool isSerializeBefore() const 500 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 501 bool isSerializeAfter() const 502 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 503 bool isSquashAfter() const { return staticInst->isSquashAfter(); } 504 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 505 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 506 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 507 bool isQuiesce() const { return staticInst->isQuiesce(); } 508 bool isIprAccess() const { return staticInst->isIprAccess(); } 509 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 510 bool isSyscall() const { return staticInst->isSyscall(); } 511 bool isMacroop() const { return staticInst->isMacroop(); } 512 bool isMicroop() const { return staticInst->isMicroop(); } 513 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 514 bool isLastMicroop() const { return staticInst->isLastMicroop(); } 515 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 516 bool isMicroBranch() const { return staticInst->isMicroBranch(); } 517 518 /** Temporarily sets this instruction as a serialize before instruction. */ 519 void setSerializeBefore() { status.set(SerializeBefore); } 520 521 /** Clears the serializeBefore part of this instruction. */ 522 void clearSerializeBefore() { status.reset(SerializeBefore); } 523 524 /** Checks if this serializeBefore is only temporarily set. */ 525 bool isTempSerializeBefore() { return status[SerializeBefore]; } 526 527 /** Temporarily sets this instruction as a serialize after instruction. */ 528 void setSerializeAfter() { status.set(SerializeAfter); } 529 530 /** Clears the serializeAfter part of this instruction.*/ 531 void clearSerializeAfter() { status.reset(SerializeAfter); } 532 533 /** Checks if this serializeAfter is only temporarily set. */ 534 bool isTempSerializeAfter() { return status[SerializeAfter]; } 535 536 /** Sets the serialization part of this instruction as handled. */ 537 void setSerializeHandled() { status.set(SerializeHandled); } 538 539 /** Checks if the serialization part of this instruction has been 540 * handled. This does not apply to the temporary serializing 541 * state; it only applies to this instruction's own permanent 542 * serializing state. 543 */ 544 bool isSerializeHandled() { return status[SerializeHandled]; } 545 546 /** Returns the opclass of this instruction. */ 547 OpClass opClass() const { return staticInst->opClass(); } 548 549 /** Returns the branch target address. */ 550 TheISA::PCState branchTarget() const 551 { return staticInst->branchTarget(pc); } 552 553 /** Returns the number of source registers. */ 554 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 555 556 /** Returns the number of destination registers. */ 557 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 558 559 // the following are used to track physical register usage 560 // for machines with separate int & FP reg files 561 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 562 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 563 564 /** Returns the logical register index of the i'th destination register. */ 565 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 566 567 /** Returns the logical register index of the i'th source register. */ 568 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 569 570 /** Pops a result off the instResult queue */ 571 template <class T> 572 void popResult(T& t) 573 { 574 if (!instResult.empty()) { 575 instResult.front().get(t); 576 instResult.pop(); 577 } 578 } 579 580 /** Read the most recent result stored by this instruction */ 581 template <class T> 582 void readResult(T& t) 583 { 584 instResult.back().get(t); 585 } 586 587 /** Pushes a result onto the instResult queue */ 588 template <class T> 589 void setResult(T t) 590 { 591 if (recordResult) { 592 Result instRes; 593 instRes.set(t); 594 instResult.push(instRes); 595 } 596 } 597 598 /** Records an integer register being set to a value. */ 599 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 600 { 601 setResult<uint64_t>(val); 602 } 603 604 /** Records an fp register being set to a value. */ 605 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 606 int width) 607 { 608 if (width == 32 || width == 64) { 609 setResult<double>(val); 610 } else { 611 panic("Unsupported width!"); 612 } 613 } 614 615 /** Records an fp register being set to a value. */ 616 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 617 { 618 setResult<double>(val); 619 } 620 621 /** Records an fp register being set to an integer value. */ 622 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 623 int width) 624 { 625 setResult<uint64_t>(val); 626 } 627 628 /** Records an fp register being set to an integer value. */ 629 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 630 { 631 setResult<uint64_t>(val); 632 } 633 634 /** Records that one of the source registers is ready. */ 635 void markSrcRegReady(); 636 637 /** Marks a specific register as ready. */ 638 void markSrcRegReady(RegIndex src_idx); 639 640 /** Returns if a source register is ready. */ 641 bool isReadySrcRegIdx(int idx) const 642 { 643 return this->_readySrcRegIdx[idx]; 644 } 645 646 /** Sets this instruction as completed. */ 647 void setCompleted() { status.set(Completed); } 648 649 /** Returns whether or not this instruction is completed. */ 650 bool isCompleted() const { return status[Completed]; } 651 652 /** Marks the result as ready. */ 653 void setResultReady() { status.set(ResultReady); } 654 655 /** Returns whether or not the result is ready. */ 656 bool isResultReady() const { return status[ResultReady]; } 657 658 /** Sets this instruction as ready to issue. */ 659 void setCanIssue() { status.set(CanIssue); } 660 661 /** Returns whether or not this instruction is ready to issue. */ 662 bool readyToIssue() const { return status[CanIssue]; } 663 664 /** Clears this instruction being able to issue. */ 665 void clearCanIssue() { status.reset(CanIssue); } 666 667 /** Sets this instruction as issued from the IQ. */ 668 void setIssued() { status.set(Issued); } 669 670 /** Returns whether or not this instruction has issued. */ 671 bool isIssued() const { return status[Issued]; } 672 673 /** Clears this instruction as being issued. */ 674 void clearIssued() { status.reset(Issued); } 675 676 /** Sets this instruction as executed. */ 677 void setExecuted() { status.set(Executed); } 678 679 /** Returns whether or not this instruction has executed. */ 680 bool isExecuted() const { return status[Executed]; } 681 682 /** Sets this instruction as ready to commit. */ 683 void setCanCommit() { status.set(CanCommit); } 684 685 /** Clears this instruction as being ready to commit. */ 686 void clearCanCommit() { status.reset(CanCommit); } 687 688 /** Returns whether or not this instruction is ready to commit. */ 689 bool readyToCommit() const { return status[CanCommit]; } 690 691 void setAtCommit() { status.set(AtCommit); } 692 693 bool isAtCommit() { return status[AtCommit]; } 694 695 /** Sets this instruction as committed. */ 696 void setCommitted() { status.set(Committed); } 697 698 /** Returns whether or not this instruction is committed. */ 699 bool isCommitted() const { return status[Committed]; } 700 701 /** Sets this instruction as squashed. */ 702 void setSquashed() { status.set(Squashed); } 703 704 /** Returns whether or not this instruction is squashed. */ 705 bool isSquashed() const { return status[Squashed]; } 706 707 //Instruction Queue Entry 708 //----------------------- 709 /** Sets this instruction as a entry the IQ. */ 710 void setInIQ() { status.set(IqEntry); } 711 712 /** Sets this instruction as a entry the IQ. */ 713 void clearInIQ() { status.reset(IqEntry); } 714 715 /** Returns whether or not this instruction has issued. */ 716 bool isInIQ() const { return status[IqEntry]; } 717 718 /** Sets this instruction as squashed in the IQ. */ 719 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 720 721 /** Returns whether or not this instruction is squashed in the IQ. */ 722 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 723 724 725 //Load / Store Queue Functions 726 //----------------------- 727 /** Sets this instruction as a entry the LSQ. */ 728 void setInLSQ() { status.set(LsqEntry); } 729 730 /** Sets this instruction as a entry the LSQ. */ 731 void removeInLSQ() { status.reset(LsqEntry); } 732 733 /** Returns whether or not this instruction is in the LSQ. */ 734 bool isInLSQ() const { return status[LsqEntry]; } 735 736 /** Sets this instruction as squashed in the LSQ. */ 737 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 738 739 /** Returns whether or not this instruction is squashed in the LSQ. */ 740 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 741 742 743 //Reorder Buffer Functions 744 //----------------------- 745 /** Sets this instruction as a entry the ROB. */ 746 void setInROB() { status.set(RobEntry); } 747 748 /** Sets this instruction as a entry the ROB. */ 749 void clearInROB() { status.reset(RobEntry); } 750 751 /** Returns whether or not this instruction is in the ROB. */ 752 bool isInROB() const { return status[RobEntry]; } 753 754 /** Sets this instruction as squashed in the ROB. */ 755 void setSquashedInROB() { status.set(SquashedInROB); } 756 757 /** Returns whether or not this instruction is squashed in the ROB. */ 758 bool isSquashedInROB() const { return status[SquashedInROB]; } 759 760 /** Read the PC state of this instruction. */ 761 const TheISA::PCState pcState() const { return pc; } 762 763 /** Set the PC state of this instruction. */ 764 const void pcState(const TheISA::PCState &val) { pc = val; } 765 766 /** Read the PC of this instruction. */ 767 const Addr instAddr() const { return pc.instAddr(); } 768 769 /** Read the PC of the next instruction. */ 770 const Addr nextInstAddr() const { return pc.nextInstAddr(); } 771 772 /**Read the micro PC of this instruction. */ 773 const Addr microPC() const { return pc.microPC(); } 774 775 bool readPredicate() 776 { 777 return predicate; 778 } 779 780 void setPredicate(bool val) 781 { 782 predicate = val; 783 784 if (traceData) { 785 traceData->setPredicate(val); 786 } 787 } 788 789 /** Sets the ASID. */ 790 void setASID(short addr_space_id) { asid = addr_space_id; } 791 792 /** Sets the thread id. */ 793 void setTid(ThreadID tid) { threadNumber = tid; } 794 795 /** Sets the pointer to the thread state. */ 796 void setThreadState(ImplState *state) { thread = state; } 797 798 /** Returns the thread context. */ 799 ThreadContext *tcBase() { return thread->getTC(); } 800 801 private: 802 /** Instruction effective address. 803 * @todo: Consider if this is necessary or not. 804 */ 805 Addr instEffAddr; 806 807 /** Whether or not the effective address calculation is completed. 808 * @todo: Consider if this is necessary or not. 809 */ 810 bool eaCalcDone; 811 812 /** Is this instruction's memory access uncacheable. */ 813 bool isUncacheable; 814 815 /** Has this instruction generated a memory request. */ 816 bool reqMade; 817 818 public: 819 /** Sets the effective address. */ 820 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 821 822 /** Returns the effective address. */ 823 const Addr &getEA() const { return instEffAddr; } 824 825 /** Returns whether or not the eff. addr. calculation has been completed. */ 826 bool doneEACalc() { return eaCalcDone; } 827 828 /** Returns whether or not the eff. addr. source registers are ready. */ 829 bool eaSrcsReady(); 830 831 /** Whether or not the memory operation is done. */ 832 bool memOpDone; 833 834 /** Is this instruction's memory access uncacheable. */ 835 bool uncacheable() { return isUncacheable; } 836 837 /** Has this instruction generated a memory request. */ 838 bool hasRequest() { return reqMade; } 839 840 public: 841 /** Load queue index. */ 842 int16_t lqIdx; 843 844 /** Store queue index. */ 845 int16_t sqIdx; 846 847 /** Iterator pointing to this BaseDynInst in the list of all insts. */ 848 ListIt instListIt; 849 850 /** Returns iterator to this instruction in the list of all insts. */ 851 ListIt &getInstListIt() { return instListIt; } 852 853 /** Sets iterator for this instruction in the list of all insts. */ 854 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 855 856 public: 857 /** Returns the number of consecutive store conditional failures. */ 858 unsigned readStCondFailures() 859 { return thread->storeCondFailures; } 860 861 /** Sets the number of consecutive store conditional failures. */ 862 void setStCondFailures(unsigned sc_failures) 863 { thread->storeCondFailures = sc_failures; } 864}; 865 866template<class Impl> 867Fault 868BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data, 869 unsigned size, unsigned flags) 870{ 871 reqMade = true; 872 Request *req = NULL; 873 Request *sreqLow = NULL; 874 Request *sreqHigh = NULL; 875 876 if (reqMade && translationStarted) { 877 req = savedReq; 878 sreqLow = savedSreqLow; 879 sreqHigh = savedSreqHigh; 880 } else { 881 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), 882 thread->contextId(), threadNumber); 883 884 // Only split the request if the ISA supports unaligned accesses. 885 if (TheISA::HasUnalignedMemAcc) { 886 splitRequest(req, sreqLow, sreqHigh); 887 } 888 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 889 } 890 891 if (translationCompleted) { 892 if (fault == NoFault) { 893 effAddr = req->getVaddr(); 894 effSize = size; 895 effAddrValid = true; 896 897 if (cpu->checker) { 898 if (reqToVerify != NULL) { 899 delete reqToVerify; 900 } 901 reqToVerify = new Request(*req); 902 } 903 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); 904 } else { 905 // Commit will have to clean up whatever happened. Set this 906 // instruction as executed. 907 this->setExecuted(); 908 } 909 910 if (fault != NoFault) { 911 // Return a fixed value to keep simulation deterministic even 912 // along misspeculated paths. 913 if (data) 914 bzero(data, size); 915 } 916 } 917 918 if (traceData) { 919 traceData->setAddr(addr); 920 } 921 922 return fault; 923} 924 925template<class Impl> 926Fault 927BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, 928 Addr addr, unsigned flags, uint64_t *res) 929{ 930 if (traceData) { 931 traceData->setAddr(addr); 932 } 933 934 reqMade = true; 935 Request *req = NULL; 936 Request *sreqLow = NULL; 937 Request *sreqHigh = NULL; 938 939 if (reqMade && translationStarted) { 940 req = savedReq; 941 sreqLow = savedSreqLow; 942 sreqHigh = savedSreqHigh; 943 } else { 944 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), 945 thread->contextId(), threadNumber); 946 947 // Only split the request if the ISA supports unaligned accesses. 948 if (TheISA::HasUnalignedMemAcc) { 949 splitRequest(req, sreqLow, sreqHigh); 950 } 951 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 952 } 953 954 if (fault == NoFault && translationCompleted) { 955 effAddr = req->getVaddr(); 956 effSize = size; 957 effAddrValid = true; 958 959 if (cpu->checker) { 960 if (reqToVerify != NULL) { 961 delete reqToVerify; 962 } 963 reqToVerify = new Request(*req); 964 } 965 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 966 } 967 968 return fault; 969} 970 971template<class Impl> 972inline void 973BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 974 RequestPtr &sreqHigh) 975{ 976 // Check to see if the request crosses the next level block boundary. 977 unsigned block_size = cpu->getDataPort().peerBlockSize(); 978 Addr addr = req->getVaddr(); 979 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 980 assert(split_addr <= addr || split_addr - addr < block_size); 981 982 // Spans two blocks. 983 if (split_addr > addr) { 984 req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 985 } 986} 987 988template<class Impl> 989inline void 990BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 991 RequestPtr sreqHigh, uint64_t *res, 992 BaseTLB::Mode mode) 993{ 994 translationStarted = true; 995 996 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 997 WholeTranslationState *state = 998 new WholeTranslationState(req, NULL, res, mode); 999 1000 // One translation if the request isn't split. 1001 DataTranslation<BaseDynInstPtr> *trans = 1002 new DataTranslation<BaseDynInstPtr>(this, state); 1003 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 1004 if (!translationCompleted) { 1005 // Save memory requests. 1006 savedReq = state->mainReq; 1007 savedSreqLow = state->sreqLow; 1008 savedSreqHigh = state->sreqHigh; 1009 } 1010 } else { 1011 WholeTranslationState *state = 1012 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 1013 1014 // Two translations when the request is split. 1015 DataTranslation<BaseDynInstPtr> *stransLow = 1016 new DataTranslation<BaseDynInstPtr>(this, state, 0); 1017 DataTranslation<BaseDynInstPtr> *stransHigh = 1018 new DataTranslation<BaseDynInstPtr>(this, state, 1); 1019 1020 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 1021 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 1022 if (!translationCompleted) { 1023 // Save memory requests. 1024 savedReq = state->mainReq; 1025 savedSreqLow = state->sreqLow; 1026 savedSreqHigh = state->sreqHigh; 1027 } 1028 } 1029} 1030 1031template<class Impl> 1032inline void 1033BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 1034{ 1035 fault = state->getFault(); 1036 1037 if (state->isUncacheable()) 1038 isUncacheable = true; 1039 1040 if (fault == NoFault) { 1041 physEffAddr = state->getPaddr(); 1042 memReqFlags = state->getFlags(); 1043 1044 if (state->mainReq->isCondSwap()) { 1045 assert(state->res); 1046 state->mainReq->setExtraData(*state->res); 1047 } 1048 1049 } else { 1050 state->deleteReqs(); 1051 } 1052 delete state; 1053 1054 translationCompleted = true; 1055} 1056 1057#endif // __CPU_BASE_DYN_INST_HH__ 1058