base_dyn_inst.hh revision 2935:d1223a6c9156
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_BASE_DYN_INST_HH__ 32#define __CPU_BASE_DYN_INST_HH__ 33 34#include <bitset> 35#include <list> 36#include <string> 37 38#include "arch/faults.hh" 39#include "base/fast_alloc.hh" 40#include "base/trace.hh" 41#include "config/full_system.hh" 42#include "cpu/exetrace.hh" 43#include "cpu/inst_seq.hh" 44#include "cpu/op_class.hh" 45#include "cpu/static_inst.hh" 46#include "mem/packet.hh" 47#include "sim/system.hh" 48 49/** 50 * @file 51 * Defines a dynamic instruction context. 52 */ 53 54// Forward declaration. 55class StaticInstPtr; 56 57template <class Impl> 58class BaseDynInst : public FastAlloc, public RefCounted 59{ 60 public: 61 // Typedef for the CPU. 62 typedef typename Impl::CPUType ImplCPU; 63 typedef typename ImplCPU::ImplState ImplState; 64 65 // Binary machine instruction type. 66 typedef TheISA::MachInst MachInst; 67 // Extended machine instruction type 68 typedef TheISA::ExtMachInst ExtMachInst; 69 // Logical register index type. 70 typedef TheISA::RegIndex RegIndex; 71 // Integer register type. 72 typedef TheISA::IntReg IntReg; 73 // Floating point register type. 74 typedef TheISA::FloatReg FloatReg; 75 76 // The DynInstPtr type. 77 typedef typename Impl::DynInstPtr DynInstPtr; 78 79 // The list of instructions iterator type. 80 typedef typename std::list<DynInstPtr>::iterator ListIt; 81 82 enum { 83 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 84 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 85 }; 86 87 /** The StaticInst used by this BaseDynInst. */ 88 StaticInstPtr staticInst; 89 90 //////////////////////////////////////////// 91 // 92 // INSTRUCTION EXECUTION 93 // 94 //////////////////////////////////////////// 95 /** InstRecord that tracks this instructions. */ 96 Trace::InstRecord *traceData; 97 98 /** 99 * Does a read to a given address. 100 * @param addr The address to read. 101 * @param data The read's data is written into this parameter. 102 * @param flags The request's flags. 103 * @return Returns any fault due to the read. 104 */ 105 template <class T> 106 Fault read(Addr addr, T &data, unsigned flags); 107 108 /** 109 * Does a write to a given address. 110 * @param data The data to be written. 111 * @param addr The address to write to. 112 * @param flags The request's flags. 113 * @param res The result of the write (for load locked/store conditionals). 114 * @return Returns any fault due to the write. 115 */ 116 template <class T> 117 Fault write(T data, Addr addr, unsigned flags, 118 uint64_t *res); 119 120 void prefetch(Addr addr, unsigned flags); 121 void writeHint(Addr addr, int size, unsigned flags); 122 Fault copySrcTranslate(Addr src); 123 Fault copy(Addr dest); 124 125 /** @todo: Consider making this private. */ 126 public: 127 /** The sequence number of the instruction. */ 128 InstSeqNum seqNum; 129 130 enum Status { 131 IqEntry, /// Instruction is in the IQ 132 RobEntry, /// Instruction is in the ROB 133 LsqEntry, /// Instruction is in the LSQ 134 Completed, /// Instruction has completed 135 ResultReady, /// Instruction has its result 136 CanIssue, /// Instruction can issue and execute 137 Issued, /// Instruction has issued 138 Executed, /// Instruction has executed 139 CanCommit, /// Instruction can commit 140 AtCommit, /// Instruction has reached commit 141 Committed, /// Instruction has committed 142 Squashed, /// Instruction is squashed 143 SquashedInIQ, /// Instruction is squashed in the IQ 144 SquashedInLSQ, /// Instruction is squashed in the LSQ 145 SquashedInROB, /// Instruction is squashed in the ROB 146 RecoverInst, /// Is a recover instruction 147 BlockingInst, /// Is a blocking instruction 148 ThreadsyncWait, /// Is a thread synchronization instruction 149 SerializeBefore, /// Needs to serialize on 150 /// instructions ahead of it 151 SerializeAfter, /// Needs to serialize instructions behind it 152 SerializeHandled, /// Serialization has been handled 153 NumStatus 154 }; 155 156 /** The status of this BaseDynInst. Several bits can be set. */ 157 std::bitset<NumStatus> status; 158 159 /** The thread this instruction is from. */ 160 short threadNumber; 161 162 /** data address space ID, for loads & stores. */ 163 short asid; 164 165 /** How many source registers are ready. */ 166 unsigned readyRegs; 167 168 /** Pointer to the Impl's CPU object. */ 169 ImplCPU *cpu; 170 171 /** Pointer to the thread state. */ 172 ImplState *thread; 173 174 /** The kind of fault this instruction has generated. */ 175 Fault fault; 176 177 /** The memory request. */ 178 Request *req; 179 180 /** Pointer to the data for the memory access. */ 181 uint8_t *memData; 182 183 /** The effective virtual address (lds & stores only). */ 184 Addr effAddr; 185 186 /** The effective physical address. */ 187 Addr physEffAddr; 188 189 /** Effective virtual address for a copy source. */ 190 Addr copySrcEffAddr; 191 192 /** Effective physical address for a copy source. */ 193 Addr copySrcPhysEffAddr; 194 195 /** The memory request flags (from translation). */ 196 unsigned memReqFlags; 197 198 union Result { 199 uint64_t integer; 200 float fp; 201 double dbl; 202 }; 203 204 /** The result of the instruction; assumes for now that there's only one 205 * destination register. 206 */ 207 Result instResult; 208 209 /** PC of this instruction. */ 210 Addr PC; 211 212 /** Next non-speculative PC. It is not filled in at fetch, but rather 213 * once the target of the branch is truly known (either decode or 214 * execute). 215 */ 216 Addr nextPC; 217 218 /** Next non-speculative NPC. Target PC for Mips or Sparc. */ 219 Addr nextNPC; 220 221 /** Predicted next PC. */ 222 Addr predPC; 223 224 /** Count of total number of dynamic instructions. */ 225 static int instcount; 226 227#ifdef DEBUG 228 void dumpSNList(); 229#endif 230 231 /** Whether or not the source register is ready. 232 * @todo: Not sure this should be here vs the derived class. 233 */ 234 bool _readySrcRegIdx[MaxInstSrcRegs]; 235 236 public: 237 /** BaseDynInst constructor given a binary instruction. 238 * @param inst The binary instruction. 239 * @param PC The PC of the instruction. 240 * @param pred_PC The predicted next PC. 241 * @param seq_num The sequence number of the instruction. 242 * @param cpu Pointer to the instruction's CPU. 243 */ 244 BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num, 245 ImplCPU *cpu); 246 247 /** BaseDynInst constructor given a StaticInst pointer. 248 * @param _staticInst The StaticInst for this BaseDynInst. 249 */ 250 BaseDynInst(StaticInstPtr &_staticInst); 251 252 /** BaseDynInst destructor. */ 253 ~BaseDynInst(); 254 255 private: 256 /** Function to initialize variables in the constructors. */ 257 void initVars(); 258 259 public: 260 /** Dumps out contents of this BaseDynInst. */ 261 void dump(); 262 263 /** Dumps out contents of this BaseDynInst into given string. */ 264 void dump(std::string &outstring); 265 266 /** Returns the fault type. */ 267 Fault getFault() { return fault; } 268 269 /** Checks whether or not this instruction has had its branch target 270 * calculated yet. For now it is not utilized and is hacked to be 271 * always false. 272 * @todo: Actually use this instruction. 273 */ 274 bool doneTargCalc() { return false; } 275 276 /** Returns the next PC. This could be the speculative next PC if it is 277 * called prior to the actual branch target being calculated. 278 */ 279 Addr readNextPC() { return nextPC; } 280 281 /** Returns the next NPC. This could be the speculative next NPC if it is 282 * called prior to the actual branch target being calculated. 283 */ 284 Addr readNextNPC() { return nextNPC; } 285 286 /** Set the predicted target of this current instruction. */ 287 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; } 288 289 /** Returns the predicted target of the branch. */ 290 Addr readPredTarg() { return predPC; } 291 292 /** Returns whether the instruction was predicted taken or not. */ 293 bool predTaken() 294#if THE_ISA == ALPHA_ISA 295 { return predPC != (PC + sizeof(MachInst)); } 296#else 297 { return predPC != (nextPC + sizeof(MachInst)); } 298#endif 299 300 /** Returns whether the instruction mispredicted. */ 301 bool mispredicted() 302#if THE_ISA == ALPHA_ISA 303 { return predPC != nextPC; } 304#else 305 { return predPC != nextNPC; } 306#endif 307 // 308 // Instruction types. Forward checks to StaticInst object. 309 // 310 bool isNop() const { return staticInst->isNop(); } 311 bool isMemRef() const { return staticInst->isMemRef(); } 312 bool isLoad() const { return staticInst->isLoad(); } 313 bool isStore() const { return staticInst->isStore(); } 314 bool isStoreConditional() const 315 { return staticInst->isStoreConditional(); } 316 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 317 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 318 bool isCopy() const { return staticInst->isCopy(); } 319 bool isInteger() const { return staticInst->isInteger(); } 320 bool isFloating() const { return staticInst->isFloating(); } 321 bool isControl() const { return staticInst->isControl(); } 322 bool isCall() const { return staticInst->isCall(); } 323 bool isReturn() const { return staticInst->isReturn(); } 324 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 325 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 326 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 327 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 328 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 329 bool isThreadSync() const { return staticInst->isThreadSync(); } 330 bool isSerializing() const { return staticInst->isSerializing(); } 331 bool isSerializeBefore() const 332 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 333 bool isSerializeAfter() const 334 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 335 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 336 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 337 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 338 bool isQuiesce() const { return staticInst->isQuiesce(); } 339 bool isIprAccess() const { return staticInst->isIprAccess(); } 340 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 341 342 /** Temporarily sets this instruction as a serialize before instruction. */ 343 void setSerializeBefore() { status.set(SerializeBefore); } 344 345 /** Clears the serializeBefore part of this instruction. */ 346 void clearSerializeBefore() { status.reset(SerializeBefore); } 347 348 /** Checks if this serializeBefore is only temporarily set. */ 349 bool isTempSerializeBefore() { return status[SerializeBefore]; } 350 351 /** Temporarily sets this instruction as a serialize after instruction. */ 352 void setSerializeAfter() { status.set(SerializeAfter); } 353 354 /** Clears the serializeAfter part of this instruction.*/ 355 void clearSerializeAfter() { status.reset(SerializeAfter); } 356 357 /** Checks if this serializeAfter is only temporarily set. */ 358 bool isTempSerializeAfter() { return status[SerializeAfter]; } 359 360 /** Sets the serialization part of this instruction as handled. */ 361 void setSerializeHandled() { status.set(SerializeHandled); } 362 363 /** Checks if the serialization part of this instruction has been 364 * handled. This does not apply to the temporary serializing 365 * state; it only applies to this instruction's own permanent 366 * serializing state. 367 */ 368 bool isSerializeHandled() { return status[SerializeHandled]; } 369 370 /** Returns the opclass of this instruction. */ 371 OpClass opClass() const { return staticInst->opClass(); } 372 373 /** Returns the branch target address. */ 374 Addr branchTarget() const { return staticInst->branchTarget(PC); } 375 376 /** Returns the number of source registers. */ 377 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 378 379 /** Returns the number of destination registers. */ 380 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 381 382 // the following are used to track physical register usage 383 // for machines with separate int & FP reg files 384 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 385 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 386 387 /** Returns the logical register index of the i'th destination register. */ 388 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 389 390 /** Returns the logical register index of the i'th source register. */ 391 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 392 393 /** Returns the result of an integer instruction. */ 394 uint64_t readIntResult() { return instResult.integer; } 395 396 /** Returns the result of a floating point instruction. */ 397 float readFloatResult() { return instResult.fp; } 398 399 /** Returns the result of a floating point (double) instruction. */ 400 double readDoubleResult() { return instResult.dbl; } 401 402 /** Records an integer register being set to a value. */ 403 void setIntReg(const StaticInst *si, int idx, uint64_t val) 404 { 405 instResult.integer = val; 406 } 407 408 /** Records an fp register being set to a value. */ 409 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width) 410 { 411 if (width == 32) 412 instResult.fp = val; 413 else if (width == 64) 414 instResult.dbl = val; 415 else 416 panic("Unsupported width!"); 417 } 418 419 /** Records an fp register being set to a value. */ 420 void setFloatReg(const StaticInst *si, int idx, FloatReg val) 421 { 422 instResult.fp = val; 423 } 424 425 /** Records an fp register being set to an integer value. */ 426 void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width) 427 { 428 instResult.integer = val; 429 } 430 431 /** Records an fp register being set to an integer value. */ 432 void setFloatRegBits(const StaticInst *si, int idx, uint64_t val) 433 { 434 instResult.integer = val; 435 } 436 437 /** Records that one of the source registers is ready. */ 438 void markSrcRegReady(); 439 440 /** Marks a specific register as ready. */ 441 void markSrcRegReady(RegIndex src_idx); 442 443 /** Returns if a source register is ready. */ 444 bool isReadySrcRegIdx(int idx) const 445 { 446 return this->_readySrcRegIdx[idx]; 447 } 448 449 /** Sets this instruction as completed. */ 450 void setCompleted() { status.set(Completed); } 451 452 /** Returns whether or not this instruction is completed. */ 453 bool isCompleted() const { return status[Completed]; } 454 455 /** Marks the result as ready. */ 456 void setResultReady() { status.set(ResultReady); } 457 458 /** Returns whether or not the result is ready. */ 459 bool isResultReady() const { return status[ResultReady]; } 460 461 /** Sets this instruction as ready to issue. */ 462 void setCanIssue() { status.set(CanIssue); } 463 464 /** Returns whether or not this instruction is ready to issue. */ 465 bool readyToIssue() const { return status[CanIssue]; } 466 467 /** Sets this instruction as issued from the IQ. */ 468 void setIssued() { status.set(Issued); } 469 470 /** Returns whether or not this instruction has issued. */ 471 bool isIssued() const { return status[Issued]; } 472 473 /** Sets this instruction as executed. */ 474 void setExecuted() { status.set(Executed); } 475 476 /** Returns whether or not this instruction has executed. */ 477 bool isExecuted() const { return status[Executed]; } 478 479 /** Sets this instruction as ready to commit. */ 480 void setCanCommit() { status.set(CanCommit); } 481 482 /** Clears this instruction as being ready to commit. */ 483 void clearCanCommit() { status.reset(CanCommit); } 484 485 /** Returns whether or not this instruction is ready to commit. */ 486 bool readyToCommit() const { return status[CanCommit]; } 487 488 void setAtCommit() { status.set(AtCommit); } 489 490 bool isAtCommit() { return status[AtCommit]; } 491 492 /** Sets this instruction as committed. */ 493 void setCommitted() { status.set(Committed); } 494 495 /** Returns whether or not this instruction is committed. */ 496 bool isCommitted() const { return status[Committed]; } 497 498 /** Sets this instruction as squashed. */ 499 void setSquashed() { status.set(Squashed); } 500 501 /** Returns whether or not this instruction is squashed. */ 502 bool isSquashed() const { return status[Squashed]; } 503 504 //Instruction Queue Entry 505 //----------------------- 506 /** Sets this instruction as a entry the IQ. */ 507 void setInIQ() { status.set(IqEntry); } 508 509 /** Sets this instruction as a entry the IQ. */ 510 void clearInIQ() { status.reset(IqEntry); } 511 512 /** Returns whether or not this instruction has issued. */ 513 bool isInIQ() const { return status[IqEntry]; } 514 515 /** Sets this instruction as squashed in the IQ. */ 516 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 517 518 /** Returns whether or not this instruction is squashed in the IQ. */ 519 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 520 521 522 //Load / Store Queue Functions 523 //----------------------- 524 /** Sets this instruction as a entry the LSQ. */ 525 void setInLSQ() { status.set(LsqEntry); } 526 527 /** Sets this instruction as a entry the LSQ. */ 528 void removeInLSQ() { status.reset(LsqEntry); } 529 530 /** Returns whether or not this instruction is in the LSQ. */ 531 bool isInLSQ() const { return status[LsqEntry]; } 532 533 /** Sets this instruction as squashed in the LSQ. */ 534 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 535 536 /** Returns whether or not this instruction is squashed in the LSQ. */ 537 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 538 539 540 //Reorder Buffer Functions 541 //----------------------- 542 /** Sets this instruction as a entry the ROB. */ 543 void setInROB() { status.set(RobEntry); } 544 545 /** Sets this instruction as a entry the ROB. */ 546 void clearInROB() { status.reset(RobEntry); } 547 548 /** Returns whether or not this instruction is in the ROB. */ 549 bool isInROB() const { return status[RobEntry]; } 550 551 /** Sets this instruction as squashed in the ROB. */ 552 void setSquashedInROB() { status.set(SquashedInROB); } 553 554 /** Returns whether or not this instruction is squashed in the ROB. */ 555 bool isSquashedInROB() const { return status[SquashedInROB]; } 556 557 /** Read the PC of this instruction. */ 558 const Addr readPC() const { return PC; } 559 560 /** Set the next PC of this instruction (its actual target). */ 561 void setNextPC(uint64_t val) 562 { 563 nextPC = val; 564 } 565 566 /** Set the next NPC of this instruction (the target in Mips or Sparc).*/ 567 void setNextNPC(uint64_t val) 568 { 569 nextNPC = val; 570 } 571 572 /** Sets the ASID. */ 573 void setASID(short addr_space_id) { asid = addr_space_id; } 574 575 /** Sets the thread id. */ 576 void setTid(unsigned tid) { threadNumber = tid; } 577 578 /** Sets the pointer to the thread state. */ 579 void setThreadState(ImplState *state) { thread = state; } 580 581 /** Returns the thread context. */ 582 ThreadContext *tcBase() { return thread->getTC(); } 583 584 private: 585 /** Instruction effective address. 586 * @todo: Consider if this is necessary or not. 587 */ 588 Addr instEffAddr; 589 590 /** Whether or not the effective address calculation is completed. 591 * @todo: Consider if this is necessary or not. 592 */ 593 bool eaCalcDone; 594 595 public: 596 /** Sets the effective address. */ 597 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 598 599 /** Returns the effective address. */ 600 const Addr &getEA() const { return instEffAddr; } 601 602 /** Returns whether or not the eff. addr. calculation has been completed. */ 603 bool doneEACalc() { return eaCalcDone; } 604 605 /** Returns whether or not the eff. addr. source registers are ready. */ 606 bool eaSrcsReady(); 607 608 /** Whether or not the memory operation is done. */ 609 bool memOpDone; 610 611 public: 612 /** Load queue index. */ 613 int16_t lqIdx; 614 615 /** Store queue index. */ 616 int16_t sqIdx; 617 618 /** Iterator pointing to this BaseDynInst in the list of all insts. */ 619 ListIt instListIt; 620 621 /** Returns iterator to this instruction in the list of all insts. */ 622 ListIt &getInstListIt() { return instListIt; } 623 624 /** Sets iterator for this instruction in the list of all insts. */ 625 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 626}; 627 628template<class Impl> 629template<class T> 630inline Fault 631BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 632{ 633 // Sometimes reads will get retried, so they may come through here 634 // twice. 635 if (!req) { 636 req = new Request(); 637 req->setVirt(asid, addr, sizeof(T), flags, this->PC); 638 req->setThreadContext(thread->readCpuId(), threadNumber); 639 } else { 640 assert(addr == req->getVaddr()); 641 } 642 643 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() > 644 TheISA::VMPageSize) { 645 return TheISA::genAlignmentFault(); 646 } 647 648 fault = cpu->translateDataReadReq(req, thread); 649 650 if (fault == NoFault) { 651 effAddr = req->getVaddr(); 652 physEffAddr = req->getPaddr(); 653 memReqFlags = req->getFlags(); 654 655#if 0 656 if (cpu->system->memctrl->badaddr(physEffAddr)) { 657 fault = TheISA::genMachineCheckFault(); 658 data = (T)-1; 659 this->setExecuted(); 660 } else { 661 fault = cpu->read(req, data, lqIdx); 662 } 663#else 664 fault = cpu->read(req, data, lqIdx); 665#endif 666 } else { 667 // Return a fixed value to keep simulation deterministic even 668 // along misspeculated paths. 669 data = (T)-1; 670 671 // Commit will have to clean up whatever happened. Set this 672 // instruction as executed. 673 this->setExecuted(); 674 } 675 676 if (traceData) { 677 traceData->setAddr(addr); 678 traceData->setData(data); 679 } 680 681 return fault; 682} 683 684template<class Impl> 685template<class T> 686inline Fault 687BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 688{ 689 if (traceData) { 690 traceData->setAddr(addr); 691 traceData->setData(data); 692 } 693 694 assert(req == NULL); 695 696 req = new Request(); 697 req->setVirt(asid, addr, sizeof(T), flags, this->PC); 698 req->setThreadContext(thread->readCpuId(), threadNumber); 699 700 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() > 701 TheISA::VMPageSize) { 702 return TheISA::genAlignmentFault(); 703 } 704 705 fault = cpu->translateDataWriteReq(req, thread); 706 707 if (fault == NoFault) { 708 effAddr = req->getVaddr(); 709 physEffAddr = req->getPaddr(); 710 memReqFlags = req->getFlags(); 711#if 0 712 if (cpu->system->memctrl->badaddr(physEffAddr)) { 713 fault = TheISA::genMachineCheckFault(); 714 } else { 715 fault = cpu->write(req, data, sqIdx); 716 } 717#else 718 fault = cpu->write(req, data, sqIdx); 719#endif 720 } 721 722 if (res) { 723 // always return some result to keep misspeculated paths 724 // (which will ignore faults) deterministic 725 *res = (fault == NoFault) ? req->getScResult() : 0; 726 } 727 728 return fault; 729} 730 731#endif // __CPU_BASE_DYN_INST_HH__ 732