base_dyn_inst.hh revision 9932
11060SN/A/* 29814Sandreas.hansson@arm.com * Copyright (c) 2011,2013 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47944SGiacomo.Gabrielli@arm.com * All rights reserved. 57944SGiacomo.Gabrielli@arm.com * 67944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 147944SGiacomo.Gabrielli@arm.com * 152702Sktlim@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 166973Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The University of Edinburgh 171060SN/A * All rights reserved. 181060SN/A * 191060SN/A * Redistribution and use in source and binary forms, with or without 201060SN/A * modification, are permitted provided that the following conditions are 211060SN/A * met: redistributions of source code must retain the above copyright 221060SN/A * notice, this list of conditions and the following disclaimer; 231060SN/A * redistributions in binary form must reproduce the above copyright 241060SN/A * notice, this list of conditions and the following disclaimer in the 251060SN/A * documentation and/or other materials provided with the distribution; 261060SN/A * neither the name of the copyright holders nor the names of its 271060SN/A * contributors may be used to endorse or promote products derived from 281060SN/A * this software without specific prior written permission. 291060SN/A * 301060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412665Ssaidi@eecs.umich.edu * 422665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 436973Stjones1@inf.ed.ac.uk * Timothy M. Jones 441060SN/A */ 451060SN/A 461464SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 471464SN/A#define __CPU_BASE_DYN_INST_HH__ 481060SN/A 492731Sktlim@umich.edu#include <bitset> 502292SN/A#include <list> 511464SN/A#include <string> 528733Sgeoffrey.blake@arm.com#include <queue> 531060SN/A 547720Sgblack@eecs.umich.edu#include "arch/utility.hh" 551060SN/A#include "base/trace.hh" 566658Snate@binkert.org#include "config/the_isa.hh" 578887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 583770Sgblack@eecs.umich.edu#include "cpu/o3/comm.hh" 591464SN/A#include "cpu/exetrace.hh" 601464SN/A#include "cpu/inst_seq.hh" 612669Sktlim@umich.edu#include "cpu/op_class.hh" 621060SN/A#include "cpu/static_inst.hh" 636973Stjones1@inf.ed.ac.uk#include "cpu/translation.hh" 642669Sktlim@umich.edu#include "mem/packet.hh" 657678Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 668817Sgblack@eecs.umich.edu#include "sim/fault_fwd.hh" 672292SN/A#include "sim/system.hh" 686023Snate@binkert.org#include "sim/tlb.hh" 691060SN/A 701060SN/A/** 711060SN/A * @file 721060SN/A * Defines a dynamic instruction context. 731060SN/A */ 741060SN/A 751060SN/Atemplate <class Impl> 769044SAli.Saidi@ARM.comclass BaseDynInst : public RefCounted 771060SN/A{ 781060SN/A public: 791060SN/A // Typedef for the CPU. 802733Sktlim@umich.edu typedef typename Impl::CPUType ImplCPU; 812733Sktlim@umich.edu typedef typename ImplCPU::ImplState ImplState; 821060SN/A 832292SN/A // Logical register index type. 842107SN/A typedef TheISA::RegIndex RegIndex; 852690Sktlim@umich.edu // Integer register type. 862107SN/A typedef TheISA::IntReg IntReg; 872690Sktlim@umich.edu // Floating point register type. 882690Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 891060SN/A 902292SN/A // The DynInstPtr type. 912292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 928486Sgblack@eecs.umich.edu typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 932292SN/A 942292SN/A // The list of instructions iterator type. 952292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 962292SN/A 971060SN/A enum { 985543Ssaidi@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 998902Sandreas.hansson@arm.com MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs 1001060SN/A }; 1011060SN/A 1029046SAli.Saidi@ARM.com union Result { 1039046SAli.Saidi@ARM.com uint64_t integer; 1049046SAli.Saidi@ARM.com double dbl; 1059046SAli.Saidi@ARM.com void set(uint64_t i) { integer = i; } 1069046SAli.Saidi@ARM.com void set(double d) { dbl = d; } 1079046SAli.Saidi@ARM.com void get(uint64_t& i) { i = integer; } 1089046SAli.Saidi@ARM.com void get(double& d) { d = dbl; } 1099046SAli.Saidi@ARM.com }; 1109046SAli.Saidi@ARM.com 1119046SAli.Saidi@ARM.com protected: 1129046SAli.Saidi@ARM.com enum Status { 1139046SAli.Saidi@ARM.com IqEntry, /// Instruction is in the IQ 1149046SAli.Saidi@ARM.com RobEntry, /// Instruction is in the ROB 1159046SAli.Saidi@ARM.com LsqEntry, /// Instruction is in the LSQ 1169046SAli.Saidi@ARM.com Completed, /// Instruction has completed 1179046SAli.Saidi@ARM.com ResultReady, /// Instruction has its result 1189046SAli.Saidi@ARM.com CanIssue, /// Instruction can issue and execute 1199046SAli.Saidi@ARM.com Issued, /// Instruction has issued 1209046SAli.Saidi@ARM.com Executed, /// Instruction has executed 1219046SAli.Saidi@ARM.com CanCommit, /// Instruction can commit 1229046SAli.Saidi@ARM.com AtCommit, /// Instruction has reached commit 1239046SAli.Saidi@ARM.com Committed, /// Instruction has committed 1249046SAli.Saidi@ARM.com Squashed, /// Instruction is squashed 1259046SAli.Saidi@ARM.com SquashedInIQ, /// Instruction is squashed in the IQ 1269046SAli.Saidi@ARM.com SquashedInLSQ, /// Instruction is squashed in the LSQ 1279046SAli.Saidi@ARM.com SquashedInROB, /// Instruction is squashed in the ROB 1289046SAli.Saidi@ARM.com RecoverInst, /// Is a recover instruction 1299046SAli.Saidi@ARM.com BlockingInst, /// Is a blocking instruction 1309046SAli.Saidi@ARM.com ThreadsyncWait, /// Is a thread synchronization instruction 1319046SAli.Saidi@ARM.com SerializeBefore, /// Needs to serialize on 1329046SAli.Saidi@ARM.com /// instructions ahead of it 1339046SAli.Saidi@ARM.com SerializeAfter, /// Needs to serialize instructions behind it 1349046SAli.Saidi@ARM.com SerializeHandled, /// Serialization has been handled 1359046SAli.Saidi@ARM.com NumStatus 1369046SAli.Saidi@ARM.com }; 1379046SAli.Saidi@ARM.com 1389046SAli.Saidi@ARM.com enum Flags { 1399046SAli.Saidi@ARM.com TranslationStarted, 1409046SAli.Saidi@ARM.com TranslationCompleted, 1419046SAli.Saidi@ARM.com PossibleLoadViolation, 1429046SAli.Saidi@ARM.com HitExternalSnoop, 1439046SAli.Saidi@ARM.com EffAddrValid, 1449046SAli.Saidi@ARM.com RecordResult, 1459046SAli.Saidi@ARM.com Predicate, 1469046SAli.Saidi@ARM.com PredTaken, 1479046SAli.Saidi@ARM.com /** Whether or not the effective address calculation is completed. 1489046SAli.Saidi@ARM.com * @todo: Consider if this is necessary or not. 1499046SAli.Saidi@ARM.com */ 1509046SAli.Saidi@ARM.com EACalcDone, 1519046SAli.Saidi@ARM.com IsUncacheable, 1529046SAli.Saidi@ARM.com ReqMade, 1539046SAli.Saidi@ARM.com MemOpDone, 1549046SAli.Saidi@ARM.com MaxFlags 1559046SAli.Saidi@ARM.com }; 1569046SAli.Saidi@ARM.com 1579046SAli.Saidi@ARM.com public: 1589046SAli.Saidi@ARM.com /** The sequence number of the instruction. */ 1599046SAli.Saidi@ARM.com InstSeqNum seqNum; 1609046SAli.Saidi@ARM.com 1612292SN/A /** The StaticInst used by this BaseDynInst. */ 1622107SN/A StaticInstPtr staticInst; 1639046SAli.Saidi@ARM.com 1649046SAli.Saidi@ARM.com /** Pointer to the Impl's CPU object. */ 1659046SAli.Saidi@ARM.com ImplCPU *cpu; 1669046SAli.Saidi@ARM.com 1679046SAli.Saidi@ARM.com /** Pointer to the thread state. */ 1689046SAli.Saidi@ARM.com ImplState *thread; 1699046SAli.Saidi@ARM.com 1709046SAli.Saidi@ARM.com /** The kind of fault this instruction has generated. */ 1719046SAli.Saidi@ARM.com Fault fault; 1729046SAli.Saidi@ARM.com 1739046SAli.Saidi@ARM.com /** InstRecord that tracks this instructions. */ 1749046SAli.Saidi@ARM.com Trace::InstRecord *traceData; 1759046SAli.Saidi@ARM.com 1769046SAli.Saidi@ARM.com protected: 1779046SAli.Saidi@ARM.com /** The result of the instruction; assumes an instruction can have many 1789046SAli.Saidi@ARM.com * destination registers. 1799046SAli.Saidi@ARM.com */ 1809046SAli.Saidi@ARM.com std::queue<Result> instResult; 1819046SAli.Saidi@ARM.com 1829046SAli.Saidi@ARM.com /** PC state for this instruction. */ 1839046SAli.Saidi@ARM.com TheISA::PCState pc; 1849046SAli.Saidi@ARM.com 1859046SAli.Saidi@ARM.com /* An amalgamation of a lot of boolean values into one */ 1869046SAli.Saidi@ARM.com std::bitset<MaxFlags> instFlags; 1879046SAli.Saidi@ARM.com 1889046SAli.Saidi@ARM.com /** The status of this BaseDynInst. Several bits can be set. */ 1899046SAli.Saidi@ARM.com std::bitset<NumStatus> status; 1909046SAli.Saidi@ARM.com 1919046SAli.Saidi@ARM.com /** Whether or not the source register is ready. 1929046SAli.Saidi@ARM.com * @todo: Not sure this should be here vs the derived class. 1939046SAli.Saidi@ARM.com */ 1949046SAli.Saidi@ARM.com std::bitset<MaxInstSrcRegs> _readySrcRegIdx; 1959046SAli.Saidi@ARM.com 1969046SAli.Saidi@ARM.com public: 1979046SAli.Saidi@ARM.com /** The thread this instruction is from. */ 1989046SAli.Saidi@ARM.com ThreadID threadNumber; 1999046SAli.Saidi@ARM.com 2009046SAli.Saidi@ARM.com /** Iterator pointing to this BaseDynInst in the list of all insts. */ 2019046SAli.Saidi@ARM.com ListIt instListIt; 2029046SAli.Saidi@ARM.com 2039046SAli.Saidi@ARM.com ////////////////////// Branch Data /////////////// 2049046SAli.Saidi@ARM.com /** Predicted PC state after this instruction. */ 2059046SAli.Saidi@ARM.com TheISA::PCState predPC; 2069046SAli.Saidi@ARM.com 2079046SAli.Saidi@ARM.com /** The Macroop if one exists */ 2088502Sgblack@eecs.umich.edu StaticInstPtr macroop; 2091060SN/A 2109046SAli.Saidi@ARM.com /** How many source registers are ready. */ 2119046SAli.Saidi@ARM.com uint8_t readyRegs; 2129046SAli.Saidi@ARM.com 2139046SAli.Saidi@ARM.com public: 2149046SAli.Saidi@ARM.com /////////////////////// Load Store Data ////////////////////// 2159046SAli.Saidi@ARM.com /** The effective virtual address (lds & stores only). */ 2169046SAli.Saidi@ARM.com Addr effAddr; 2179046SAli.Saidi@ARM.com 2189046SAli.Saidi@ARM.com /** The effective physical address. */ 2199046SAli.Saidi@ARM.com Addr physEffAddr; 2209046SAli.Saidi@ARM.com 2219046SAli.Saidi@ARM.com /** The memory request flags (from translation). */ 2229046SAli.Saidi@ARM.com unsigned memReqFlags; 2239046SAli.Saidi@ARM.com 2249046SAli.Saidi@ARM.com /** data address space ID, for loads & stores. */ 2259046SAli.Saidi@ARM.com short asid; 2269046SAli.Saidi@ARM.com 2279046SAli.Saidi@ARM.com /** The size of the request */ 2289046SAli.Saidi@ARM.com uint8_t effSize; 2299046SAli.Saidi@ARM.com 2309046SAli.Saidi@ARM.com /** Pointer to the data for the memory access. */ 2319046SAli.Saidi@ARM.com uint8_t *memData; 2329046SAli.Saidi@ARM.com 2339046SAli.Saidi@ARM.com /** Load queue index. */ 2349046SAli.Saidi@ARM.com int16_t lqIdx; 2359046SAli.Saidi@ARM.com 2369046SAli.Saidi@ARM.com /** Store queue index. */ 2379046SAli.Saidi@ARM.com int16_t sqIdx; 2389046SAli.Saidi@ARM.com 2399046SAli.Saidi@ARM.com 2409046SAli.Saidi@ARM.com /////////////////////// TLB Miss ////////////////////// 2419046SAli.Saidi@ARM.com /** 2429046SAli.Saidi@ARM.com * Saved memory requests (needed when the DTB address translation is 2439046SAli.Saidi@ARM.com * delayed due to a hw page table walk). 2449046SAli.Saidi@ARM.com */ 2459046SAli.Saidi@ARM.com RequestPtr savedReq; 2469046SAli.Saidi@ARM.com RequestPtr savedSreqLow; 2479046SAli.Saidi@ARM.com RequestPtr savedSreqHigh; 2489046SAli.Saidi@ARM.com 2499046SAli.Saidi@ARM.com /////////////////////// Checker ////////////////////// 2509046SAli.Saidi@ARM.com // Need a copy of main request pointer to verify on writes. 2519046SAli.Saidi@ARM.com RequestPtr reqToVerify; 2529046SAli.Saidi@ARM.com 2539046SAli.Saidi@ARM.com private: 2549046SAli.Saidi@ARM.com /** Instruction effective address. 2559046SAli.Saidi@ARM.com * @todo: Consider if this is necessary or not. 2569046SAli.Saidi@ARM.com */ 2579046SAli.Saidi@ARM.com Addr instEffAddr; 2589046SAli.Saidi@ARM.com 2599046SAli.Saidi@ARM.com protected: 2609046SAli.Saidi@ARM.com /** Flattened register index of the destination registers of this 2619046SAli.Saidi@ARM.com * instruction. 2629046SAli.Saidi@ARM.com */ 2639046SAli.Saidi@ARM.com TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 2649046SAli.Saidi@ARM.com 2659046SAli.Saidi@ARM.com /** Physical register index of the destination registers of this 2669046SAli.Saidi@ARM.com * instruction. 2679046SAli.Saidi@ARM.com */ 2689046SAli.Saidi@ARM.com PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 2699046SAli.Saidi@ARM.com 2709046SAli.Saidi@ARM.com /** Physical register index of the source registers of this 2719046SAli.Saidi@ARM.com * instruction. 2729046SAli.Saidi@ARM.com */ 2739046SAli.Saidi@ARM.com PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 2749046SAli.Saidi@ARM.com 2759046SAli.Saidi@ARM.com /** Physical register index of the previous producers of the 2769046SAli.Saidi@ARM.com * architected destinations. 2779046SAli.Saidi@ARM.com */ 2789046SAli.Saidi@ARM.com PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 2799046SAli.Saidi@ARM.com 2809046SAli.Saidi@ARM.com 2819046SAli.Saidi@ARM.com public: 2829046SAli.Saidi@ARM.com /** Records changes to result? */ 2839046SAli.Saidi@ARM.com void recordResult(bool f) { instFlags[RecordResult] = f; } 2849046SAli.Saidi@ARM.com 2859046SAli.Saidi@ARM.com /** Is the effective virtual address valid. */ 2869046SAli.Saidi@ARM.com bool effAddrValid() const { return instFlags[EffAddrValid]; } 2879046SAli.Saidi@ARM.com 2889046SAli.Saidi@ARM.com /** Whether or not the memory operation is done. */ 2899046SAli.Saidi@ARM.com bool memOpDone() const { return instFlags[MemOpDone]; } 2909046SAli.Saidi@ARM.com void memOpDone(bool f) { instFlags[MemOpDone] = f; } 2919046SAli.Saidi@ARM.com 2929046SAli.Saidi@ARM.com 2931060SN/A //////////////////////////////////////////// 2941060SN/A // 2951060SN/A // INSTRUCTION EXECUTION 2961060SN/A // 2971060SN/A //////////////////////////////////////////// 2981060SN/A 2995358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 3005358Sgblack@eecs.umich.edu { 3015358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 3025358Sgblack@eecs.umich.edu } 3035358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 3045358Sgblack@eecs.umich.edu { 3055358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 3065358Sgblack@eecs.umich.edu } 3075358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 3085358Sgblack@eecs.umich.edu { 3095358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 3105358Sgblack@eecs.umich.edu } 3115358Sgblack@eecs.umich.edu 3128444Sgblack@eecs.umich.edu Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 3137520Sgblack@eecs.umich.edu 3148444Sgblack@eecs.umich.edu Fault writeMem(uint8_t *data, unsigned size, 3158444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res); 3167520Sgblack@eecs.umich.edu 3176974Stjones1@inf.ed.ac.uk /** Splits a request in two if it crosses a dcache block. */ 3186974Stjones1@inf.ed.ac.uk void splitRequest(RequestPtr req, RequestPtr &sreqLow, 3196974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh); 3206974Stjones1@inf.ed.ac.uk 3216973Stjones1@inf.ed.ac.uk /** Initiate a DTB address translation. */ 3226974Stjones1@inf.ed.ac.uk void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 3236974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 3246973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode); 3256973Stjones1@inf.ed.ac.uk 3266973Stjones1@inf.ed.ac.uk /** Finish a DTB address translation. */ 3276973Stjones1@inf.ed.ac.uk void finishTranslation(WholeTranslationState *state); 3281060SN/A 3297944SGiacomo.Gabrielli@arm.com /** True if the DTB address translation has started. */ 3309046SAli.Saidi@ARM.com bool translationStarted() const { return instFlags[TranslationStarted]; } 3319046SAli.Saidi@ARM.com void translationStarted(bool f) { instFlags[TranslationStarted] = f; } 3327944SGiacomo.Gabrielli@arm.com 3337944SGiacomo.Gabrielli@arm.com /** True if the DTB address translation has completed. */ 3349046SAli.Saidi@ARM.com bool translationCompleted() const { return instFlags[TranslationCompleted]; } 3359046SAli.Saidi@ARM.com void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; } 3367944SGiacomo.Gabrielli@arm.com 3378545Ssaidi@eecs.umich.edu /** True if this address was found to match a previous load and they issued 3388545Ssaidi@eecs.umich.edu * out of order. If that happend, then it's only a problem if an incoming 3398545Ssaidi@eecs.umich.edu * snoop invalidate modifies the line, in which case we need to squash. 3408545Ssaidi@eecs.umich.edu * If nothing modified the line the order doesn't matter. 3418545Ssaidi@eecs.umich.edu */ 3429046SAli.Saidi@ARM.com bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; } 3439046SAli.Saidi@ARM.com void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; } 3448545Ssaidi@eecs.umich.edu 3458545Ssaidi@eecs.umich.edu /** True if the address hit a external snoop while sitting in the LSQ. 3468545Ssaidi@eecs.umich.edu * If this is true and a older instruction sees it, this instruction must 3478545Ssaidi@eecs.umich.edu * reexecute 3488545Ssaidi@eecs.umich.edu */ 3499046SAli.Saidi@ARM.com bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; } 3509046SAli.Saidi@ARM.com void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; } 3518545Ssaidi@eecs.umich.edu 3527944SGiacomo.Gabrielli@arm.com /** 3537944SGiacomo.Gabrielli@arm.com * Returns true if the DTB address translation is being delayed due to a hw 3547944SGiacomo.Gabrielli@arm.com * page table walk. 3557944SGiacomo.Gabrielli@arm.com */ 3567944SGiacomo.Gabrielli@arm.com bool isTranslationDelayed() const 3577944SGiacomo.Gabrielli@arm.com { 3589046SAli.Saidi@ARM.com return (translationStarted() && !translationCompleted()); 3597944SGiacomo.Gabrielli@arm.com } 3607944SGiacomo.Gabrielli@arm.com 3611060SN/A public: 3622292SN/A#ifdef DEBUG 3632292SN/A void dumpSNList(); 3642292SN/A#endif 3652292SN/A 3663770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th destination 3673770Sgblack@eecs.umich.edu * register. 3683770Sgblack@eecs.umich.edu */ 3693770Sgblack@eecs.umich.edu PhysRegIndex renamedDestRegIdx(int idx) const 3703770Sgblack@eecs.umich.edu { 3713770Sgblack@eecs.umich.edu return _destRegIdx[idx]; 3723770Sgblack@eecs.umich.edu } 3733770Sgblack@eecs.umich.edu 3743770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th source register. */ 3753770Sgblack@eecs.umich.edu PhysRegIndex renamedSrcRegIdx(int idx) const 3763770Sgblack@eecs.umich.edu { 3779046SAli.Saidi@ARM.com assert(TheISA::MaxInstSrcRegs > idx); 3783770Sgblack@eecs.umich.edu return _srcRegIdx[idx]; 3793770Sgblack@eecs.umich.edu } 3803770Sgblack@eecs.umich.edu 3813770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th destination 3823770Sgblack@eecs.umich.edu * register. 3833770Sgblack@eecs.umich.edu */ 3843770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedDestRegIdx(int idx) const 3853770Sgblack@eecs.umich.edu { 3863770Sgblack@eecs.umich.edu return _flatDestRegIdx[idx]; 3873770Sgblack@eecs.umich.edu } 3883770Sgblack@eecs.umich.edu 3893770Sgblack@eecs.umich.edu /** Returns the physical register index of the previous physical register 3903770Sgblack@eecs.umich.edu * that remapped to the same logical register index. 3913770Sgblack@eecs.umich.edu */ 3923770Sgblack@eecs.umich.edu PhysRegIndex prevDestRegIdx(int idx) const 3933770Sgblack@eecs.umich.edu { 3943770Sgblack@eecs.umich.edu return _prevDestRegIdx[idx]; 3953770Sgblack@eecs.umich.edu } 3963770Sgblack@eecs.umich.edu 3973770Sgblack@eecs.umich.edu /** Renames a destination register to a physical register. Also records 3983770Sgblack@eecs.umich.edu * the previous physical register that the logical register mapped to. 3993770Sgblack@eecs.umich.edu */ 4003770Sgblack@eecs.umich.edu void renameDestReg(int idx, 4013770Sgblack@eecs.umich.edu PhysRegIndex renamed_dest, 4023770Sgblack@eecs.umich.edu PhysRegIndex previous_rename) 4033770Sgblack@eecs.umich.edu { 4043770Sgblack@eecs.umich.edu _destRegIdx[idx] = renamed_dest; 4053770Sgblack@eecs.umich.edu _prevDestRegIdx[idx] = previous_rename; 4063770Sgblack@eecs.umich.edu } 4073770Sgblack@eecs.umich.edu 4083770Sgblack@eecs.umich.edu /** Renames a source logical register to the physical register which 4093770Sgblack@eecs.umich.edu * has/will produce that logical register's result. 4103770Sgblack@eecs.umich.edu * @todo: add in whether or not the source register is ready. 4113770Sgblack@eecs.umich.edu */ 4123770Sgblack@eecs.umich.edu void renameSrcReg(int idx, PhysRegIndex renamed_src) 4133770Sgblack@eecs.umich.edu { 4143770Sgblack@eecs.umich.edu _srcRegIdx[idx] = renamed_src; 4153770Sgblack@eecs.umich.edu } 4163770Sgblack@eecs.umich.edu 4173770Sgblack@eecs.umich.edu /** Flattens a destination architectural register index into a logical 4183770Sgblack@eecs.umich.edu * index. 4193770Sgblack@eecs.umich.edu */ 4203770Sgblack@eecs.umich.edu void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 4213770Sgblack@eecs.umich.edu { 4223770Sgblack@eecs.umich.edu _flatDestRegIdx[idx] = flattened_dest; 4233770Sgblack@eecs.umich.edu } 4244636Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. 4254636Sgblack@eecs.umich.edu * @param staticInst A StaticInstPtr to the underlying instruction. 4267720Sgblack@eecs.umich.edu * @param pc The PC state for the instruction. 4277720Sgblack@eecs.umich.edu * @param predPC The predicted next PC state for the instruction. 4284636Sgblack@eecs.umich.edu * @param seq_num The sequence number of the instruction. 4294636Sgblack@eecs.umich.edu * @param cpu Pointer to the instruction's CPU. 4304636Sgblack@eecs.umich.edu */ 4318502Sgblack@eecs.umich.edu BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop, 4328502Sgblack@eecs.umich.edu TheISA::PCState pc, TheISA::PCState predPC, 4338502Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu); 4343770Sgblack@eecs.umich.edu 4352292SN/A /** BaseDynInst constructor given a StaticInst pointer. 4362292SN/A * @param _staticInst The StaticInst for this BaseDynInst. 4372292SN/A */ 4388502Sgblack@eecs.umich.edu BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop); 4391060SN/A 4401060SN/A /** BaseDynInst destructor. */ 4411060SN/A ~BaseDynInst(); 4421060SN/A 4431464SN/A private: 4441684SN/A /** Function to initialize variables in the constructors. */ 4451464SN/A void initVars(); 4461060SN/A 4471464SN/A public: 4481060SN/A /** Dumps out contents of this BaseDynInst. */ 4491060SN/A void dump(); 4501060SN/A 4511060SN/A /** Dumps out contents of this BaseDynInst into given string. */ 4521060SN/A void dump(std::string &outstring); 4531060SN/A 4543326Sktlim@umich.edu /** Read this CPU's ID. */ 4555712Shsul@eecs.umich.edu int cpuId() { return cpu->cpuId(); } 4563326Sktlim@umich.edu 4578832SAli.Saidi@ARM.com /** Read this CPU's data requestor ID */ 4588832SAli.Saidi@ARM.com MasterID masterId() { return cpu->dataMasterId(); } 4598832SAli.Saidi@ARM.com 4605714Shsul@eecs.umich.edu /** Read this context's system-wide ID **/ 4615714Shsul@eecs.umich.edu int contextId() { return thread->contextId(); } 4625714Shsul@eecs.umich.edu 4631060SN/A /** Returns the fault type. */ 4642132SN/A Fault getFault() { return fault; } 4651060SN/A 4661060SN/A /** Checks whether or not this instruction has had its branch target 4671060SN/A * calculated yet. For now it is not utilized and is hacked to be 4681060SN/A * always false. 4692292SN/A * @todo: Actually use this instruction. 4701060SN/A */ 4711060SN/A bool doneTargCalc() { return false; } 4721060SN/A 4737720Sgblack@eecs.umich.edu /** Set the predicted target of this current instruction. */ 4747720Sgblack@eecs.umich.edu void setPredTarg(const TheISA::PCState &_predPC) 4753965Sgblack@eecs.umich.edu { 4767720Sgblack@eecs.umich.edu predPC = _predPC; 4773965Sgblack@eecs.umich.edu } 4782935Sksewell@umich.edu 4797720Sgblack@eecs.umich.edu const TheISA::PCState &readPredTarg() { return predPC; } 4801060SN/A 4813794Sgblack@eecs.umich.edu /** Returns the predicted PC immediately after the branch. */ 4827720Sgblack@eecs.umich.edu Addr predInstAddr() { return predPC.instAddr(); } 4833794Sgblack@eecs.umich.edu 4843794Sgblack@eecs.umich.edu /** Returns the predicted PC two instructions after the branch */ 4857720Sgblack@eecs.umich.edu Addr predNextInstAddr() { return predPC.nextInstAddr(); } 4861060SN/A 4874636Sgblack@eecs.umich.edu /** Returns the predicted micro PC after the branch */ 4887720Sgblack@eecs.umich.edu Addr predMicroPC() { return predPC.microPC(); } 4894636Sgblack@eecs.umich.edu 4901060SN/A /** Returns whether the instruction was predicted taken or not. */ 4913794Sgblack@eecs.umich.edu bool readPredTaken() 4923794Sgblack@eecs.umich.edu { 4939046SAli.Saidi@ARM.com return instFlags[PredTaken]; 4943794Sgblack@eecs.umich.edu } 4953794Sgblack@eecs.umich.edu 4963794Sgblack@eecs.umich.edu void setPredTaken(bool predicted_taken) 4973794Sgblack@eecs.umich.edu { 4989046SAli.Saidi@ARM.com instFlags[PredTaken] = predicted_taken; 4993794Sgblack@eecs.umich.edu } 5001060SN/A 5011060SN/A /** Returns whether the instruction mispredicted. */ 5022935Sksewell@umich.edu bool mispredicted() 5033794Sgblack@eecs.umich.edu { 5047720Sgblack@eecs.umich.edu TheISA::PCState tempPC = pc; 5057720Sgblack@eecs.umich.edu TheISA::advancePC(tempPC, staticInst); 5067720Sgblack@eecs.umich.edu return !(tempPC == predPC); 5073794Sgblack@eecs.umich.edu } 5083794Sgblack@eecs.umich.edu 5091060SN/A // 5101060SN/A // Instruction types. Forward checks to StaticInst object. 5111060SN/A // 5125543Ssaidi@eecs.umich.edu bool isNop() const { return staticInst->isNop(); } 5135543Ssaidi@eecs.umich.edu bool isMemRef() const { return staticInst->isMemRef(); } 5145543Ssaidi@eecs.umich.edu bool isLoad() const { return staticInst->isLoad(); } 5155543Ssaidi@eecs.umich.edu bool isStore() const { return staticInst->isStore(); } 5162336SN/A bool isStoreConditional() const 5172336SN/A { return staticInst->isStoreConditional(); } 5181060SN/A bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 5191060SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 5205543Ssaidi@eecs.umich.edu bool isInteger() const { return staticInst->isInteger(); } 5215543Ssaidi@eecs.umich.edu bool isFloating() const { return staticInst->isFloating(); } 5225543Ssaidi@eecs.umich.edu bool isControl() const { return staticInst->isControl(); } 5235543Ssaidi@eecs.umich.edu bool isCall() const { return staticInst->isCall(); } 5245543Ssaidi@eecs.umich.edu bool isReturn() const { return staticInst->isReturn(); } 5255543Ssaidi@eecs.umich.edu bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 5261060SN/A bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 5275543Ssaidi@eecs.umich.edu bool isCondCtrl() const { return staticInst->isCondCtrl(); } 5285543Ssaidi@eecs.umich.edu bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 5292935Sksewell@umich.edu bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 5301060SN/A bool isThreadSync() const { return staticInst->isThreadSync(); } 5311060SN/A bool isSerializing() const { return staticInst->isSerializing(); } 5322292SN/A bool isSerializeBefore() const 5332731Sktlim@umich.edu { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 5342292SN/A bool isSerializeAfter() const 5352731Sktlim@umich.edu { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 5367784SAli.Saidi@ARM.com bool isSquashAfter() const { return staticInst->isSquashAfter(); } 5371060SN/A bool isMemBarrier() const { return staticInst->isMemBarrier(); } 5381060SN/A bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 5391060SN/A bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 5402292SN/A bool isQuiesce() const { return staticInst->isQuiesce(); } 5412336SN/A bool isIprAccess() const { return staticInst->isIprAccess(); } 5422308SN/A bool isUnverifiable() const { return staticInst->isUnverifiable(); } 5434828Sgblack@eecs.umich.edu bool isSyscall() const { return staticInst->isSyscall(); } 5444654Sgblack@eecs.umich.edu bool isMacroop() const { return staticInst->isMacroop(); } 5454654Sgblack@eecs.umich.edu bool isMicroop() const { return staticInst->isMicroop(); } 5464636Sgblack@eecs.umich.edu bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 5474654Sgblack@eecs.umich.edu bool isLastMicroop() const { return staticInst->isLastMicroop(); } 5484654Sgblack@eecs.umich.edu bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 5494636Sgblack@eecs.umich.edu bool isMicroBranch() const { return staticInst->isMicroBranch(); } 5502292SN/A 5512292SN/A /** Temporarily sets this instruction as a serialize before instruction. */ 5522731Sktlim@umich.edu void setSerializeBefore() { status.set(SerializeBefore); } 5532292SN/A 5542292SN/A /** Clears the serializeBefore part of this instruction. */ 5552731Sktlim@umich.edu void clearSerializeBefore() { status.reset(SerializeBefore); } 5562292SN/A 5572292SN/A /** Checks if this serializeBefore is only temporarily set. */ 5582731Sktlim@umich.edu bool isTempSerializeBefore() { return status[SerializeBefore]; } 5592292SN/A 5602292SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 5612731Sktlim@umich.edu void setSerializeAfter() { status.set(SerializeAfter); } 5622292SN/A 5632292SN/A /** Clears the serializeAfter part of this instruction.*/ 5642731Sktlim@umich.edu void clearSerializeAfter() { status.reset(SerializeAfter); } 5652292SN/A 5662292SN/A /** Checks if this serializeAfter is only temporarily set. */ 5672731Sktlim@umich.edu bool isTempSerializeAfter() { return status[SerializeAfter]; } 5682292SN/A 5692731Sktlim@umich.edu /** Sets the serialization part of this instruction as handled. */ 5702731Sktlim@umich.edu void setSerializeHandled() { status.set(SerializeHandled); } 5712292SN/A 5722292SN/A /** Checks if the serialization part of this instruction has been 5732292SN/A * handled. This does not apply to the temporary serializing 5742292SN/A * state; it only applies to this instruction's own permanent 5752292SN/A * serializing state. 5762292SN/A */ 5772731Sktlim@umich.edu bool isSerializeHandled() { return status[SerializeHandled]; } 5781060SN/A 5791464SN/A /** Returns the opclass of this instruction. */ 5801464SN/A OpClass opClass() const { return staticInst->opClass(); } 5811464SN/A 5821464SN/A /** Returns the branch target address. */ 5837720Sgblack@eecs.umich.edu TheISA::PCState branchTarget() const 5847720Sgblack@eecs.umich.edu { return staticInst->branchTarget(pc); } 5851464SN/A 5862292SN/A /** Returns the number of source registers. */ 5875543Ssaidi@eecs.umich.edu int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 5881684SN/A 5892292SN/A /** Returns the number of destination registers. */ 5901060SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 5911060SN/A 5921060SN/A // the following are used to track physical register usage 5931060SN/A // for machines with separate int & FP reg files 5941060SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 5951060SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 5961060SN/A 5971060SN/A /** Returns the logical register index of the i'th destination register. */ 5982292SN/A RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 5991060SN/A 6001060SN/A /** Returns the logical register index of the i'th source register. */ 6012292SN/A RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 6021060SN/A 6038733Sgeoffrey.blake@arm.com /** Pops a result off the instResult queue */ 6048733Sgeoffrey.blake@arm.com template <class T> 6058733Sgeoffrey.blake@arm.com void popResult(T& t) 6068733Sgeoffrey.blake@arm.com { 6078733Sgeoffrey.blake@arm.com if (!instResult.empty()) { 6088733Sgeoffrey.blake@arm.com instResult.front().get(t); 6098733Sgeoffrey.blake@arm.com instResult.pop(); 6108733Sgeoffrey.blake@arm.com } 6118733Sgeoffrey.blake@arm.com } 6121684SN/A 6138733Sgeoffrey.blake@arm.com /** Read the most recent result stored by this instruction */ 6148733Sgeoffrey.blake@arm.com template <class T> 6158733Sgeoffrey.blake@arm.com void readResult(T& t) 6168733Sgeoffrey.blake@arm.com { 6178733Sgeoffrey.blake@arm.com instResult.back().get(t); 6188733Sgeoffrey.blake@arm.com } 6191684SN/A 6208733Sgeoffrey.blake@arm.com /** Pushes a result onto the instResult queue */ 6218733Sgeoffrey.blake@arm.com template <class T> 6228733Sgeoffrey.blake@arm.com void setResult(T t) 6238733Sgeoffrey.blake@arm.com { 6249046SAli.Saidi@ARM.com if (instFlags[RecordResult]) { 6258733Sgeoffrey.blake@arm.com Result instRes; 6268733Sgeoffrey.blake@arm.com instRes.set(t); 6278733Sgeoffrey.blake@arm.com instResult.push(instRes); 6288733Sgeoffrey.blake@arm.com } 6298733Sgeoffrey.blake@arm.com } 6301060SN/A 6312702Sktlim@umich.edu /** Records an integer register being set to a value. */ 6323735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 6331060SN/A { 6348733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 6351060SN/A } 6361060SN/A 6379920Syasuko.eckert@amd.com /** Records a CC register being set to a value. */ 6389920Syasuko.eckert@amd.com void setCCRegOperand(const StaticInst *si, int idx, uint64_t val) 6399920Syasuko.eckert@amd.com { 6409920Syasuko.eckert@amd.com setResult<uint64_t>(val); 6419920Syasuko.eckert@amd.com } 6429920Syasuko.eckert@amd.com 6432702Sktlim@umich.edu /** Records an fp register being set to a value. */ 6443735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 6453735Sstever@eecs.umich.edu int width) 6462690Sktlim@umich.edu { 6478733Sgeoffrey.blake@arm.com if (width == 32 || width == 64) { 6488733Sgeoffrey.blake@arm.com setResult<double>(val); 6498733Sgeoffrey.blake@arm.com } else { 6508733Sgeoffrey.blake@arm.com panic("Unsupported width!"); 6513326Sktlim@umich.edu } 6522690Sktlim@umich.edu } 6532690Sktlim@umich.edu 6542702Sktlim@umich.edu /** Records an fp register being set to a value. */ 6553735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 6561060SN/A { 6578733Sgeoffrey.blake@arm.com setResult<double>(val); 6582308SN/A } 6591060SN/A 6602702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 6613735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 6623735Sstever@eecs.umich.edu int width) 6632308SN/A { 6648733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 6652308SN/A } 6661060SN/A 6672702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 6683735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 6692308SN/A { 6708733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 6711060SN/A } 6721060SN/A 6732190SN/A /** Records that one of the source registers is ready. */ 6742292SN/A void markSrcRegReady(); 6752190SN/A 6762331SN/A /** Marks a specific register as ready. */ 6772292SN/A void markSrcRegReady(RegIndex src_idx); 6782190SN/A 6791684SN/A /** Returns if a source register is ready. */ 6801464SN/A bool isReadySrcRegIdx(int idx) const 6811464SN/A { 6821464SN/A return this->_readySrcRegIdx[idx]; 6831464SN/A } 6841464SN/A 6851684SN/A /** Sets this instruction as completed. */ 6862731Sktlim@umich.edu void setCompleted() { status.set(Completed); } 6871464SN/A 6882292SN/A /** Returns whether or not this instruction is completed. */ 6892731Sktlim@umich.edu bool isCompleted() const { return status[Completed]; } 6901464SN/A 6912731Sktlim@umich.edu /** Marks the result as ready. */ 6922731Sktlim@umich.edu void setResultReady() { status.set(ResultReady); } 6932308SN/A 6942731Sktlim@umich.edu /** Returns whether or not the result is ready. */ 6952731Sktlim@umich.edu bool isResultReady() const { return status[ResultReady]; } 6962308SN/A 6971060SN/A /** Sets this instruction as ready to issue. */ 6982731Sktlim@umich.edu void setCanIssue() { status.set(CanIssue); } 6991060SN/A 7001060SN/A /** Returns whether or not this instruction is ready to issue. */ 7012731Sktlim@umich.edu bool readyToIssue() const { return status[CanIssue]; } 7021060SN/A 7034032Sktlim@umich.edu /** Clears this instruction being able to issue. */ 7044032Sktlim@umich.edu void clearCanIssue() { status.reset(CanIssue); } 7054032Sktlim@umich.edu 7061060SN/A /** Sets this instruction as issued from the IQ. */ 7072731Sktlim@umich.edu void setIssued() { status.set(Issued); } 7081060SN/A 7091060SN/A /** Returns whether or not this instruction has issued. */ 7102731Sktlim@umich.edu bool isIssued() const { return status[Issued]; } 7111060SN/A 7124032Sktlim@umich.edu /** Clears this instruction as being issued. */ 7134032Sktlim@umich.edu void clearIssued() { status.reset(Issued); } 7144032Sktlim@umich.edu 7151060SN/A /** Sets this instruction as executed. */ 7162731Sktlim@umich.edu void setExecuted() { status.set(Executed); } 7171060SN/A 7181060SN/A /** Returns whether or not this instruction has executed. */ 7192731Sktlim@umich.edu bool isExecuted() const { return status[Executed]; } 7201060SN/A 7211060SN/A /** Sets this instruction as ready to commit. */ 7222731Sktlim@umich.edu void setCanCommit() { status.set(CanCommit); } 7231060SN/A 7241061SN/A /** Clears this instruction as being ready to commit. */ 7252731Sktlim@umich.edu void clearCanCommit() { status.reset(CanCommit); } 7261061SN/A 7271060SN/A /** Returns whether or not this instruction is ready to commit. */ 7282731Sktlim@umich.edu bool readyToCommit() const { return status[CanCommit]; } 7292731Sktlim@umich.edu 7302731Sktlim@umich.edu void setAtCommit() { status.set(AtCommit); } 7312731Sktlim@umich.edu 7322731Sktlim@umich.edu bool isAtCommit() { return status[AtCommit]; } 7331060SN/A 7342292SN/A /** Sets this instruction as committed. */ 7352731Sktlim@umich.edu void setCommitted() { status.set(Committed); } 7362292SN/A 7372292SN/A /** Returns whether or not this instruction is committed. */ 7382731Sktlim@umich.edu bool isCommitted() const { return status[Committed]; } 7392292SN/A 7401060SN/A /** Sets this instruction as squashed. */ 7412731Sktlim@umich.edu void setSquashed() { status.set(Squashed); } 7421060SN/A 7431060SN/A /** Returns whether or not this instruction is squashed. */ 7442731Sktlim@umich.edu bool isSquashed() const { return status[Squashed]; } 7451060SN/A 7462292SN/A //Instruction Queue Entry 7472292SN/A //----------------------- 7482292SN/A /** Sets this instruction as a entry the IQ. */ 7492731Sktlim@umich.edu void setInIQ() { status.set(IqEntry); } 7502292SN/A 7512292SN/A /** Sets this instruction as a entry the IQ. */ 7522731Sktlim@umich.edu void clearInIQ() { status.reset(IqEntry); } 7532731Sktlim@umich.edu 7542731Sktlim@umich.edu /** Returns whether or not this instruction has issued. */ 7552731Sktlim@umich.edu bool isInIQ() const { return status[IqEntry]; } 7562292SN/A 7571060SN/A /** Sets this instruction as squashed in the IQ. */ 7582731Sktlim@umich.edu void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 7591060SN/A 7601060SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 7612731Sktlim@umich.edu bool isSquashedInIQ() const { return status[SquashedInIQ]; } 7622292SN/A 7632292SN/A 7642292SN/A //Load / Store Queue Functions 7652292SN/A //----------------------- 7662292SN/A /** Sets this instruction as a entry the LSQ. */ 7672731Sktlim@umich.edu void setInLSQ() { status.set(LsqEntry); } 7682292SN/A 7692292SN/A /** Sets this instruction as a entry the LSQ. */ 7702731Sktlim@umich.edu void removeInLSQ() { status.reset(LsqEntry); } 7712731Sktlim@umich.edu 7722731Sktlim@umich.edu /** Returns whether or not this instruction is in the LSQ. */ 7732731Sktlim@umich.edu bool isInLSQ() const { return status[LsqEntry]; } 7742292SN/A 7752292SN/A /** Sets this instruction as squashed in the LSQ. */ 7762731Sktlim@umich.edu void setSquashedInLSQ() { status.set(SquashedInLSQ);} 7772292SN/A 7782292SN/A /** Returns whether or not this instruction is squashed in the LSQ. */ 7792731Sktlim@umich.edu bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 7802292SN/A 7812292SN/A 7822292SN/A //Reorder Buffer Functions 7832292SN/A //----------------------- 7842292SN/A /** Sets this instruction as a entry the ROB. */ 7852731Sktlim@umich.edu void setInROB() { status.set(RobEntry); } 7862292SN/A 7872292SN/A /** Sets this instruction as a entry the ROB. */ 7882731Sktlim@umich.edu void clearInROB() { status.reset(RobEntry); } 7892731Sktlim@umich.edu 7902731Sktlim@umich.edu /** Returns whether or not this instruction is in the ROB. */ 7912731Sktlim@umich.edu bool isInROB() const { return status[RobEntry]; } 7922292SN/A 7932292SN/A /** Sets this instruction as squashed in the ROB. */ 7942731Sktlim@umich.edu void setSquashedInROB() { status.set(SquashedInROB); } 7952292SN/A 7962292SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 7972731Sktlim@umich.edu bool isSquashedInROB() const { return status[SquashedInROB]; } 7982292SN/A 7997720Sgblack@eecs.umich.edu /** Read the PC state of this instruction. */ 8007720Sgblack@eecs.umich.edu const TheISA::PCState pcState() const { return pc; } 8017720Sgblack@eecs.umich.edu 8027720Sgblack@eecs.umich.edu /** Set the PC state of this instruction. */ 8037720Sgblack@eecs.umich.edu const void pcState(const TheISA::PCState &val) { pc = val; } 8047720Sgblack@eecs.umich.edu 8051060SN/A /** Read the PC of this instruction. */ 8067720Sgblack@eecs.umich.edu const Addr instAddr() const { return pc.instAddr(); } 8077720Sgblack@eecs.umich.edu 8087720Sgblack@eecs.umich.edu /** Read the PC of the next instruction. */ 8097720Sgblack@eecs.umich.edu const Addr nextInstAddr() const { return pc.nextInstAddr(); } 8101060SN/A 8114636Sgblack@eecs.umich.edu /**Read the micro PC of this instruction. */ 8127720Sgblack@eecs.umich.edu const Addr microPC() const { return pc.microPC(); } 8134636Sgblack@eecs.umich.edu 8147597Sminkyu.jeong@arm.com bool readPredicate() 8157597Sminkyu.jeong@arm.com { 8169046SAli.Saidi@ARM.com return instFlags[Predicate]; 8177597Sminkyu.jeong@arm.com } 8187597Sminkyu.jeong@arm.com 8197597Sminkyu.jeong@arm.com void setPredicate(bool val) 8207597Sminkyu.jeong@arm.com { 8219046SAli.Saidi@ARM.com instFlags[Predicate] = val; 8227600Sminkyu.jeong@arm.com 8237600Sminkyu.jeong@arm.com if (traceData) { 8247600Sminkyu.jeong@arm.com traceData->setPredicate(val); 8257600Sminkyu.jeong@arm.com } 8267597Sminkyu.jeong@arm.com } 8277597Sminkyu.jeong@arm.com 8282702Sktlim@umich.edu /** Sets the ASID. */ 8292292SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 8302292SN/A 8312702Sktlim@umich.edu /** Sets the thread id. */ 8326221Snate@binkert.org void setTid(ThreadID tid) { threadNumber = tid; } 8332292SN/A 8342731Sktlim@umich.edu /** Sets the pointer to the thread state. */ 8352702Sktlim@umich.edu void setThreadState(ImplState *state) { thread = state; } 8361060SN/A 8372731Sktlim@umich.edu /** Returns the thread context. */ 8382680Sktlim@umich.edu ThreadContext *tcBase() { return thread->getTC(); } 8391464SN/A 8401464SN/A public: 8411684SN/A /** Sets the effective address. */ 8429046SAli.Saidi@ARM.com void setEA(Addr &ea) { instEffAddr = ea; instFlags[EACalcDone] = true; } 8431684SN/A 8441684SN/A /** Returns the effective address. */ 8451464SN/A const Addr &getEA() const { return instEffAddr; } 8461684SN/A 8471684SN/A /** Returns whether or not the eff. addr. calculation has been completed. */ 8489046SAli.Saidi@ARM.com bool doneEACalc() { return instFlags[EACalcDone]; } 8491684SN/A 8501684SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 8511464SN/A bool eaSrcsReady(); 8521681SN/A 8534032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 8549046SAli.Saidi@ARM.com bool uncacheable() { return instFlags[IsUncacheable]; } 8554032Sktlim@umich.edu 8564032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8579046SAli.Saidi@ARM.com bool hasRequest() { return instFlags[ReqMade]; } 8582292SN/A 8592292SN/A /** Returns iterator to this instruction in the list of all insts. */ 8602292SN/A ListIt &getInstListIt() { return instListIt; } 8612292SN/A 8622292SN/A /** Sets iterator for this instruction in the list of all insts. */ 8632292SN/A void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 8643326Sktlim@umich.edu 8653326Sktlim@umich.edu public: 8663326Sktlim@umich.edu /** Returns the number of consecutive store conditional failures. */ 8673326Sktlim@umich.edu unsigned readStCondFailures() 8683326Sktlim@umich.edu { return thread->storeCondFailures; } 8693326Sktlim@umich.edu 8703326Sktlim@umich.edu /** Sets the number of consecutive store conditional failures. */ 8713326Sktlim@umich.edu void setStCondFailures(unsigned sc_failures) 8723326Sktlim@umich.edu { thread->storeCondFailures = sc_failures; } 8731060SN/A}; 8741060SN/A 8751060SN/Atemplate<class Impl> 8767520Sgblack@eecs.umich.eduFault 8778444Sgblack@eecs.umich.eduBaseDynInst<Impl>::readMem(Addr addr, uint8_t *data, 8788444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 8791060SN/A{ 8809046SAli.Saidi@ARM.com instFlags[ReqMade] = true; 8817944SGiacomo.Gabrielli@arm.com Request *req = NULL; 8826974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 8836974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 8846974Stjones1@inf.ed.ac.uk 8859046SAli.Saidi@ARM.com if (instFlags[ReqMade] && translationStarted()) { 8867944SGiacomo.Gabrielli@arm.com req = savedReq; 8877944SGiacomo.Gabrielli@arm.com sreqLow = savedSreqLow; 8887944SGiacomo.Gabrielli@arm.com sreqHigh = savedSreqHigh; 8897944SGiacomo.Gabrielli@arm.com } else { 8908832SAli.Saidi@ARM.com req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), 8917944SGiacomo.Gabrielli@arm.com thread->contextId(), threadNumber); 8924032Sktlim@umich.edu 8937944SGiacomo.Gabrielli@arm.com // Only split the request if the ISA supports unaligned accesses. 8947944SGiacomo.Gabrielli@arm.com if (TheISA::HasUnalignedMemAcc) { 8957944SGiacomo.Gabrielli@arm.com splitRequest(req, sreqLow, sreqHigh); 8967944SGiacomo.Gabrielli@arm.com } 8977944SGiacomo.Gabrielli@arm.com initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 8981060SN/A } 8991060SN/A 9009046SAli.Saidi@ARM.com if (translationCompleted()) { 9017944SGiacomo.Gabrielli@arm.com if (fault == NoFault) { 9027944SGiacomo.Gabrielli@arm.com effAddr = req->getVaddr(); 9038199SAli.Saidi@ARM.com effSize = size; 9049046SAli.Saidi@ARM.com instFlags[EffAddrValid] = true; 9058887Sgeoffrey.blake@arm.com 9068887Sgeoffrey.blake@arm.com if (cpu->checker) { 9078887Sgeoffrey.blake@arm.com if (reqToVerify != NULL) { 9088887Sgeoffrey.blake@arm.com delete reqToVerify; 9098887Sgeoffrey.blake@arm.com } 9108887Sgeoffrey.blake@arm.com reqToVerify = new Request(*req); 9118733Sgeoffrey.blake@arm.com } 9127944SGiacomo.Gabrielli@arm.com fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); 9137944SGiacomo.Gabrielli@arm.com } else { 9147944SGiacomo.Gabrielli@arm.com // Commit will have to clean up whatever happened. Set this 9157944SGiacomo.Gabrielli@arm.com // instruction as executed. 9167944SGiacomo.Gabrielli@arm.com this->setExecuted(); 9177944SGiacomo.Gabrielli@arm.com } 9187944SGiacomo.Gabrielli@arm.com 9197944SGiacomo.Gabrielli@arm.com if (fault != NoFault) { 9207944SGiacomo.Gabrielli@arm.com // Return a fixed value to keep simulation deterministic even 9217944SGiacomo.Gabrielli@arm.com // along misspeculated paths. 9227944SGiacomo.Gabrielli@arm.com if (data) 9237944SGiacomo.Gabrielli@arm.com bzero(data, size); 9247944SGiacomo.Gabrielli@arm.com } 9257577SAli.Saidi@ARM.com } 9267577SAli.Saidi@ARM.com 9271060SN/A if (traceData) { 9281060SN/A traceData->setAddr(addr); 9291060SN/A } 9301060SN/A 9311060SN/A return fault; 9321060SN/A} 9331060SN/A 9341060SN/Atemplate<class Impl> 9357520Sgblack@eecs.umich.eduFault 9368444Sgblack@eecs.umich.eduBaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, 9378444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 9381060SN/A{ 9391060SN/A if (traceData) { 9401060SN/A traceData->setAddr(addr); 9411060SN/A } 9421060SN/A 9439046SAli.Saidi@ARM.com instFlags[ReqMade] = true; 9447944SGiacomo.Gabrielli@arm.com Request *req = NULL; 9456974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 9466974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 9476974Stjones1@inf.ed.ac.uk 9489046SAli.Saidi@ARM.com if (instFlags[ReqMade] && translationStarted()) { 9497944SGiacomo.Gabrielli@arm.com req = savedReq; 9507944SGiacomo.Gabrielli@arm.com sreqLow = savedSreqLow; 9517944SGiacomo.Gabrielli@arm.com sreqHigh = savedSreqHigh; 9527944SGiacomo.Gabrielli@arm.com } else { 9538832SAli.Saidi@ARM.com req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), 9547944SGiacomo.Gabrielli@arm.com thread->contextId(), threadNumber); 9557944SGiacomo.Gabrielli@arm.com 9567944SGiacomo.Gabrielli@arm.com // Only split the request if the ISA supports unaligned accesses. 9577944SGiacomo.Gabrielli@arm.com if (TheISA::HasUnalignedMemAcc) { 9587944SGiacomo.Gabrielli@arm.com splitRequest(req, sreqLow, sreqHigh); 9597944SGiacomo.Gabrielli@arm.com } 9607944SGiacomo.Gabrielli@arm.com initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 9616974Stjones1@inf.ed.ac.uk } 9624032Sktlim@umich.edu 9639046SAli.Saidi@ARM.com if (fault == NoFault && translationCompleted()) { 9642678Sktlim@umich.edu effAddr = req->getVaddr(); 9658199SAli.Saidi@ARM.com effSize = size; 9669046SAli.Saidi@ARM.com instFlags[EffAddrValid] = true; 9678887Sgeoffrey.blake@arm.com 9688887Sgeoffrey.blake@arm.com if (cpu->checker) { 9698887Sgeoffrey.blake@arm.com if (reqToVerify != NULL) { 9708887Sgeoffrey.blake@arm.com delete reqToVerify; 9718887Sgeoffrey.blake@arm.com } 9728887Sgeoffrey.blake@arm.com reqToVerify = new Request(*req); 9738733Sgeoffrey.blake@arm.com } 9746975Stjones1@inf.ed.ac.uk fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 9751060SN/A } 9761060SN/A 9771060SN/A return fault; 9781060SN/A} 9791060SN/A 9806973Stjones1@inf.ed.ac.uktemplate<class Impl> 9816973Stjones1@inf.ed.ac.ukinline void 9826974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 9836974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh) 9846974Stjones1@inf.ed.ac.uk{ 9856974Stjones1@inf.ed.ac.uk // Check to see if the request crosses the next level block boundary. 9869814Sandreas.hansson@arm.com unsigned block_size = cpu->cacheLineSize(); 9876974Stjones1@inf.ed.ac.uk Addr addr = req->getVaddr(); 9886974Stjones1@inf.ed.ac.uk Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 9896974Stjones1@inf.ed.ac.uk assert(split_addr <= addr || split_addr - addr < block_size); 9906974Stjones1@inf.ed.ac.uk 9916974Stjones1@inf.ed.ac.uk // Spans two blocks. 9926974Stjones1@inf.ed.ac.uk if (split_addr > addr) { 9936974Stjones1@inf.ed.ac.uk req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 9946974Stjones1@inf.ed.ac.uk } 9956974Stjones1@inf.ed.ac.uk} 9966974Stjones1@inf.ed.ac.uk 9976974Stjones1@inf.ed.ac.uktemplate<class Impl> 9986974Stjones1@inf.ed.ac.ukinline void 9996974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 10006974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 10016973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode) 10026973Stjones1@inf.ed.ac.uk{ 10039046SAli.Saidi@ARM.com translationStarted(true); 10047944SGiacomo.Gabrielli@arm.com 10056974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 10066974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 10076974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, NULL, res, mode); 10086974Stjones1@inf.ed.ac.uk 10096974Stjones1@inf.ed.ac.uk // One translation if the request isn't split. 10108486Sgblack@eecs.umich.edu DataTranslation<BaseDynInstPtr> *trans = 10118486Sgblack@eecs.umich.edu new DataTranslation<BaseDynInstPtr>(this, state); 10129932SAli.Saidi@ARM.com 10136974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 10149932SAli.Saidi@ARM.com 10159046SAli.Saidi@ARM.com if (!translationCompleted()) { 10169932SAli.Saidi@ARM.com // The translation isn't yet complete, so we can't possibly have a 10179932SAli.Saidi@ARM.com // fault. Overwrite any existing fault we might have from a previous 10189932SAli.Saidi@ARM.com // execution of this instruction (e.g. an uncachable load that 10199932SAli.Saidi@ARM.com // couldn't execute because it wasn't at the head of the ROB). 10209932SAli.Saidi@ARM.com fault = NoFault; 10219932SAli.Saidi@ARM.com 10227944SGiacomo.Gabrielli@arm.com // Save memory requests. 10237944SGiacomo.Gabrielli@arm.com savedReq = state->mainReq; 10247944SGiacomo.Gabrielli@arm.com savedSreqLow = state->sreqLow; 10257944SGiacomo.Gabrielli@arm.com savedSreqHigh = state->sreqHigh; 10267944SGiacomo.Gabrielli@arm.com } 10276974Stjones1@inf.ed.ac.uk } else { 10286974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 10296974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 10306974Stjones1@inf.ed.ac.uk 10316974Stjones1@inf.ed.ac.uk // Two translations when the request is split. 10328486Sgblack@eecs.umich.edu DataTranslation<BaseDynInstPtr> *stransLow = 10338486Sgblack@eecs.umich.edu new DataTranslation<BaseDynInstPtr>(this, state, 0); 10348486Sgblack@eecs.umich.edu DataTranslation<BaseDynInstPtr> *stransHigh = 10358486Sgblack@eecs.umich.edu new DataTranslation<BaseDynInstPtr>(this, state, 1); 10366974Stjones1@inf.ed.ac.uk 10376974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 10386974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 10399932SAli.Saidi@ARM.com 10409046SAli.Saidi@ARM.com if (!translationCompleted()) { 10419932SAli.Saidi@ARM.com // The translation isn't yet complete, so we can't possibly have a 10429932SAli.Saidi@ARM.com // fault. Overwrite any existing fault we might have from a previous 10439932SAli.Saidi@ARM.com // execution of this instruction (e.g. an uncachable load that 10449932SAli.Saidi@ARM.com // couldn't execute because it wasn't at the head of the ROB). 10459932SAli.Saidi@ARM.com fault = NoFault; 10469932SAli.Saidi@ARM.com 10477944SGiacomo.Gabrielli@arm.com // Save memory requests. 10487944SGiacomo.Gabrielli@arm.com savedReq = state->mainReq; 10497944SGiacomo.Gabrielli@arm.com savedSreqLow = state->sreqLow; 10507944SGiacomo.Gabrielli@arm.com savedSreqHigh = state->sreqHigh; 10517944SGiacomo.Gabrielli@arm.com } 10526974Stjones1@inf.ed.ac.uk } 10536973Stjones1@inf.ed.ac.uk} 10546973Stjones1@inf.ed.ac.uk 10556973Stjones1@inf.ed.ac.uktemplate<class Impl> 10566973Stjones1@inf.ed.ac.ukinline void 10576973Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 10586973Stjones1@inf.ed.ac.uk{ 10596973Stjones1@inf.ed.ac.uk fault = state->getFault(); 10606973Stjones1@inf.ed.ac.uk 10619046SAli.Saidi@ARM.com instFlags[IsUncacheable] = state->isUncacheable(); 10626973Stjones1@inf.ed.ac.uk 10636973Stjones1@inf.ed.ac.uk if (fault == NoFault) { 10646973Stjones1@inf.ed.ac.uk physEffAddr = state->getPaddr(); 10656973Stjones1@inf.ed.ac.uk memReqFlags = state->getFlags(); 10666973Stjones1@inf.ed.ac.uk 10676973Stjones1@inf.ed.ac.uk if (state->mainReq->isCondSwap()) { 10686973Stjones1@inf.ed.ac.uk assert(state->res); 10696973Stjones1@inf.ed.ac.uk state->mainReq->setExtraData(*state->res); 10706973Stjones1@inf.ed.ac.uk } 10716973Stjones1@inf.ed.ac.uk 10726973Stjones1@inf.ed.ac.uk } else { 10736973Stjones1@inf.ed.ac.uk state->deleteReqs(); 10746973Stjones1@inf.ed.ac.uk } 10756973Stjones1@inf.ed.ac.uk delete state; 10767944SGiacomo.Gabrielli@arm.com 10779046SAli.Saidi@ARM.com translationCompleted(true); 10786973Stjones1@inf.ed.ac.uk} 10796973Stjones1@inf.ed.ac.uk 10801464SN/A#endif // __CPU_BASE_DYN_INST_HH__ 1081