base_dyn_inst.hh revision 9044
11060SN/A/* 27944SGiacomo.Gabrielli@arm.com * Copyright (c) 2011 ARM Limited 37944SGiacomo.Gabrielli@arm.com * All rights reserved. 47944SGiacomo.Gabrielli@arm.com * 57944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137944SGiacomo.Gabrielli@arm.com * 142702Sktlim@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 156973Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The University of Edinburgh 161060SN/A * All rights reserved. 171060SN/A * 181060SN/A * Redistribution and use in source and binary forms, with or without 191060SN/A * modification, are permitted provided that the following conditions are 201060SN/A * met: redistributions of source code must retain the above copyright 211060SN/A * notice, this list of conditions and the following disclaimer; 221060SN/A * redistributions in binary form must reproduce the above copyright 231060SN/A * notice, this list of conditions and the following disclaimer in the 241060SN/A * documentation and/or other materials provided with the distribution; 251060SN/A * neither the name of the copyright holders nor the names of its 261060SN/A * contributors may be used to endorse or promote products derived from 271060SN/A * this software without specific prior written permission. 281060SN/A * 291060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 426973Stjones1@inf.ed.ac.uk * Timothy M. Jones 431060SN/A */ 441060SN/A 451464SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 461464SN/A#define __CPU_BASE_DYN_INST_HH__ 471060SN/A 482731Sktlim@umich.edu#include <bitset> 492292SN/A#include <list> 501464SN/A#include <string> 518733Sgeoffrey.blake@arm.com#include <queue> 521060SN/A 537720Sgblack@eecs.umich.edu#include "arch/utility.hh" 541060SN/A#include "base/trace.hh" 556658Snate@binkert.org#include "config/the_isa.hh" 568887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 573770Sgblack@eecs.umich.edu#include "cpu/o3/comm.hh" 581464SN/A#include "cpu/exetrace.hh" 591464SN/A#include "cpu/inst_seq.hh" 602669Sktlim@umich.edu#include "cpu/op_class.hh" 611060SN/A#include "cpu/static_inst.hh" 626973Stjones1@inf.ed.ac.uk#include "cpu/translation.hh" 632669Sktlim@umich.edu#include "mem/packet.hh" 647678Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 658817Sgblack@eecs.umich.edu#include "sim/fault_fwd.hh" 662292SN/A#include "sim/system.hh" 676023Snate@binkert.org#include "sim/tlb.hh" 681060SN/A 691060SN/A/** 701060SN/A * @file 711060SN/A * Defines a dynamic instruction context. 721060SN/A */ 731060SN/A 741060SN/Atemplate <class Impl> 759044SAli.Saidi@ARM.comclass BaseDynInst : public RefCounted 761060SN/A{ 771060SN/A public: 781060SN/A // Typedef for the CPU. 792733Sktlim@umich.edu typedef typename Impl::CPUType ImplCPU; 802733Sktlim@umich.edu typedef typename ImplCPU::ImplState ImplState; 811060SN/A 822292SN/A // Logical register index type. 832107SN/A typedef TheISA::RegIndex RegIndex; 842690Sktlim@umich.edu // Integer register type. 852107SN/A typedef TheISA::IntReg IntReg; 862690Sktlim@umich.edu // Floating point register type. 872690Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 881060SN/A 892292SN/A // The DynInstPtr type. 902292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 918486Sgblack@eecs.umich.edu typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 922292SN/A 932292SN/A // The list of instructions iterator type. 942292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 952292SN/A 961060SN/A enum { 975543Ssaidi@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 988902Sandreas.hansson@arm.com MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs 991060SN/A }; 1001060SN/A 1012292SN/A /** The StaticInst used by this BaseDynInst. */ 1022107SN/A StaticInstPtr staticInst; 1038502Sgblack@eecs.umich.edu StaticInstPtr macroop; 1041060SN/A 1051060SN/A //////////////////////////////////////////// 1061060SN/A // 1071060SN/A // INSTRUCTION EXECUTION 1081060SN/A // 1091060SN/A //////////////////////////////////////////// 1102292SN/A /** InstRecord that tracks this instructions. */ 1111060SN/A Trace::InstRecord *traceData; 1121060SN/A 1135358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1145358Sgblack@eecs.umich.edu { 1155358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1165358Sgblack@eecs.umich.edu } 1175358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1185358Sgblack@eecs.umich.edu { 1195358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1205358Sgblack@eecs.umich.edu } 1215358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1225358Sgblack@eecs.umich.edu { 1235358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1245358Sgblack@eecs.umich.edu } 1255358Sgblack@eecs.umich.edu 1268444Sgblack@eecs.umich.edu Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 1277520Sgblack@eecs.umich.edu 1288444Sgblack@eecs.umich.edu Fault writeMem(uint8_t *data, unsigned size, 1298444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res); 1307520Sgblack@eecs.umich.edu 1316974Stjones1@inf.ed.ac.uk /** Splits a request in two if it crosses a dcache block. */ 1326974Stjones1@inf.ed.ac.uk void splitRequest(RequestPtr req, RequestPtr &sreqLow, 1336974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh); 1346974Stjones1@inf.ed.ac.uk 1356973Stjones1@inf.ed.ac.uk /** Initiate a DTB address translation. */ 1366974Stjones1@inf.ed.ac.uk void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 1376974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 1386973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode); 1396973Stjones1@inf.ed.ac.uk 1406973Stjones1@inf.ed.ac.uk /** Finish a DTB address translation. */ 1416973Stjones1@inf.ed.ac.uk void finishTranslation(WholeTranslationState *state); 1421060SN/A 1437944SGiacomo.Gabrielli@arm.com /** True if the DTB address translation has started. */ 1447944SGiacomo.Gabrielli@arm.com bool translationStarted; 1457944SGiacomo.Gabrielli@arm.com 1467944SGiacomo.Gabrielli@arm.com /** True if the DTB address translation has completed. */ 1477944SGiacomo.Gabrielli@arm.com bool translationCompleted; 1487944SGiacomo.Gabrielli@arm.com 1498545Ssaidi@eecs.umich.edu /** True if this address was found to match a previous load and they issued 1508545Ssaidi@eecs.umich.edu * out of order. If that happend, then it's only a problem if an incoming 1518545Ssaidi@eecs.umich.edu * snoop invalidate modifies the line, in which case we need to squash. 1528545Ssaidi@eecs.umich.edu * If nothing modified the line the order doesn't matter. 1538545Ssaidi@eecs.umich.edu */ 1548545Ssaidi@eecs.umich.edu bool possibleLoadViolation; 1558545Ssaidi@eecs.umich.edu 1568545Ssaidi@eecs.umich.edu /** True if the address hit a external snoop while sitting in the LSQ. 1578545Ssaidi@eecs.umich.edu * If this is true and a older instruction sees it, this instruction must 1588545Ssaidi@eecs.umich.edu * reexecute 1598545Ssaidi@eecs.umich.edu */ 1608545Ssaidi@eecs.umich.edu bool hitExternalSnoop; 1618545Ssaidi@eecs.umich.edu 1627944SGiacomo.Gabrielli@arm.com /** 1637944SGiacomo.Gabrielli@arm.com * Returns true if the DTB address translation is being delayed due to a hw 1647944SGiacomo.Gabrielli@arm.com * page table walk. 1657944SGiacomo.Gabrielli@arm.com */ 1667944SGiacomo.Gabrielli@arm.com bool isTranslationDelayed() const 1677944SGiacomo.Gabrielli@arm.com { 1687944SGiacomo.Gabrielli@arm.com return (translationStarted && !translationCompleted); 1697944SGiacomo.Gabrielli@arm.com } 1707944SGiacomo.Gabrielli@arm.com 1717944SGiacomo.Gabrielli@arm.com /** 1727944SGiacomo.Gabrielli@arm.com * Saved memory requests (needed when the DTB address translation is 1737944SGiacomo.Gabrielli@arm.com * delayed due to a hw page table walk). 1747944SGiacomo.Gabrielli@arm.com */ 1757944SGiacomo.Gabrielli@arm.com RequestPtr savedReq; 1767944SGiacomo.Gabrielli@arm.com RequestPtr savedSreqLow; 1777944SGiacomo.Gabrielli@arm.com RequestPtr savedSreqHigh; 1787944SGiacomo.Gabrielli@arm.com 1798733Sgeoffrey.blake@arm.com // Need a copy of main request pointer to verify on writes. 1808733Sgeoffrey.blake@arm.com RequestPtr reqToVerify; 1818733Sgeoffrey.blake@arm.com 1821684SN/A /** @todo: Consider making this private. */ 1831060SN/A public: 1841060SN/A /** The sequence number of the instruction. */ 1851060SN/A InstSeqNum seqNum; 1861060SN/A 1872731Sktlim@umich.edu enum Status { 1882731Sktlim@umich.edu IqEntry, /// Instruction is in the IQ 1892731Sktlim@umich.edu RobEntry, /// Instruction is in the ROB 1902731Sktlim@umich.edu LsqEntry, /// Instruction is in the LSQ 1912731Sktlim@umich.edu Completed, /// Instruction has completed 1922731Sktlim@umich.edu ResultReady, /// Instruction has its result 1932731Sktlim@umich.edu CanIssue, /// Instruction can issue and execute 1942731Sktlim@umich.edu Issued, /// Instruction has issued 1952731Sktlim@umich.edu Executed, /// Instruction has executed 1962731Sktlim@umich.edu CanCommit, /// Instruction can commit 1972731Sktlim@umich.edu AtCommit, /// Instruction has reached commit 1982731Sktlim@umich.edu Committed, /// Instruction has committed 1992731Sktlim@umich.edu Squashed, /// Instruction is squashed 2002731Sktlim@umich.edu SquashedInIQ, /// Instruction is squashed in the IQ 2012731Sktlim@umich.edu SquashedInLSQ, /// Instruction is squashed in the LSQ 2022731Sktlim@umich.edu SquashedInROB, /// Instruction is squashed in the ROB 2032731Sktlim@umich.edu RecoverInst, /// Is a recover instruction 2042731Sktlim@umich.edu BlockingInst, /// Is a blocking instruction 2052731Sktlim@umich.edu ThreadsyncWait, /// Is a thread synchronization instruction 2062731Sktlim@umich.edu SerializeBefore, /// Needs to serialize on 2072731Sktlim@umich.edu /// instructions ahead of it 2082731Sktlim@umich.edu SerializeAfter, /// Needs to serialize instructions behind it 2092731Sktlim@umich.edu SerializeHandled, /// Serialization has been handled 2102731Sktlim@umich.edu NumStatus 2112731Sktlim@umich.edu }; 2122292SN/A 2132731Sktlim@umich.edu /** The status of this BaseDynInst. Several bits can be set. */ 2142731Sktlim@umich.edu std::bitset<NumStatus> status; 2151060SN/A 2161060SN/A /** The thread this instruction is from. */ 2176221Snate@binkert.org ThreadID threadNumber; 2181060SN/A 2191060SN/A /** data address space ID, for loads & stores. */ 2201060SN/A short asid; 2211060SN/A 2222292SN/A /** How many source registers are ready. */ 2232292SN/A unsigned readyRegs; 2242292SN/A 2252733Sktlim@umich.edu /** Pointer to the Impl's CPU object. */ 2262733Sktlim@umich.edu ImplCPU *cpu; 2271060SN/A 2282680Sktlim@umich.edu /** Pointer to the thread state. */ 2292292SN/A ImplState *thread; 2301060SN/A 2311060SN/A /** The kind of fault this instruction has generated. */ 2322132SN/A Fault fault; 2331060SN/A 2342702Sktlim@umich.edu /** Pointer to the data for the memory access. */ 2352669Sktlim@umich.edu uint8_t *memData; 2362292SN/A 2371060SN/A /** The effective virtual address (lds & stores only). */ 2381060SN/A Addr effAddr; 2391060SN/A 2408199SAli.Saidi@ARM.com /** The size of the request */ 2418199SAli.Saidi@ARM.com Addr effSize; 2428199SAli.Saidi@ARM.com 2434032Sktlim@umich.edu /** Is the effective virtual address valid. */ 2444032Sktlim@umich.edu bool effAddrValid; 2454032Sktlim@umich.edu 2461060SN/A /** The effective physical address. */ 2471060SN/A Addr physEffAddr; 2481060SN/A 2491060SN/A /** The memory request flags (from translation). */ 2501060SN/A unsigned memReqFlags; 2511060SN/A 2521464SN/A union Result { 2531464SN/A uint64_t integer; 2541464SN/A double dbl; 2558733Sgeoffrey.blake@arm.com void set(uint64_t i) { integer = i; } 2568733Sgeoffrey.blake@arm.com void set(double d) { dbl = d; } 2578733Sgeoffrey.blake@arm.com void get(uint64_t& i) { i = integer; } 2588733Sgeoffrey.blake@arm.com void get(double& d) { d = dbl; } 2591464SN/A }; 2601060SN/A 2618733Sgeoffrey.blake@arm.com /** The result of the instruction; assumes an instruction can have many 2628733Sgeoffrey.blake@arm.com * destination registers. 2631464SN/A */ 2648733Sgeoffrey.blake@arm.com std::queue<Result> instResult; 2651060SN/A 2663326Sktlim@umich.edu /** Records changes to result? */ 2673326Sktlim@umich.edu bool recordResult; 2683326Sktlim@umich.edu 2697597Sminkyu.jeong@arm.com /** Did this instruction execute, or is it predicated false */ 2707597Sminkyu.jeong@arm.com bool predicate; 2717597Sminkyu.jeong@arm.com 2723965Sgblack@eecs.umich.edu protected: 2737720Sgblack@eecs.umich.edu /** PC state for this instruction. */ 2747720Sgblack@eecs.umich.edu TheISA::PCState pc; 2751060SN/A 2767720Sgblack@eecs.umich.edu /** Predicted PC state after this instruction. */ 2777720Sgblack@eecs.umich.edu TheISA::PCState predPC; 2784636Sgblack@eecs.umich.edu 2793794Sgblack@eecs.umich.edu /** If this is a branch that was predicted taken */ 2803794Sgblack@eecs.umich.edu bool predTaken; 2813794Sgblack@eecs.umich.edu 2823965Sgblack@eecs.umich.edu public: 2833965Sgblack@eecs.umich.edu 2842292SN/A#ifdef DEBUG 2852292SN/A void dumpSNList(); 2862292SN/A#endif 2872292SN/A 2882292SN/A /** Whether or not the source register is ready. 2892292SN/A * @todo: Not sure this should be here vs the derived class. 2901060SN/A */ 2911060SN/A bool _readySrcRegIdx[MaxInstSrcRegs]; 2921060SN/A 2933770Sgblack@eecs.umich.edu protected: 2943770Sgblack@eecs.umich.edu /** Flattened register index of the destination registers of this 2953770Sgblack@eecs.umich.edu * instruction. 2963770Sgblack@eecs.umich.edu */ 2973770Sgblack@eecs.umich.edu TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 2983770Sgblack@eecs.umich.edu 2993770Sgblack@eecs.umich.edu /** Flattened register index of the source registers of this 3003770Sgblack@eecs.umich.edu * instruction. 3013770Sgblack@eecs.umich.edu */ 3023770Sgblack@eecs.umich.edu TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 3033770Sgblack@eecs.umich.edu 3043770Sgblack@eecs.umich.edu /** Physical register index of the destination registers of this 3053770Sgblack@eecs.umich.edu * instruction. 3063770Sgblack@eecs.umich.edu */ 3073770Sgblack@eecs.umich.edu PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 3083770Sgblack@eecs.umich.edu 3093770Sgblack@eecs.umich.edu /** Physical register index of the source registers of this 3103770Sgblack@eecs.umich.edu * instruction. 3113770Sgblack@eecs.umich.edu */ 3123770Sgblack@eecs.umich.edu PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 3133770Sgblack@eecs.umich.edu 3143770Sgblack@eecs.umich.edu /** Physical register index of the previous producers of the 3153770Sgblack@eecs.umich.edu * architected destinations. 3163770Sgblack@eecs.umich.edu */ 3173770Sgblack@eecs.umich.edu PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 3183770Sgblack@eecs.umich.edu 3191060SN/A public: 3203770Sgblack@eecs.umich.edu 3213770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th destination 3223770Sgblack@eecs.umich.edu * register. 3233770Sgblack@eecs.umich.edu */ 3243770Sgblack@eecs.umich.edu PhysRegIndex renamedDestRegIdx(int idx) const 3253770Sgblack@eecs.umich.edu { 3263770Sgblack@eecs.umich.edu return _destRegIdx[idx]; 3273770Sgblack@eecs.umich.edu } 3283770Sgblack@eecs.umich.edu 3293770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th source register. */ 3303770Sgblack@eecs.umich.edu PhysRegIndex renamedSrcRegIdx(int idx) const 3313770Sgblack@eecs.umich.edu { 3323770Sgblack@eecs.umich.edu return _srcRegIdx[idx]; 3333770Sgblack@eecs.umich.edu } 3343770Sgblack@eecs.umich.edu 3353770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th destination 3363770Sgblack@eecs.umich.edu * register. 3373770Sgblack@eecs.umich.edu */ 3383770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedDestRegIdx(int idx) const 3393770Sgblack@eecs.umich.edu { 3403770Sgblack@eecs.umich.edu return _flatDestRegIdx[idx]; 3413770Sgblack@eecs.umich.edu } 3423770Sgblack@eecs.umich.edu 3433770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th source register */ 3443770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedSrcRegIdx(int idx) const 3453770Sgblack@eecs.umich.edu { 3463770Sgblack@eecs.umich.edu return _flatSrcRegIdx[idx]; 3473770Sgblack@eecs.umich.edu } 3483770Sgblack@eecs.umich.edu 3493770Sgblack@eecs.umich.edu /** Returns the physical register index of the previous physical register 3503770Sgblack@eecs.umich.edu * that remapped to the same logical register index. 3513770Sgblack@eecs.umich.edu */ 3523770Sgblack@eecs.umich.edu PhysRegIndex prevDestRegIdx(int idx) const 3533770Sgblack@eecs.umich.edu { 3543770Sgblack@eecs.umich.edu return _prevDestRegIdx[idx]; 3553770Sgblack@eecs.umich.edu } 3563770Sgblack@eecs.umich.edu 3573770Sgblack@eecs.umich.edu /** Renames a destination register to a physical register. Also records 3583770Sgblack@eecs.umich.edu * the previous physical register that the logical register mapped to. 3593770Sgblack@eecs.umich.edu */ 3603770Sgblack@eecs.umich.edu void renameDestReg(int idx, 3613770Sgblack@eecs.umich.edu PhysRegIndex renamed_dest, 3623770Sgblack@eecs.umich.edu PhysRegIndex previous_rename) 3633770Sgblack@eecs.umich.edu { 3643770Sgblack@eecs.umich.edu _destRegIdx[idx] = renamed_dest; 3653770Sgblack@eecs.umich.edu _prevDestRegIdx[idx] = previous_rename; 3663770Sgblack@eecs.umich.edu } 3673770Sgblack@eecs.umich.edu 3683770Sgblack@eecs.umich.edu /** Renames a source logical register to the physical register which 3693770Sgblack@eecs.umich.edu * has/will produce that logical register's result. 3703770Sgblack@eecs.umich.edu * @todo: add in whether or not the source register is ready. 3713770Sgblack@eecs.umich.edu */ 3723770Sgblack@eecs.umich.edu void renameSrcReg(int idx, PhysRegIndex renamed_src) 3733770Sgblack@eecs.umich.edu { 3743770Sgblack@eecs.umich.edu _srcRegIdx[idx] = renamed_src; 3753770Sgblack@eecs.umich.edu } 3763770Sgblack@eecs.umich.edu 3773770Sgblack@eecs.umich.edu /** Flattens a source architectural register index into a logical index. 3783770Sgblack@eecs.umich.edu */ 3793770Sgblack@eecs.umich.edu void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 3803770Sgblack@eecs.umich.edu { 3813770Sgblack@eecs.umich.edu _flatSrcRegIdx[idx] = flattened_src; 3823770Sgblack@eecs.umich.edu } 3833770Sgblack@eecs.umich.edu 3843770Sgblack@eecs.umich.edu /** Flattens a destination architectural register index into a logical 3853770Sgblack@eecs.umich.edu * index. 3863770Sgblack@eecs.umich.edu */ 3873770Sgblack@eecs.umich.edu void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 3883770Sgblack@eecs.umich.edu { 3893770Sgblack@eecs.umich.edu _flatDestRegIdx[idx] = flattened_dest; 3903770Sgblack@eecs.umich.edu } 3914636Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. 3924636Sgblack@eecs.umich.edu * @param staticInst A StaticInstPtr to the underlying instruction. 3937720Sgblack@eecs.umich.edu * @param pc The PC state for the instruction. 3947720Sgblack@eecs.umich.edu * @param predPC The predicted next PC state for the instruction. 3954636Sgblack@eecs.umich.edu * @param seq_num The sequence number of the instruction. 3964636Sgblack@eecs.umich.edu * @param cpu Pointer to the instruction's CPU. 3974636Sgblack@eecs.umich.edu */ 3988502Sgblack@eecs.umich.edu BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop, 3998502Sgblack@eecs.umich.edu TheISA::PCState pc, TheISA::PCState predPC, 4008502Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu); 4013770Sgblack@eecs.umich.edu 4022292SN/A /** BaseDynInst constructor given a StaticInst pointer. 4032292SN/A * @param _staticInst The StaticInst for this BaseDynInst. 4042292SN/A */ 4058502Sgblack@eecs.umich.edu BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop); 4061060SN/A 4071060SN/A /** BaseDynInst destructor. */ 4081060SN/A ~BaseDynInst(); 4091060SN/A 4101464SN/A private: 4111684SN/A /** Function to initialize variables in the constructors. */ 4121464SN/A void initVars(); 4131060SN/A 4141464SN/A public: 4151060SN/A /** Dumps out contents of this BaseDynInst. */ 4161060SN/A void dump(); 4171060SN/A 4181060SN/A /** Dumps out contents of this BaseDynInst into given string. */ 4191060SN/A void dump(std::string &outstring); 4201060SN/A 4213326Sktlim@umich.edu /** Read this CPU's ID. */ 4225712Shsul@eecs.umich.edu int cpuId() { return cpu->cpuId(); } 4233326Sktlim@umich.edu 4248832SAli.Saidi@ARM.com /** Read this CPU's data requestor ID */ 4258832SAli.Saidi@ARM.com MasterID masterId() { return cpu->dataMasterId(); } 4268832SAli.Saidi@ARM.com 4275714Shsul@eecs.umich.edu /** Read this context's system-wide ID **/ 4285714Shsul@eecs.umich.edu int contextId() { return thread->contextId(); } 4295714Shsul@eecs.umich.edu 4301060SN/A /** Returns the fault type. */ 4312132SN/A Fault getFault() { return fault; } 4321060SN/A 4331060SN/A /** Checks whether or not this instruction has had its branch target 4341060SN/A * calculated yet. For now it is not utilized and is hacked to be 4351060SN/A * always false. 4362292SN/A * @todo: Actually use this instruction. 4371060SN/A */ 4381060SN/A bool doneTargCalc() { return false; } 4391060SN/A 4407720Sgblack@eecs.umich.edu /** Set the predicted target of this current instruction. */ 4417720Sgblack@eecs.umich.edu void setPredTarg(const TheISA::PCState &_predPC) 4423965Sgblack@eecs.umich.edu { 4437720Sgblack@eecs.umich.edu predPC = _predPC; 4443965Sgblack@eecs.umich.edu } 4452935Sksewell@umich.edu 4467720Sgblack@eecs.umich.edu const TheISA::PCState &readPredTarg() { return predPC; } 4471060SN/A 4483794Sgblack@eecs.umich.edu /** Returns the predicted PC immediately after the branch. */ 4497720Sgblack@eecs.umich.edu Addr predInstAddr() { return predPC.instAddr(); } 4503794Sgblack@eecs.umich.edu 4513794Sgblack@eecs.umich.edu /** Returns the predicted PC two instructions after the branch */ 4527720Sgblack@eecs.umich.edu Addr predNextInstAddr() { return predPC.nextInstAddr(); } 4531060SN/A 4544636Sgblack@eecs.umich.edu /** Returns the predicted micro PC after the branch */ 4557720Sgblack@eecs.umich.edu Addr predMicroPC() { return predPC.microPC(); } 4564636Sgblack@eecs.umich.edu 4571060SN/A /** Returns whether the instruction was predicted taken or not. */ 4583794Sgblack@eecs.umich.edu bool readPredTaken() 4593794Sgblack@eecs.umich.edu { 4603794Sgblack@eecs.umich.edu return predTaken; 4613794Sgblack@eecs.umich.edu } 4623794Sgblack@eecs.umich.edu 4633794Sgblack@eecs.umich.edu void setPredTaken(bool predicted_taken) 4643794Sgblack@eecs.umich.edu { 4653794Sgblack@eecs.umich.edu predTaken = predicted_taken; 4663794Sgblack@eecs.umich.edu } 4671060SN/A 4681060SN/A /** Returns whether the instruction mispredicted. */ 4692935Sksewell@umich.edu bool mispredicted() 4703794Sgblack@eecs.umich.edu { 4717720Sgblack@eecs.umich.edu TheISA::PCState tempPC = pc; 4727720Sgblack@eecs.umich.edu TheISA::advancePC(tempPC, staticInst); 4737720Sgblack@eecs.umich.edu return !(tempPC == predPC); 4743794Sgblack@eecs.umich.edu } 4753794Sgblack@eecs.umich.edu 4761060SN/A // 4771060SN/A // Instruction types. Forward checks to StaticInst object. 4781060SN/A // 4795543Ssaidi@eecs.umich.edu bool isNop() const { return staticInst->isNop(); } 4805543Ssaidi@eecs.umich.edu bool isMemRef() const { return staticInst->isMemRef(); } 4815543Ssaidi@eecs.umich.edu bool isLoad() const { return staticInst->isLoad(); } 4825543Ssaidi@eecs.umich.edu bool isStore() const { return staticInst->isStore(); } 4832336SN/A bool isStoreConditional() const 4842336SN/A { return staticInst->isStoreConditional(); } 4851060SN/A bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 4861060SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 4875543Ssaidi@eecs.umich.edu bool isInteger() const { return staticInst->isInteger(); } 4885543Ssaidi@eecs.umich.edu bool isFloating() const { return staticInst->isFloating(); } 4895543Ssaidi@eecs.umich.edu bool isControl() const { return staticInst->isControl(); } 4905543Ssaidi@eecs.umich.edu bool isCall() const { return staticInst->isCall(); } 4915543Ssaidi@eecs.umich.edu bool isReturn() const { return staticInst->isReturn(); } 4925543Ssaidi@eecs.umich.edu bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 4931060SN/A bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 4945543Ssaidi@eecs.umich.edu bool isCondCtrl() const { return staticInst->isCondCtrl(); } 4955543Ssaidi@eecs.umich.edu bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 4962935Sksewell@umich.edu bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 4971060SN/A bool isThreadSync() const { return staticInst->isThreadSync(); } 4981060SN/A bool isSerializing() const { return staticInst->isSerializing(); } 4992292SN/A bool isSerializeBefore() const 5002731Sktlim@umich.edu { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 5012292SN/A bool isSerializeAfter() const 5022731Sktlim@umich.edu { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 5037784SAli.Saidi@ARM.com bool isSquashAfter() const { return staticInst->isSquashAfter(); } 5041060SN/A bool isMemBarrier() const { return staticInst->isMemBarrier(); } 5051060SN/A bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 5061060SN/A bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 5072292SN/A bool isQuiesce() const { return staticInst->isQuiesce(); } 5082336SN/A bool isIprAccess() const { return staticInst->isIprAccess(); } 5092308SN/A bool isUnverifiable() const { return staticInst->isUnverifiable(); } 5104828Sgblack@eecs.umich.edu bool isSyscall() const { return staticInst->isSyscall(); } 5114654Sgblack@eecs.umich.edu bool isMacroop() const { return staticInst->isMacroop(); } 5124654Sgblack@eecs.umich.edu bool isMicroop() const { return staticInst->isMicroop(); } 5134636Sgblack@eecs.umich.edu bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 5144654Sgblack@eecs.umich.edu bool isLastMicroop() const { return staticInst->isLastMicroop(); } 5154654Sgblack@eecs.umich.edu bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 5164636Sgblack@eecs.umich.edu bool isMicroBranch() const { return staticInst->isMicroBranch(); } 5172292SN/A 5182292SN/A /** Temporarily sets this instruction as a serialize before instruction. */ 5192731Sktlim@umich.edu void setSerializeBefore() { status.set(SerializeBefore); } 5202292SN/A 5212292SN/A /** Clears the serializeBefore part of this instruction. */ 5222731Sktlim@umich.edu void clearSerializeBefore() { status.reset(SerializeBefore); } 5232292SN/A 5242292SN/A /** Checks if this serializeBefore is only temporarily set. */ 5252731Sktlim@umich.edu bool isTempSerializeBefore() { return status[SerializeBefore]; } 5262292SN/A 5272292SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 5282731Sktlim@umich.edu void setSerializeAfter() { status.set(SerializeAfter); } 5292292SN/A 5302292SN/A /** Clears the serializeAfter part of this instruction.*/ 5312731Sktlim@umich.edu void clearSerializeAfter() { status.reset(SerializeAfter); } 5322292SN/A 5332292SN/A /** Checks if this serializeAfter is only temporarily set. */ 5342731Sktlim@umich.edu bool isTempSerializeAfter() { return status[SerializeAfter]; } 5352292SN/A 5362731Sktlim@umich.edu /** Sets the serialization part of this instruction as handled. */ 5372731Sktlim@umich.edu void setSerializeHandled() { status.set(SerializeHandled); } 5382292SN/A 5392292SN/A /** Checks if the serialization part of this instruction has been 5402292SN/A * handled. This does not apply to the temporary serializing 5412292SN/A * state; it only applies to this instruction's own permanent 5422292SN/A * serializing state. 5432292SN/A */ 5442731Sktlim@umich.edu bool isSerializeHandled() { return status[SerializeHandled]; } 5451060SN/A 5461464SN/A /** Returns the opclass of this instruction. */ 5471464SN/A OpClass opClass() const { return staticInst->opClass(); } 5481464SN/A 5491464SN/A /** Returns the branch target address. */ 5507720Sgblack@eecs.umich.edu TheISA::PCState branchTarget() const 5517720Sgblack@eecs.umich.edu { return staticInst->branchTarget(pc); } 5521464SN/A 5532292SN/A /** Returns the number of source registers. */ 5545543Ssaidi@eecs.umich.edu int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 5551684SN/A 5562292SN/A /** Returns the number of destination registers. */ 5571060SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 5581060SN/A 5591060SN/A // the following are used to track physical register usage 5601060SN/A // for machines with separate int & FP reg files 5611060SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 5621060SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 5631060SN/A 5641060SN/A /** Returns the logical register index of the i'th destination register. */ 5652292SN/A RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 5661060SN/A 5671060SN/A /** Returns the logical register index of the i'th source register. */ 5682292SN/A RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 5691060SN/A 5708733Sgeoffrey.blake@arm.com /** Pops a result off the instResult queue */ 5718733Sgeoffrey.blake@arm.com template <class T> 5728733Sgeoffrey.blake@arm.com void popResult(T& t) 5738733Sgeoffrey.blake@arm.com { 5748733Sgeoffrey.blake@arm.com if (!instResult.empty()) { 5758733Sgeoffrey.blake@arm.com instResult.front().get(t); 5768733Sgeoffrey.blake@arm.com instResult.pop(); 5778733Sgeoffrey.blake@arm.com } 5788733Sgeoffrey.blake@arm.com } 5791684SN/A 5808733Sgeoffrey.blake@arm.com /** Read the most recent result stored by this instruction */ 5818733Sgeoffrey.blake@arm.com template <class T> 5828733Sgeoffrey.blake@arm.com void readResult(T& t) 5838733Sgeoffrey.blake@arm.com { 5848733Sgeoffrey.blake@arm.com instResult.back().get(t); 5858733Sgeoffrey.blake@arm.com } 5861684SN/A 5878733Sgeoffrey.blake@arm.com /** Pushes a result onto the instResult queue */ 5888733Sgeoffrey.blake@arm.com template <class T> 5898733Sgeoffrey.blake@arm.com void setResult(T t) 5908733Sgeoffrey.blake@arm.com { 5918733Sgeoffrey.blake@arm.com if (recordResult) { 5928733Sgeoffrey.blake@arm.com Result instRes; 5938733Sgeoffrey.blake@arm.com instRes.set(t); 5948733Sgeoffrey.blake@arm.com instResult.push(instRes); 5958733Sgeoffrey.blake@arm.com } 5968733Sgeoffrey.blake@arm.com } 5971060SN/A 5982702Sktlim@umich.edu /** Records an integer register being set to a value. */ 5993735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 6001060SN/A { 6018733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 6021060SN/A } 6031060SN/A 6042702Sktlim@umich.edu /** Records an fp register being set to a value. */ 6053735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 6063735Sstever@eecs.umich.edu int width) 6072690Sktlim@umich.edu { 6088733Sgeoffrey.blake@arm.com if (width == 32 || width == 64) { 6098733Sgeoffrey.blake@arm.com setResult<double>(val); 6108733Sgeoffrey.blake@arm.com } else { 6118733Sgeoffrey.blake@arm.com panic("Unsupported width!"); 6123326Sktlim@umich.edu } 6132690Sktlim@umich.edu } 6142690Sktlim@umich.edu 6152702Sktlim@umich.edu /** Records an fp register being set to a value. */ 6163735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 6171060SN/A { 6188733Sgeoffrey.blake@arm.com setResult<double>(val); 6192308SN/A } 6201060SN/A 6212702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 6223735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 6233735Sstever@eecs.umich.edu int width) 6242308SN/A { 6258733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 6262308SN/A } 6271060SN/A 6282702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 6293735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 6302308SN/A { 6318733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 6321060SN/A } 6331060SN/A 6342190SN/A /** Records that one of the source registers is ready. */ 6352292SN/A void markSrcRegReady(); 6362190SN/A 6372331SN/A /** Marks a specific register as ready. */ 6382292SN/A void markSrcRegReady(RegIndex src_idx); 6392190SN/A 6401684SN/A /** Returns if a source register is ready. */ 6411464SN/A bool isReadySrcRegIdx(int idx) const 6421464SN/A { 6431464SN/A return this->_readySrcRegIdx[idx]; 6441464SN/A } 6451464SN/A 6461684SN/A /** Sets this instruction as completed. */ 6472731Sktlim@umich.edu void setCompleted() { status.set(Completed); } 6481464SN/A 6492292SN/A /** Returns whether or not this instruction is completed. */ 6502731Sktlim@umich.edu bool isCompleted() const { return status[Completed]; } 6511464SN/A 6522731Sktlim@umich.edu /** Marks the result as ready. */ 6532731Sktlim@umich.edu void setResultReady() { status.set(ResultReady); } 6542308SN/A 6552731Sktlim@umich.edu /** Returns whether or not the result is ready. */ 6562731Sktlim@umich.edu bool isResultReady() const { return status[ResultReady]; } 6572308SN/A 6581060SN/A /** Sets this instruction as ready to issue. */ 6592731Sktlim@umich.edu void setCanIssue() { status.set(CanIssue); } 6601060SN/A 6611060SN/A /** Returns whether or not this instruction is ready to issue. */ 6622731Sktlim@umich.edu bool readyToIssue() const { return status[CanIssue]; } 6631060SN/A 6644032Sktlim@umich.edu /** Clears this instruction being able to issue. */ 6654032Sktlim@umich.edu void clearCanIssue() { status.reset(CanIssue); } 6664032Sktlim@umich.edu 6671060SN/A /** Sets this instruction as issued from the IQ. */ 6682731Sktlim@umich.edu void setIssued() { status.set(Issued); } 6691060SN/A 6701060SN/A /** Returns whether or not this instruction has issued. */ 6712731Sktlim@umich.edu bool isIssued() const { return status[Issued]; } 6721060SN/A 6734032Sktlim@umich.edu /** Clears this instruction as being issued. */ 6744032Sktlim@umich.edu void clearIssued() { status.reset(Issued); } 6754032Sktlim@umich.edu 6761060SN/A /** Sets this instruction as executed. */ 6772731Sktlim@umich.edu void setExecuted() { status.set(Executed); } 6781060SN/A 6791060SN/A /** Returns whether or not this instruction has executed. */ 6802731Sktlim@umich.edu bool isExecuted() const { return status[Executed]; } 6811060SN/A 6821060SN/A /** Sets this instruction as ready to commit. */ 6832731Sktlim@umich.edu void setCanCommit() { status.set(CanCommit); } 6841060SN/A 6851061SN/A /** Clears this instruction as being ready to commit. */ 6862731Sktlim@umich.edu void clearCanCommit() { status.reset(CanCommit); } 6871061SN/A 6881060SN/A /** Returns whether or not this instruction is ready to commit. */ 6892731Sktlim@umich.edu bool readyToCommit() const { return status[CanCommit]; } 6902731Sktlim@umich.edu 6912731Sktlim@umich.edu void setAtCommit() { status.set(AtCommit); } 6922731Sktlim@umich.edu 6932731Sktlim@umich.edu bool isAtCommit() { return status[AtCommit]; } 6941060SN/A 6952292SN/A /** Sets this instruction as committed. */ 6962731Sktlim@umich.edu void setCommitted() { status.set(Committed); } 6972292SN/A 6982292SN/A /** Returns whether or not this instruction is committed. */ 6992731Sktlim@umich.edu bool isCommitted() const { return status[Committed]; } 7002292SN/A 7011060SN/A /** Sets this instruction as squashed. */ 7022731Sktlim@umich.edu void setSquashed() { status.set(Squashed); } 7031060SN/A 7041060SN/A /** Returns whether or not this instruction is squashed. */ 7052731Sktlim@umich.edu bool isSquashed() const { return status[Squashed]; } 7061060SN/A 7072292SN/A //Instruction Queue Entry 7082292SN/A //----------------------- 7092292SN/A /** Sets this instruction as a entry the IQ. */ 7102731Sktlim@umich.edu void setInIQ() { status.set(IqEntry); } 7112292SN/A 7122292SN/A /** Sets this instruction as a entry the IQ. */ 7132731Sktlim@umich.edu void clearInIQ() { status.reset(IqEntry); } 7142731Sktlim@umich.edu 7152731Sktlim@umich.edu /** Returns whether or not this instruction has issued. */ 7162731Sktlim@umich.edu bool isInIQ() const { return status[IqEntry]; } 7172292SN/A 7181060SN/A /** Sets this instruction as squashed in the IQ. */ 7192731Sktlim@umich.edu void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 7201060SN/A 7211060SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 7222731Sktlim@umich.edu bool isSquashedInIQ() const { return status[SquashedInIQ]; } 7232292SN/A 7242292SN/A 7252292SN/A //Load / Store Queue Functions 7262292SN/A //----------------------- 7272292SN/A /** Sets this instruction as a entry the LSQ. */ 7282731Sktlim@umich.edu void setInLSQ() { status.set(LsqEntry); } 7292292SN/A 7302292SN/A /** Sets this instruction as a entry the LSQ. */ 7312731Sktlim@umich.edu void removeInLSQ() { status.reset(LsqEntry); } 7322731Sktlim@umich.edu 7332731Sktlim@umich.edu /** Returns whether or not this instruction is in the LSQ. */ 7342731Sktlim@umich.edu bool isInLSQ() const { return status[LsqEntry]; } 7352292SN/A 7362292SN/A /** Sets this instruction as squashed in the LSQ. */ 7372731Sktlim@umich.edu void setSquashedInLSQ() { status.set(SquashedInLSQ);} 7382292SN/A 7392292SN/A /** Returns whether or not this instruction is squashed in the LSQ. */ 7402731Sktlim@umich.edu bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 7412292SN/A 7422292SN/A 7432292SN/A //Reorder Buffer Functions 7442292SN/A //----------------------- 7452292SN/A /** Sets this instruction as a entry the ROB. */ 7462731Sktlim@umich.edu void setInROB() { status.set(RobEntry); } 7472292SN/A 7482292SN/A /** Sets this instruction as a entry the ROB. */ 7492731Sktlim@umich.edu void clearInROB() { status.reset(RobEntry); } 7502731Sktlim@umich.edu 7512731Sktlim@umich.edu /** Returns whether or not this instruction is in the ROB. */ 7522731Sktlim@umich.edu bool isInROB() const { return status[RobEntry]; } 7532292SN/A 7542292SN/A /** Sets this instruction as squashed in the ROB. */ 7552731Sktlim@umich.edu void setSquashedInROB() { status.set(SquashedInROB); } 7562292SN/A 7572292SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 7582731Sktlim@umich.edu bool isSquashedInROB() const { return status[SquashedInROB]; } 7592292SN/A 7607720Sgblack@eecs.umich.edu /** Read the PC state of this instruction. */ 7617720Sgblack@eecs.umich.edu const TheISA::PCState pcState() const { return pc; } 7627720Sgblack@eecs.umich.edu 7637720Sgblack@eecs.umich.edu /** Set the PC state of this instruction. */ 7647720Sgblack@eecs.umich.edu const void pcState(const TheISA::PCState &val) { pc = val; } 7657720Sgblack@eecs.umich.edu 7661060SN/A /** Read the PC of this instruction. */ 7677720Sgblack@eecs.umich.edu const Addr instAddr() const { return pc.instAddr(); } 7687720Sgblack@eecs.umich.edu 7697720Sgblack@eecs.umich.edu /** Read the PC of the next instruction. */ 7707720Sgblack@eecs.umich.edu const Addr nextInstAddr() const { return pc.nextInstAddr(); } 7711060SN/A 7724636Sgblack@eecs.umich.edu /**Read the micro PC of this instruction. */ 7737720Sgblack@eecs.umich.edu const Addr microPC() const { return pc.microPC(); } 7744636Sgblack@eecs.umich.edu 7757597Sminkyu.jeong@arm.com bool readPredicate() 7767597Sminkyu.jeong@arm.com { 7777597Sminkyu.jeong@arm.com return predicate; 7787597Sminkyu.jeong@arm.com } 7797597Sminkyu.jeong@arm.com 7807597Sminkyu.jeong@arm.com void setPredicate(bool val) 7817597Sminkyu.jeong@arm.com { 7827597Sminkyu.jeong@arm.com predicate = val; 7837600Sminkyu.jeong@arm.com 7847600Sminkyu.jeong@arm.com if (traceData) { 7857600Sminkyu.jeong@arm.com traceData->setPredicate(val); 7867600Sminkyu.jeong@arm.com } 7877597Sminkyu.jeong@arm.com } 7887597Sminkyu.jeong@arm.com 7892702Sktlim@umich.edu /** Sets the ASID. */ 7902292SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 7912292SN/A 7922702Sktlim@umich.edu /** Sets the thread id. */ 7936221Snate@binkert.org void setTid(ThreadID tid) { threadNumber = tid; } 7942292SN/A 7952731Sktlim@umich.edu /** Sets the pointer to the thread state. */ 7962702Sktlim@umich.edu void setThreadState(ImplState *state) { thread = state; } 7971060SN/A 7982731Sktlim@umich.edu /** Returns the thread context. */ 7992680Sktlim@umich.edu ThreadContext *tcBase() { return thread->getTC(); } 8001464SN/A 8011464SN/A private: 8021684SN/A /** Instruction effective address. 8031684SN/A * @todo: Consider if this is necessary or not. 8041684SN/A */ 8051464SN/A Addr instEffAddr; 8062292SN/A 8071684SN/A /** Whether or not the effective address calculation is completed. 8081684SN/A * @todo: Consider if this is necessary or not. 8091684SN/A */ 8101464SN/A bool eaCalcDone; 8111464SN/A 8124032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 8134032Sktlim@umich.edu bool isUncacheable; 8144032Sktlim@umich.edu 8154032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8164032Sktlim@umich.edu bool reqMade; 8174032Sktlim@umich.edu 8181464SN/A public: 8191684SN/A /** Sets the effective address. */ 8201464SN/A void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 8211684SN/A 8221684SN/A /** Returns the effective address. */ 8231464SN/A const Addr &getEA() const { return instEffAddr; } 8241684SN/A 8251684SN/A /** Returns whether or not the eff. addr. calculation has been completed. */ 8261464SN/A bool doneEACalc() { return eaCalcDone; } 8271684SN/A 8281684SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 8291464SN/A bool eaSrcsReady(); 8301681SN/A 8312292SN/A /** Whether or not the memory operation is done. */ 8322292SN/A bool memOpDone; 8332292SN/A 8344032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 8354032Sktlim@umich.edu bool uncacheable() { return isUncacheable; } 8364032Sktlim@umich.edu 8374032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8384032Sktlim@umich.edu bool hasRequest() { return reqMade; } 8394032Sktlim@umich.edu 8401681SN/A public: 8411684SN/A /** Load queue index. */ 8421681SN/A int16_t lqIdx; 8431684SN/A 8441684SN/A /** Store queue index. */ 8451681SN/A int16_t sqIdx; 8462292SN/A 8472292SN/A /** Iterator pointing to this BaseDynInst in the list of all insts. */ 8482292SN/A ListIt instListIt; 8492292SN/A 8502292SN/A /** Returns iterator to this instruction in the list of all insts. */ 8512292SN/A ListIt &getInstListIt() { return instListIt; } 8522292SN/A 8532292SN/A /** Sets iterator for this instruction in the list of all insts. */ 8542292SN/A void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 8553326Sktlim@umich.edu 8563326Sktlim@umich.edu public: 8573326Sktlim@umich.edu /** Returns the number of consecutive store conditional failures. */ 8583326Sktlim@umich.edu unsigned readStCondFailures() 8593326Sktlim@umich.edu { return thread->storeCondFailures; } 8603326Sktlim@umich.edu 8613326Sktlim@umich.edu /** Sets the number of consecutive store conditional failures. */ 8623326Sktlim@umich.edu void setStCondFailures(unsigned sc_failures) 8633326Sktlim@umich.edu { thread->storeCondFailures = sc_failures; } 8641060SN/A}; 8651060SN/A 8661060SN/Atemplate<class Impl> 8677520Sgblack@eecs.umich.eduFault 8688444Sgblack@eecs.umich.eduBaseDynInst<Impl>::readMem(Addr addr, uint8_t *data, 8698444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 8701060SN/A{ 8714032Sktlim@umich.edu reqMade = true; 8727944SGiacomo.Gabrielli@arm.com Request *req = NULL; 8736974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 8746974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 8756974Stjones1@inf.ed.ac.uk 8767944SGiacomo.Gabrielli@arm.com if (reqMade && translationStarted) { 8777944SGiacomo.Gabrielli@arm.com req = savedReq; 8787944SGiacomo.Gabrielli@arm.com sreqLow = savedSreqLow; 8797944SGiacomo.Gabrielli@arm.com sreqHigh = savedSreqHigh; 8807944SGiacomo.Gabrielli@arm.com } else { 8818832SAli.Saidi@ARM.com req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), 8827944SGiacomo.Gabrielli@arm.com thread->contextId(), threadNumber); 8834032Sktlim@umich.edu 8847944SGiacomo.Gabrielli@arm.com // Only split the request if the ISA supports unaligned accesses. 8857944SGiacomo.Gabrielli@arm.com if (TheISA::HasUnalignedMemAcc) { 8867944SGiacomo.Gabrielli@arm.com splitRequest(req, sreqLow, sreqHigh); 8877944SGiacomo.Gabrielli@arm.com } 8887944SGiacomo.Gabrielli@arm.com initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 8891060SN/A } 8901060SN/A 8917944SGiacomo.Gabrielli@arm.com if (translationCompleted) { 8927944SGiacomo.Gabrielli@arm.com if (fault == NoFault) { 8937944SGiacomo.Gabrielli@arm.com effAddr = req->getVaddr(); 8948199SAli.Saidi@ARM.com effSize = size; 8957944SGiacomo.Gabrielli@arm.com effAddrValid = true; 8968887Sgeoffrey.blake@arm.com 8978887Sgeoffrey.blake@arm.com if (cpu->checker) { 8988887Sgeoffrey.blake@arm.com if (reqToVerify != NULL) { 8998887Sgeoffrey.blake@arm.com delete reqToVerify; 9008887Sgeoffrey.blake@arm.com } 9018887Sgeoffrey.blake@arm.com reqToVerify = new Request(*req); 9028733Sgeoffrey.blake@arm.com } 9037944SGiacomo.Gabrielli@arm.com fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); 9047944SGiacomo.Gabrielli@arm.com } else { 9057944SGiacomo.Gabrielli@arm.com // Commit will have to clean up whatever happened. Set this 9067944SGiacomo.Gabrielli@arm.com // instruction as executed. 9077944SGiacomo.Gabrielli@arm.com this->setExecuted(); 9087944SGiacomo.Gabrielli@arm.com } 9097944SGiacomo.Gabrielli@arm.com 9107944SGiacomo.Gabrielli@arm.com if (fault != NoFault) { 9117944SGiacomo.Gabrielli@arm.com // Return a fixed value to keep simulation deterministic even 9127944SGiacomo.Gabrielli@arm.com // along misspeculated paths. 9137944SGiacomo.Gabrielli@arm.com if (data) 9147944SGiacomo.Gabrielli@arm.com bzero(data, size); 9157944SGiacomo.Gabrielli@arm.com } 9167577SAli.Saidi@ARM.com } 9177577SAli.Saidi@ARM.com 9181060SN/A if (traceData) { 9191060SN/A traceData->setAddr(addr); 9201060SN/A } 9211060SN/A 9221060SN/A return fault; 9231060SN/A} 9241060SN/A 9251060SN/Atemplate<class Impl> 9267520Sgblack@eecs.umich.eduFault 9278444Sgblack@eecs.umich.eduBaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, 9288444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 9291060SN/A{ 9301060SN/A if (traceData) { 9311060SN/A traceData->setAddr(addr); 9321060SN/A } 9331060SN/A 9344032Sktlim@umich.edu reqMade = true; 9357944SGiacomo.Gabrielli@arm.com Request *req = NULL; 9366974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 9376974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 9386974Stjones1@inf.ed.ac.uk 9397944SGiacomo.Gabrielli@arm.com if (reqMade && translationStarted) { 9407944SGiacomo.Gabrielli@arm.com req = savedReq; 9417944SGiacomo.Gabrielli@arm.com sreqLow = savedSreqLow; 9427944SGiacomo.Gabrielli@arm.com sreqHigh = savedSreqHigh; 9437944SGiacomo.Gabrielli@arm.com } else { 9448832SAli.Saidi@ARM.com req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), 9457944SGiacomo.Gabrielli@arm.com thread->contextId(), threadNumber); 9467944SGiacomo.Gabrielli@arm.com 9477944SGiacomo.Gabrielli@arm.com // Only split the request if the ISA supports unaligned accesses. 9487944SGiacomo.Gabrielli@arm.com if (TheISA::HasUnalignedMemAcc) { 9497944SGiacomo.Gabrielli@arm.com splitRequest(req, sreqLow, sreqHigh); 9507944SGiacomo.Gabrielli@arm.com } 9517944SGiacomo.Gabrielli@arm.com initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 9526974Stjones1@inf.ed.ac.uk } 9534032Sktlim@umich.edu 9547944SGiacomo.Gabrielli@arm.com if (fault == NoFault && translationCompleted) { 9552678Sktlim@umich.edu effAddr = req->getVaddr(); 9568199SAli.Saidi@ARM.com effSize = size; 9574032Sktlim@umich.edu effAddrValid = true; 9588887Sgeoffrey.blake@arm.com 9598887Sgeoffrey.blake@arm.com if (cpu->checker) { 9608887Sgeoffrey.blake@arm.com if (reqToVerify != NULL) { 9618887Sgeoffrey.blake@arm.com delete reqToVerify; 9628887Sgeoffrey.blake@arm.com } 9638887Sgeoffrey.blake@arm.com reqToVerify = new Request(*req); 9648733Sgeoffrey.blake@arm.com } 9656975Stjones1@inf.ed.ac.uk fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 9661060SN/A } 9671060SN/A 9681060SN/A return fault; 9691060SN/A} 9701060SN/A 9716973Stjones1@inf.ed.ac.uktemplate<class Impl> 9726973Stjones1@inf.ed.ac.ukinline void 9736974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 9746974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh) 9756974Stjones1@inf.ed.ac.uk{ 9766974Stjones1@inf.ed.ac.uk // Check to see if the request crosses the next level block boundary. 9778850Sandreas.hansson@arm.com unsigned block_size = cpu->getDataPort().peerBlockSize(); 9786974Stjones1@inf.ed.ac.uk Addr addr = req->getVaddr(); 9796974Stjones1@inf.ed.ac.uk Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 9806974Stjones1@inf.ed.ac.uk assert(split_addr <= addr || split_addr - addr < block_size); 9816974Stjones1@inf.ed.ac.uk 9826974Stjones1@inf.ed.ac.uk // Spans two blocks. 9836974Stjones1@inf.ed.ac.uk if (split_addr > addr) { 9846974Stjones1@inf.ed.ac.uk req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 9856974Stjones1@inf.ed.ac.uk } 9866974Stjones1@inf.ed.ac.uk} 9876974Stjones1@inf.ed.ac.uk 9886974Stjones1@inf.ed.ac.uktemplate<class Impl> 9896974Stjones1@inf.ed.ac.ukinline void 9906974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 9916974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 9926973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode) 9936973Stjones1@inf.ed.ac.uk{ 9947944SGiacomo.Gabrielli@arm.com translationStarted = true; 9957944SGiacomo.Gabrielli@arm.com 9966974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 9976974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 9986974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, NULL, res, mode); 9996974Stjones1@inf.ed.ac.uk 10006974Stjones1@inf.ed.ac.uk // One translation if the request isn't split. 10018486Sgblack@eecs.umich.edu DataTranslation<BaseDynInstPtr> *trans = 10028486Sgblack@eecs.umich.edu new DataTranslation<BaseDynInstPtr>(this, state); 10036974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 10047944SGiacomo.Gabrielli@arm.com if (!translationCompleted) { 10057944SGiacomo.Gabrielli@arm.com // Save memory requests. 10067944SGiacomo.Gabrielli@arm.com savedReq = state->mainReq; 10077944SGiacomo.Gabrielli@arm.com savedSreqLow = state->sreqLow; 10087944SGiacomo.Gabrielli@arm.com savedSreqHigh = state->sreqHigh; 10097944SGiacomo.Gabrielli@arm.com } 10106974Stjones1@inf.ed.ac.uk } else { 10116974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 10126974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 10136974Stjones1@inf.ed.ac.uk 10146974Stjones1@inf.ed.ac.uk // Two translations when the request is split. 10158486Sgblack@eecs.umich.edu DataTranslation<BaseDynInstPtr> *stransLow = 10168486Sgblack@eecs.umich.edu new DataTranslation<BaseDynInstPtr>(this, state, 0); 10178486Sgblack@eecs.umich.edu DataTranslation<BaseDynInstPtr> *stransHigh = 10188486Sgblack@eecs.umich.edu new DataTranslation<BaseDynInstPtr>(this, state, 1); 10196974Stjones1@inf.ed.ac.uk 10206974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 10216974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 10227944SGiacomo.Gabrielli@arm.com if (!translationCompleted) { 10237944SGiacomo.Gabrielli@arm.com // Save memory requests. 10247944SGiacomo.Gabrielli@arm.com savedReq = state->mainReq; 10257944SGiacomo.Gabrielli@arm.com savedSreqLow = state->sreqLow; 10267944SGiacomo.Gabrielli@arm.com savedSreqHigh = state->sreqHigh; 10277944SGiacomo.Gabrielli@arm.com } 10286974Stjones1@inf.ed.ac.uk } 10296973Stjones1@inf.ed.ac.uk} 10306973Stjones1@inf.ed.ac.uk 10316973Stjones1@inf.ed.ac.uktemplate<class Impl> 10326973Stjones1@inf.ed.ac.ukinline void 10336973Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 10346973Stjones1@inf.ed.ac.uk{ 10356973Stjones1@inf.ed.ac.uk fault = state->getFault(); 10366973Stjones1@inf.ed.ac.uk 10376973Stjones1@inf.ed.ac.uk if (state->isUncacheable()) 10386973Stjones1@inf.ed.ac.uk isUncacheable = true; 10396973Stjones1@inf.ed.ac.uk 10406973Stjones1@inf.ed.ac.uk if (fault == NoFault) { 10416973Stjones1@inf.ed.ac.uk physEffAddr = state->getPaddr(); 10426973Stjones1@inf.ed.ac.uk memReqFlags = state->getFlags(); 10436973Stjones1@inf.ed.ac.uk 10446973Stjones1@inf.ed.ac.uk if (state->mainReq->isCondSwap()) { 10456973Stjones1@inf.ed.ac.uk assert(state->res); 10466973Stjones1@inf.ed.ac.uk state->mainReq->setExtraData(*state->res); 10476973Stjones1@inf.ed.ac.uk } 10486973Stjones1@inf.ed.ac.uk 10496973Stjones1@inf.ed.ac.uk } else { 10506973Stjones1@inf.ed.ac.uk state->deleteReqs(); 10516973Stjones1@inf.ed.ac.uk } 10526973Stjones1@inf.ed.ac.uk delete state; 10537944SGiacomo.Gabrielli@arm.com 10547944SGiacomo.Gabrielli@arm.com translationCompleted = true; 10556973Stjones1@inf.ed.ac.uk} 10566973Stjones1@inf.ed.ac.uk 10571464SN/A#endif // __CPU_BASE_DYN_INST_HH__ 1058