base_dyn_inst.hh revision 8199
11060SN/A/* 27944SGiacomo.Gabrielli@arm.com * Copyright (c) 2011 ARM Limited 37944SGiacomo.Gabrielli@arm.com * All rights reserved. 47944SGiacomo.Gabrielli@arm.com * 57944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137944SGiacomo.Gabrielli@arm.com * 142702Sktlim@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 156973Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The University of Edinburgh 161060SN/A * All rights reserved. 171060SN/A * 181060SN/A * Redistribution and use in source and binary forms, with or without 191060SN/A * modification, are permitted provided that the following conditions are 201060SN/A * met: redistributions of source code must retain the above copyright 211060SN/A * notice, this list of conditions and the following disclaimer; 221060SN/A * redistributions in binary form must reproduce the above copyright 231060SN/A * notice, this list of conditions and the following disclaimer in the 241060SN/A * documentation and/or other materials provided with the distribution; 251060SN/A * neither the name of the copyright holders nor the names of its 261060SN/A * contributors may be used to endorse or promote products derived from 271060SN/A * this software without specific prior written permission. 281060SN/A * 291060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 426973Stjones1@inf.ed.ac.uk * Timothy M. Jones 431060SN/A */ 441060SN/A 451464SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 461464SN/A#define __CPU_BASE_DYN_INST_HH__ 471060SN/A 482731Sktlim@umich.edu#include <bitset> 492292SN/A#include <list> 501464SN/A#include <string> 511060SN/A 522669Sktlim@umich.edu#include "arch/faults.hh" 537720Sgblack@eecs.umich.edu#include "arch/utility.hh" 541060SN/A#include "base/fast_alloc.hh" 551060SN/A#include "base/trace.hh" 561858SN/A#include "config/full_system.hh" 576658Snate@binkert.org#include "config/the_isa.hh" 583770Sgblack@eecs.umich.edu#include "cpu/o3/comm.hh" 591464SN/A#include "cpu/exetrace.hh" 601464SN/A#include "cpu/inst_seq.hh" 612669Sktlim@umich.edu#include "cpu/op_class.hh" 621060SN/A#include "cpu/static_inst.hh" 636973Stjones1@inf.ed.ac.uk#include "cpu/translation.hh" 642669Sktlim@umich.edu#include "mem/packet.hh" 657678Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 662292SN/A#include "sim/system.hh" 676023Snate@binkert.org#include "sim/tlb.hh" 681060SN/A 691060SN/A/** 701060SN/A * @file 711060SN/A * Defines a dynamic instruction context. 721060SN/A */ 731060SN/A 741061SN/A// Forward declaration. 751061SN/Aclass StaticInstPtr; 761060SN/A 771060SN/Atemplate <class Impl> 781061SN/Aclass BaseDynInst : public FastAlloc, public RefCounted 791060SN/A{ 801060SN/A public: 811060SN/A // Typedef for the CPU. 822733Sktlim@umich.edu typedef typename Impl::CPUType ImplCPU; 832733Sktlim@umich.edu typedef typename ImplCPU::ImplState ImplState; 841060SN/A 852292SN/A // Logical register index type. 862107SN/A typedef TheISA::RegIndex RegIndex; 872690Sktlim@umich.edu // Integer register type. 882107SN/A typedef TheISA::IntReg IntReg; 892690Sktlim@umich.edu // Floating point register type. 902690Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 911060SN/A 922292SN/A // The DynInstPtr type. 932292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 942292SN/A 952292SN/A // The list of instructions iterator type. 962292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 972292SN/A 981060SN/A enum { 995543Ssaidi@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 1005543Ssaidi@eecs.umich.edu MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 1011060SN/A }; 1021060SN/A 1032292SN/A /** The StaticInst used by this BaseDynInst. */ 1042107SN/A StaticInstPtr staticInst; 1051060SN/A 1061060SN/A //////////////////////////////////////////// 1071060SN/A // 1081060SN/A // INSTRUCTION EXECUTION 1091060SN/A // 1101060SN/A //////////////////////////////////////////// 1112292SN/A /** InstRecord that tracks this instructions. */ 1121060SN/A Trace::InstRecord *traceData; 1131060SN/A 1145358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1155358Sgblack@eecs.umich.edu { 1165358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1175358Sgblack@eecs.umich.edu } 1185358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1195358Sgblack@eecs.umich.edu { 1205358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1215358Sgblack@eecs.umich.edu } 1225358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1235358Sgblack@eecs.umich.edu { 1245358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1255358Sgblack@eecs.umich.edu } 1265358Sgblack@eecs.umich.edu 1272292SN/A /** 1282292SN/A * Does a read to a given address. 1292292SN/A * @param addr The address to read. 1302292SN/A * @param data The read's data is written into this parameter. 1312292SN/A * @param flags The request's flags. 1322292SN/A * @return Returns any fault due to the read. 1332292SN/A */ 1341060SN/A template <class T> 1352132SN/A Fault read(Addr addr, T &data, unsigned flags); 1361060SN/A 1377520Sgblack@eecs.umich.edu Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags); 1387520Sgblack@eecs.umich.edu 1392292SN/A /** 1402292SN/A * Does a write to a given address. 1412292SN/A * @param data The data to be written. 1422292SN/A * @param addr The address to write to. 1432292SN/A * @param flags The request's flags. 1442292SN/A * @param res The result of the write (for load locked/store conditionals). 1452292SN/A * @return Returns any fault due to the write. 1462292SN/A */ 1471060SN/A template <class T> 1486973Stjones1@inf.ed.ac.uk Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1496973Stjones1@inf.ed.ac.uk 1507520Sgblack@eecs.umich.edu Fault writeBytes(uint8_t *data, unsigned size, 1517520Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res); 1527520Sgblack@eecs.umich.edu 1536974Stjones1@inf.ed.ac.uk /** Splits a request in two if it crosses a dcache block. */ 1546974Stjones1@inf.ed.ac.uk void splitRequest(RequestPtr req, RequestPtr &sreqLow, 1556974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh); 1566974Stjones1@inf.ed.ac.uk 1576973Stjones1@inf.ed.ac.uk /** Initiate a DTB address translation. */ 1586974Stjones1@inf.ed.ac.uk void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 1596974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 1606973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode); 1616973Stjones1@inf.ed.ac.uk 1626973Stjones1@inf.ed.ac.uk /** Finish a DTB address translation. */ 1636973Stjones1@inf.ed.ac.uk void finishTranslation(WholeTranslationState *state); 1641060SN/A 1657944SGiacomo.Gabrielli@arm.com /** True if the DTB address translation has started. */ 1667944SGiacomo.Gabrielli@arm.com bool translationStarted; 1677944SGiacomo.Gabrielli@arm.com 1687944SGiacomo.Gabrielli@arm.com /** True if the DTB address translation has completed. */ 1697944SGiacomo.Gabrielli@arm.com bool translationCompleted; 1707944SGiacomo.Gabrielli@arm.com 1717944SGiacomo.Gabrielli@arm.com /** 1727944SGiacomo.Gabrielli@arm.com * Returns true if the DTB address translation is being delayed due to a hw 1737944SGiacomo.Gabrielli@arm.com * page table walk. 1747944SGiacomo.Gabrielli@arm.com */ 1757944SGiacomo.Gabrielli@arm.com bool isTranslationDelayed() const 1767944SGiacomo.Gabrielli@arm.com { 1777944SGiacomo.Gabrielli@arm.com return (translationStarted && !translationCompleted); 1787944SGiacomo.Gabrielli@arm.com } 1797944SGiacomo.Gabrielli@arm.com 1807944SGiacomo.Gabrielli@arm.com /** 1817944SGiacomo.Gabrielli@arm.com * Saved memory requests (needed when the DTB address translation is 1827944SGiacomo.Gabrielli@arm.com * delayed due to a hw page table walk). 1837944SGiacomo.Gabrielli@arm.com */ 1847944SGiacomo.Gabrielli@arm.com RequestPtr savedReq; 1857944SGiacomo.Gabrielli@arm.com RequestPtr savedSreqLow; 1867944SGiacomo.Gabrielli@arm.com RequestPtr savedSreqHigh; 1877944SGiacomo.Gabrielli@arm.com 1881684SN/A /** @todo: Consider making this private. */ 1891060SN/A public: 1901060SN/A /** The sequence number of the instruction. */ 1911060SN/A InstSeqNum seqNum; 1921060SN/A 1932731Sktlim@umich.edu enum Status { 1942731Sktlim@umich.edu IqEntry, /// Instruction is in the IQ 1952731Sktlim@umich.edu RobEntry, /// Instruction is in the ROB 1962731Sktlim@umich.edu LsqEntry, /// Instruction is in the LSQ 1972731Sktlim@umich.edu Completed, /// Instruction has completed 1982731Sktlim@umich.edu ResultReady, /// Instruction has its result 1992731Sktlim@umich.edu CanIssue, /// Instruction can issue and execute 2002731Sktlim@umich.edu Issued, /// Instruction has issued 2012731Sktlim@umich.edu Executed, /// Instruction has executed 2022731Sktlim@umich.edu CanCommit, /// Instruction can commit 2032731Sktlim@umich.edu AtCommit, /// Instruction has reached commit 2042731Sktlim@umich.edu Committed, /// Instruction has committed 2052731Sktlim@umich.edu Squashed, /// Instruction is squashed 2062731Sktlim@umich.edu SquashedInIQ, /// Instruction is squashed in the IQ 2072731Sktlim@umich.edu SquashedInLSQ, /// Instruction is squashed in the LSQ 2082731Sktlim@umich.edu SquashedInROB, /// Instruction is squashed in the ROB 2092731Sktlim@umich.edu RecoverInst, /// Is a recover instruction 2102731Sktlim@umich.edu BlockingInst, /// Is a blocking instruction 2112731Sktlim@umich.edu ThreadsyncWait, /// Is a thread synchronization instruction 2122731Sktlim@umich.edu SerializeBefore, /// Needs to serialize on 2132731Sktlim@umich.edu /// instructions ahead of it 2142731Sktlim@umich.edu SerializeAfter, /// Needs to serialize instructions behind it 2152731Sktlim@umich.edu SerializeHandled, /// Serialization has been handled 2162731Sktlim@umich.edu NumStatus 2172731Sktlim@umich.edu }; 2182292SN/A 2192731Sktlim@umich.edu /** The status of this BaseDynInst. Several bits can be set. */ 2202731Sktlim@umich.edu std::bitset<NumStatus> status; 2211060SN/A 2221060SN/A /** The thread this instruction is from. */ 2236221Snate@binkert.org ThreadID threadNumber; 2241060SN/A 2251060SN/A /** data address space ID, for loads & stores. */ 2261060SN/A short asid; 2271060SN/A 2282292SN/A /** How many source registers are ready. */ 2292292SN/A unsigned readyRegs; 2302292SN/A 2312733Sktlim@umich.edu /** Pointer to the Impl's CPU object. */ 2322733Sktlim@umich.edu ImplCPU *cpu; 2331060SN/A 2342680Sktlim@umich.edu /** Pointer to the thread state. */ 2352292SN/A ImplState *thread; 2361060SN/A 2371060SN/A /** The kind of fault this instruction has generated. */ 2382132SN/A Fault fault; 2391060SN/A 2402702Sktlim@umich.edu /** Pointer to the data for the memory access. */ 2412669Sktlim@umich.edu uint8_t *memData; 2422292SN/A 2431060SN/A /** The effective virtual address (lds & stores only). */ 2441060SN/A Addr effAddr; 2451060SN/A 2468199SAli.Saidi@ARM.com /** The size of the request */ 2478199SAli.Saidi@ARM.com Addr effSize; 2488199SAli.Saidi@ARM.com 2494032Sktlim@umich.edu /** Is the effective virtual address valid. */ 2504032Sktlim@umich.edu bool effAddrValid; 2514032Sktlim@umich.edu 2521060SN/A /** The effective physical address. */ 2531060SN/A Addr physEffAddr; 2541060SN/A 2551060SN/A /** Effective virtual address for a copy source. */ 2561060SN/A Addr copySrcEffAddr; 2571060SN/A 2581060SN/A /** Effective physical address for a copy source. */ 2591060SN/A Addr copySrcPhysEffAddr; 2601060SN/A 2611060SN/A /** The memory request flags (from translation). */ 2621060SN/A unsigned memReqFlags; 2631060SN/A 2641464SN/A union Result { 2651464SN/A uint64_t integer; 2662356SN/A// float fp; 2671464SN/A double dbl; 2681464SN/A }; 2691060SN/A 2701464SN/A /** The result of the instruction; assumes for now that there's only one 2711464SN/A * destination register. 2721464SN/A */ 2731464SN/A Result instResult; 2741060SN/A 2753326Sktlim@umich.edu /** Records changes to result? */ 2763326Sktlim@umich.edu bool recordResult; 2773326Sktlim@umich.edu 2787597Sminkyu.jeong@arm.com /** Did this instruction execute, or is it predicated false */ 2797597Sminkyu.jeong@arm.com bool predicate; 2807597Sminkyu.jeong@arm.com 2813965Sgblack@eecs.umich.edu protected: 2827720Sgblack@eecs.umich.edu /** PC state for this instruction. */ 2837720Sgblack@eecs.umich.edu TheISA::PCState pc; 2841060SN/A 2857720Sgblack@eecs.umich.edu /** Predicted PC state after this instruction. */ 2867720Sgblack@eecs.umich.edu TheISA::PCState predPC; 2874636Sgblack@eecs.umich.edu 2883794Sgblack@eecs.umich.edu /** If this is a branch that was predicted taken */ 2893794Sgblack@eecs.umich.edu bool predTaken; 2903794Sgblack@eecs.umich.edu 2913965Sgblack@eecs.umich.edu public: 2923965Sgblack@eecs.umich.edu 2932292SN/A#ifdef DEBUG 2942292SN/A void dumpSNList(); 2952292SN/A#endif 2962292SN/A 2972292SN/A /** Whether or not the source register is ready. 2982292SN/A * @todo: Not sure this should be here vs the derived class. 2991060SN/A */ 3001060SN/A bool _readySrcRegIdx[MaxInstSrcRegs]; 3011060SN/A 3023770Sgblack@eecs.umich.edu protected: 3033770Sgblack@eecs.umich.edu /** Flattened register index of the destination registers of this 3043770Sgblack@eecs.umich.edu * instruction. 3053770Sgblack@eecs.umich.edu */ 3063770Sgblack@eecs.umich.edu TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 3073770Sgblack@eecs.umich.edu 3083770Sgblack@eecs.umich.edu /** Flattened register index of the source registers of this 3093770Sgblack@eecs.umich.edu * instruction. 3103770Sgblack@eecs.umich.edu */ 3113770Sgblack@eecs.umich.edu TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 3123770Sgblack@eecs.umich.edu 3133770Sgblack@eecs.umich.edu /** Physical register index of the destination registers of this 3143770Sgblack@eecs.umich.edu * instruction. 3153770Sgblack@eecs.umich.edu */ 3163770Sgblack@eecs.umich.edu PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 3173770Sgblack@eecs.umich.edu 3183770Sgblack@eecs.umich.edu /** Physical register index of the source registers of this 3193770Sgblack@eecs.umich.edu * instruction. 3203770Sgblack@eecs.umich.edu */ 3213770Sgblack@eecs.umich.edu PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 3223770Sgblack@eecs.umich.edu 3233770Sgblack@eecs.umich.edu /** Physical register index of the previous producers of the 3243770Sgblack@eecs.umich.edu * architected destinations. 3253770Sgblack@eecs.umich.edu */ 3263770Sgblack@eecs.umich.edu PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 3273770Sgblack@eecs.umich.edu 3281060SN/A public: 3293770Sgblack@eecs.umich.edu 3303770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th destination 3313770Sgblack@eecs.umich.edu * register. 3323770Sgblack@eecs.umich.edu */ 3333770Sgblack@eecs.umich.edu PhysRegIndex renamedDestRegIdx(int idx) const 3343770Sgblack@eecs.umich.edu { 3353770Sgblack@eecs.umich.edu return _destRegIdx[idx]; 3363770Sgblack@eecs.umich.edu } 3373770Sgblack@eecs.umich.edu 3383770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th source register. */ 3393770Sgblack@eecs.umich.edu PhysRegIndex renamedSrcRegIdx(int idx) const 3403770Sgblack@eecs.umich.edu { 3413770Sgblack@eecs.umich.edu return _srcRegIdx[idx]; 3423770Sgblack@eecs.umich.edu } 3433770Sgblack@eecs.umich.edu 3443770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th destination 3453770Sgblack@eecs.umich.edu * register. 3463770Sgblack@eecs.umich.edu */ 3473770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedDestRegIdx(int idx) const 3483770Sgblack@eecs.umich.edu { 3493770Sgblack@eecs.umich.edu return _flatDestRegIdx[idx]; 3503770Sgblack@eecs.umich.edu } 3513770Sgblack@eecs.umich.edu 3523770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th source register */ 3533770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedSrcRegIdx(int idx) const 3543770Sgblack@eecs.umich.edu { 3553770Sgblack@eecs.umich.edu return _flatSrcRegIdx[idx]; 3563770Sgblack@eecs.umich.edu } 3573770Sgblack@eecs.umich.edu 3583770Sgblack@eecs.umich.edu /** Returns the physical register index of the previous physical register 3593770Sgblack@eecs.umich.edu * that remapped to the same logical register index. 3603770Sgblack@eecs.umich.edu */ 3613770Sgblack@eecs.umich.edu PhysRegIndex prevDestRegIdx(int idx) const 3623770Sgblack@eecs.umich.edu { 3633770Sgblack@eecs.umich.edu return _prevDestRegIdx[idx]; 3643770Sgblack@eecs.umich.edu } 3653770Sgblack@eecs.umich.edu 3663770Sgblack@eecs.umich.edu /** Renames a destination register to a physical register. Also records 3673770Sgblack@eecs.umich.edu * the previous physical register that the logical register mapped to. 3683770Sgblack@eecs.umich.edu */ 3693770Sgblack@eecs.umich.edu void renameDestReg(int idx, 3703770Sgblack@eecs.umich.edu PhysRegIndex renamed_dest, 3713770Sgblack@eecs.umich.edu PhysRegIndex previous_rename) 3723770Sgblack@eecs.umich.edu { 3733770Sgblack@eecs.umich.edu _destRegIdx[idx] = renamed_dest; 3743770Sgblack@eecs.umich.edu _prevDestRegIdx[idx] = previous_rename; 3753770Sgblack@eecs.umich.edu } 3763770Sgblack@eecs.umich.edu 3773770Sgblack@eecs.umich.edu /** Renames a source logical register to the physical register which 3783770Sgblack@eecs.umich.edu * has/will produce that logical register's result. 3793770Sgblack@eecs.umich.edu * @todo: add in whether or not the source register is ready. 3803770Sgblack@eecs.umich.edu */ 3813770Sgblack@eecs.umich.edu void renameSrcReg(int idx, PhysRegIndex renamed_src) 3823770Sgblack@eecs.umich.edu { 3833770Sgblack@eecs.umich.edu _srcRegIdx[idx] = renamed_src; 3843770Sgblack@eecs.umich.edu } 3853770Sgblack@eecs.umich.edu 3863770Sgblack@eecs.umich.edu /** Flattens a source architectural register index into a logical index. 3873770Sgblack@eecs.umich.edu */ 3883770Sgblack@eecs.umich.edu void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 3893770Sgblack@eecs.umich.edu { 3903770Sgblack@eecs.umich.edu _flatSrcRegIdx[idx] = flattened_src; 3913770Sgblack@eecs.umich.edu } 3923770Sgblack@eecs.umich.edu 3933770Sgblack@eecs.umich.edu /** Flattens a destination architectural register index into a logical 3943770Sgblack@eecs.umich.edu * index. 3953770Sgblack@eecs.umich.edu */ 3963770Sgblack@eecs.umich.edu void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 3973770Sgblack@eecs.umich.edu { 3983770Sgblack@eecs.umich.edu _flatDestRegIdx[idx] = flattened_dest; 3993770Sgblack@eecs.umich.edu } 4004636Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. 4014636Sgblack@eecs.umich.edu * @param staticInst A StaticInstPtr to the underlying instruction. 4027720Sgblack@eecs.umich.edu * @param pc The PC state for the instruction. 4037720Sgblack@eecs.umich.edu * @param predPC The predicted next PC state for the instruction. 4044636Sgblack@eecs.umich.edu * @param seq_num The sequence number of the instruction. 4054636Sgblack@eecs.umich.edu * @param cpu Pointer to the instruction's CPU. 4064636Sgblack@eecs.umich.edu */ 4077720Sgblack@eecs.umich.edu BaseDynInst(StaticInstPtr staticInst, TheISA::PCState pc, 4087720Sgblack@eecs.umich.edu TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu); 4093770Sgblack@eecs.umich.edu 4102292SN/A /** BaseDynInst constructor given a binary instruction. 4112292SN/A * @param inst The binary instruction. 4127720Sgblack@eecs.umich.edu * @param _pc The PC state for the instruction. 4137720Sgblack@eecs.umich.edu * @param _predPC The predicted next PC state for the instruction. 4142292SN/A * @param seq_num The sequence number of the instruction. 4152292SN/A * @param cpu Pointer to the instruction's CPU. 4162292SN/A */ 4177720Sgblack@eecs.umich.edu BaseDynInst(TheISA::ExtMachInst inst, TheISA::PCState pc, 4187720Sgblack@eecs.umich.edu TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu); 4191060SN/A 4202292SN/A /** BaseDynInst constructor given a StaticInst pointer. 4212292SN/A * @param _staticInst The StaticInst for this BaseDynInst. 4222292SN/A */ 4232107SN/A BaseDynInst(StaticInstPtr &_staticInst); 4241060SN/A 4251060SN/A /** BaseDynInst destructor. */ 4261060SN/A ~BaseDynInst(); 4271060SN/A 4281464SN/A private: 4291684SN/A /** Function to initialize variables in the constructors. */ 4301464SN/A void initVars(); 4311060SN/A 4321464SN/A public: 4331060SN/A /** Dumps out contents of this BaseDynInst. */ 4341060SN/A void dump(); 4351060SN/A 4361060SN/A /** Dumps out contents of this BaseDynInst into given string. */ 4371060SN/A void dump(std::string &outstring); 4381060SN/A 4393326Sktlim@umich.edu /** Read this CPU's ID. */ 4405712Shsul@eecs.umich.edu int cpuId() { return cpu->cpuId(); } 4413326Sktlim@umich.edu 4425714Shsul@eecs.umich.edu /** Read this context's system-wide ID **/ 4435714Shsul@eecs.umich.edu int contextId() { return thread->contextId(); } 4445714Shsul@eecs.umich.edu 4451060SN/A /** Returns the fault type. */ 4462132SN/A Fault getFault() { return fault; } 4471060SN/A 4481060SN/A /** Checks whether or not this instruction has had its branch target 4491060SN/A * calculated yet. For now it is not utilized and is hacked to be 4501060SN/A * always false. 4512292SN/A * @todo: Actually use this instruction. 4521060SN/A */ 4531060SN/A bool doneTargCalc() { return false; } 4541060SN/A 4557720Sgblack@eecs.umich.edu /** Set the predicted target of this current instruction. */ 4567720Sgblack@eecs.umich.edu void setPredTarg(const TheISA::PCState &_predPC) 4573965Sgblack@eecs.umich.edu { 4587720Sgblack@eecs.umich.edu predPC = _predPC; 4593965Sgblack@eecs.umich.edu } 4602935Sksewell@umich.edu 4617720Sgblack@eecs.umich.edu const TheISA::PCState &readPredTarg() { return predPC; } 4621060SN/A 4633794Sgblack@eecs.umich.edu /** Returns the predicted PC immediately after the branch. */ 4647720Sgblack@eecs.umich.edu Addr predInstAddr() { return predPC.instAddr(); } 4653794Sgblack@eecs.umich.edu 4663794Sgblack@eecs.umich.edu /** Returns the predicted PC two instructions after the branch */ 4677720Sgblack@eecs.umich.edu Addr predNextInstAddr() { return predPC.nextInstAddr(); } 4681060SN/A 4694636Sgblack@eecs.umich.edu /** Returns the predicted micro PC after the branch */ 4707720Sgblack@eecs.umich.edu Addr predMicroPC() { return predPC.microPC(); } 4714636Sgblack@eecs.umich.edu 4721060SN/A /** Returns whether the instruction was predicted taken or not. */ 4733794Sgblack@eecs.umich.edu bool readPredTaken() 4743794Sgblack@eecs.umich.edu { 4753794Sgblack@eecs.umich.edu return predTaken; 4763794Sgblack@eecs.umich.edu } 4773794Sgblack@eecs.umich.edu 4783794Sgblack@eecs.umich.edu void setPredTaken(bool predicted_taken) 4793794Sgblack@eecs.umich.edu { 4803794Sgblack@eecs.umich.edu predTaken = predicted_taken; 4813794Sgblack@eecs.umich.edu } 4821060SN/A 4831060SN/A /** Returns whether the instruction mispredicted. */ 4842935Sksewell@umich.edu bool mispredicted() 4853794Sgblack@eecs.umich.edu { 4867720Sgblack@eecs.umich.edu TheISA::PCState tempPC = pc; 4877720Sgblack@eecs.umich.edu TheISA::advancePC(tempPC, staticInst); 4887720Sgblack@eecs.umich.edu return !(tempPC == predPC); 4893794Sgblack@eecs.umich.edu } 4903794Sgblack@eecs.umich.edu 4911060SN/A // 4921060SN/A // Instruction types. Forward checks to StaticInst object. 4931060SN/A // 4945543Ssaidi@eecs.umich.edu bool isNop() const { return staticInst->isNop(); } 4955543Ssaidi@eecs.umich.edu bool isMemRef() const { return staticInst->isMemRef(); } 4965543Ssaidi@eecs.umich.edu bool isLoad() const { return staticInst->isLoad(); } 4975543Ssaidi@eecs.umich.edu bool isStore() const { return staticInst->isStore(); } 4982336SN/A bool isStoreConditional() const 4992336SN/A { return staticInst->isStoreConditional(); } 5001060SN/A bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 5011060SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 5021060SN/A bool isCopy() const { return staticInst->isCopy(); } 5035543Ssaidi@eecs.umich.edu bool isInteger() const { return staticInst->isInteger(); } 5045543Ssaidi@eecs.umich.edu bool isFloating() const { return staticInst->isFloating(); } 5055543Ssaidi@eecs.umich.edu bool isControl() const { return staticInst->isControl(); } 5065543Ssaidi@eecs.umich.edu bool isCall() const { return staticInst->isCall(); } 5075543Ssaidi@eecs.umich.edu bool isReturn() const { return staticInst->isReturn(); } 5085543Ssaidi@eecs.umich.edu bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 5091060SN/A bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 5105543Ssaidi@eecs.umich.edu bool isCondCtrl() const { return staticInst->isCondCtrl(); } 5115543Ssaidi@eecs.umich.edu bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 5122935Sksewell@umich.edu bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 5131060SN/A bool isThreadSync() const { return staticInst->isThreadSync(); } 5141060SN/A bool isSerializing() const { return staticInst->isSerializing(); } 5152292SN/A bool isSerializeBefore() const 5162731Sktlim@umich.edu { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 5172292SN/A bool isSerializeAfter() const 5182731Sktlim@umich.edu { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 5197784SAli.Saidi@ARM.com bool isSquashAfter() const { return staticInst->isSquashAfter(); } 5201060SN/A bool isMemBarrier() const { return staticInst->isMemBarrier(); } 5211060SN/A bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 5221060SN/A bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 5232292SN/A bool isQuiesce() const { return staticInst->isQuiesce(); } 5242336SN/A bool isIprAccess() const { return staticInst->isIprAccess(); } 5252308SN/A bool isUnverifiable() const { return staticInst->isUnverifiable(); } 5264828Sgblack@eecs.umich.edu bool isSyscall() const { return staticInst->isSyscall(); } 5274654Sgblack@eecs.umich.edu bool isMacroop() const { return staticInst->isMacroop(); } 5284654Sgblack@eecs.umich.edu bool isMicroop() const { return staticInst->isMicroop(); } 5294636Sgblack@eecs.umich.edu bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 5304654Sgblack@eecs.umich.edu bool isLastMicroop() const { return staticInst->isLastMicroop(); } 5314654Sgblack@eecs.umich.edu bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 5324636Sgblack@eecs.umich.edu bool isMicroBranch() const { return staticInst->isMicroBranch(); } 5332292SN/A 5342292SN/A /** Temporarily sets this instruction as a serialize before instruction. */ 5352731Sktlim@umich.edu void setSerializeBefore() { status.set(SerializeBefore); } 5362292SN/A 5372292SN/A /** Clears the serializeBefore part of this instruction. */ 5382731Sktlim@umich.edu void clearSerializeBefore() { status.reset(SerializeBefore); } 5392292SN/A 5402292SN/A /** Checks if this serializeBefore is only temporarily set. */ 5412731Sktlim@umich.edu bool isTempSerializeBefore() { return status[SerializeBefore]; } 5422292SN/A 5432292SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 5442731Sktlim@umich.edu void setSerializeAfter() { status.set(SerializeAfter); } 5452292SN/A 5462292SN/A /** Clears the serializeAfter part of this instruction.*/ 5472731Sktlim@umich.edu void clearSerializeAfter() { status.reset(SerializeAfter); } 5482292SN/A 5492292SN/A /** Checks if this serializeAfter is only temporarily set. */ 5502731Sktlim@umich.edu bool isTempSerializeAfter() { return status[SerializeAfter]; } 5512292SN/A 5522731Sktlim@umich.edu /** Sets the serialization part of this instruction as handled. */ 5532731Sktlim@umich.edu void setSerializeHandled() { status.set(SerializeHandled); } 5542292SN/A 5552292SN/A /** Checks if the serialization part of this instruction has been 5562292SN/A * handled. This does not apply to the temporary serializing 5572292SN/A * state; it only applies to this instruction's own permanent 5582292SN/A * serializing state. 5592292SN/A */ 5602731Sktlim@umich.edu bool isSerializeHandled() { return status[SerializeHandled]; } 5611060SN/A 5621464SN/A /** Returns the opclass of this instruction. */ 5631464SN/A OpClass opClass() const { return staticInst->opClass(); } 5641464SN/A 5651464SN/A /** Returns the branch target address. */ 5667720Sgblack@eecs.umich.edu TheISA::PCState branchTarget() const 5677720Sgblack@eecs.umich.edu { return staticInst->branchTarget(pc); } 5681464SN/A 5692292SN/A /** Returns the number of source registers. */ 5705543Ssaidi@eecs.umich.edu int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 5711684SN/A 5722292SN/A /** Returns the number of destination registers. */ 5731060SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 5741060SN/A 5751060SN/A // the following are used to track physical register usage 5761060SN/A // for machines with separate int & FP reg files 5771060SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 5781060SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 5791060SN/A 5801060SN/A /** Returns the logical register index of the i'th destination register. */ 5812292SN/A RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 5821060SN/A 5831060SN/A /** Returns the logical register index of the i'th source register. */ 5842292SN/A RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 5851060SN/A 5861684SN/A /** Returns the result of an integer instruction. */ 5871464SN/A uint64_t readIntResult() { return instResult.integer; } 5881684SN/A 5891684SN/A /** Returns the result of a floating point instruction. */ 5902356SN/A float readFloatResult() { return (float)instResult.dbl; } 5911684SN/A 5921684SN/A /** Returns the result of a floating point (double) instruction. */ 5931464SN/A double readDoubleResult() { return instResult.dbl; } 5941060SN/A 5952702Sktlim@umich.edu /** Records an integer register being set to a value. */ 5963735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 5971060SN/A { 5983326Sktlim@umich.edu if (recordResult) 5993326Sktlim@umich.edu instResult.integer = val; 6001060SN/A } 6011060SN/A 6022702Sktlim@umich.edu /** Records an fp register being set to a value. */ 6033735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 6043735Sstever@eecs.umich.edu int width) 6052690Sktlim@umich.edu { 6063326Sktlim@umich.edu if (recordResult) { 6073326Sktlim@umich.edu if (width == 32) 6083326Sktlim@umich.edu instResult.dbl = (double)val; 6093326Sktlim@umich.edu else if (width == 64) 6103326Sktlim@umich.edu instResult.dbl = val; 6113326Sktlim@umich.edu else 6123326Sktlim@umich.edu panic("Unsupported width!"); 6133326Sktlim@umich.edu } 6142690Sktlim@umich.edu } 6152690Sktlim@umich.edu 6162702Sktlim@umich.edu /** Records an fp register being set to a value. */ 6173735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 6181060SN/A { 6193326Sktlim@umich.edu if (recordResult) 6203326Sktlim@umich.edu instResult.dbl = (double)val; 6212308SN/A } 6221060SN/A 6232702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 6243735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 6253735Sstever@eecs.umich.edu int width) 6262308SN/A { 6273326Sktlim@umich.edu if (recordResult) 6283326Sktlim@umich.edu instResult.integer = val; 6292308SN/A } 6301060SN/A 6312702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 6323735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 6332308SN/A { 6343326Sktlim@umich.edu if (recordResult) 6353326Sktlim@umich.edu instResult.integer = val; 6361060SN/A } 6371060SN/A 6382190SN/A /** Records that one of the source registers is ready. */ 6392292SN/A void markSrcRegReady(); 6402190SN/A 6412331SN/A /** Marks a specific register as ready. */ 6422292SN/A void markSrcRegReady(RegIndex src_idx); 6432190SN/A 6441684SN/A /** Returns if a source register is ready. */ 6451464SN/A bool isReadySrcRegIdx(int idx) const 6461464SN/A { 6471464SN/A return this->_readySrcRegIdx[idx]; 6481464SN/A } 6491464SN/A 6501684SN/A /** Sets this instruction as completed. */ 6512731Sktlim@umich.edu void setCompleted() { status.set(Completed); } 6521464SN/A 6532292SN/A /** Returns whether or not this instruction is completed. */ 6542731Sktlim@umich.edu bool isCompleted() const { return status[Completed]; } 6551464SN/A 6562731Sktlim@umich.edu /** Marks the result as ready. */ 6572731Sktlim@umich.edu void setResultReady() { status.set(ResultReady); } 6582308SN/A 6592731Sktlim@umich.edu /** Returns whether or not the result is ready. */ 6602731Sktlim@umich.edu bool isResultReady() const { return status[ResultReady]; } 6612308SN/A 6621060SN/A /** Sets this instruction as ready to issue. */ 6632731Sktlim@umich.edu void setCanIssue() { status.set(CanIssue); } 6641060SN/A 6651060SN/A /** Returns whether or not this instruction is ready to issue. */ 6662731Sktlim@umich.edu bool readyToIssue() const { return status[CanIssue]; } 6671060SN/A 6684032Sktlim@umich.edu /** Clears this instruction being able to issue. */ 6694032Sktlim@umich.edu void clearCanIssue() { status.reset(CanIssue); } 6704032Sktlim@umich.edu 6711060SN/A /** Sets this instruction as issued from the IQ. */ 6722731Sktlim@umich.edu void setIssued() { status.set(Issued); } 6731060SN/A 6741060SN/A /** Returns whether or not this instruction has issued. */ 6752731Sktlim@umich.edu bool isIssued() const { return status[Issued]; } 6761060SN/A 6774032Sktlim@umich.edu /** Clears this instruction as being issued. */ 6784032Sktlim@umich.edu void clearIssued() { status.reset(Issued); } 6794032Sktlim@umich.edu 6801060SN/A /** Sets this instruction as executed. */ 6812731Sktlim@umich.edu void setExecuted() { status.set(Executed); } 6821060SN/A 6831060SN/A /** Returns whether or not this instruction has executed. */ 6842731Sktlim@umich.edu bool isExecuted() const { return status[Executed]; } 6851060SN/A 6861060SN/A /** Sets this instruction as ready to commit. */ 6872731Sktlim@umich.edu void setCanCommit() { status.set(CanCommit); } 6881060SN/A 6891061SN/A /** Clears this instruction as being ready to commit. */ 6902731Sktlim@umich.edu void clearCanCommit() { status.reset(CanCommit); } 6911061SN/A 6921060SN/A /** Returns whether or not this instruction is ready to commit. */ 6932731Sktlim@umich.edu bool readyToCommit() const { return status[CanCommit]; } 6942731Sktlim@umich.edu 6952731Sktlim@umich.edu void setAtCommit() { status.set(AtCommit); } 6962731Sktlim@umich.edu 6972731Sktlim@umich.edu bool isAtCommit() { return status[AtCommit]; } 6981060SN/A 6992292SN/A /** Sets this instruction as committed. */ 7002731Sktlim@umich.edu void setCommitted() { status.set(Committed); } 7012292SN/A 7022292SN/A /** Returns whether or not this instruction is committed. */ 7032731Sktlim@umich.edu bool isCommitted() const { return status[Committed]; } 7042292SN/A 7051060SN/A /** Sets this instruction as squashed. */ 7062731Sktlim@umich.edu void setSquashed() { status.set(Squashed); } 7071060SN/A 7081060SN/A /** Returns whether or not this instruction is squashed. */ 7092731Sktlim@umich.edu bool isSquashed() const { return status[Squashed]; } 7101060SN/A 7112292SN/A //Instruction Queue Entry 7122292SN/A //----------------------- 7132292SN/A /** Sets this instruction as a entry the IQ. */ 7142731Sktlim@umich.edu void setInIQ() { status.set(IqEntry); } 7152292SN/A 7162292SN/A /** Sets this instruction as a entry the IQ. */ 7172731Sktlim@umich.edu void clearInIQ() { status.reset(IqEntry); } 7182731Sktlim@umich.edu 7192731Sktlim@umich.edu /** Returns whether or not this instruction has issued. */ 7202731Sktlim@umich.edu bool isInIQ() const { return status[IqEntry]; } 7212292SN/A 7221060SN/A /** Sets this instruction as squashed in the IQ. */ 7232731Sktlim@umich.edu void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 7241060SN/A 7251060SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 7262731Sktlim@umich.edu bool isSquashedInIQ() const { return status[SquashedInIQ]; } 7272292SN/A 7282292SN/A 7292292SN/A //Load / Store Queue Functions 7302292SN/A //----------------------- 7312292SN/A /** Sets this instruction as a entry the LSQ. */ 7322731Sktlim@umich.edu void setInLSQ() { status.set(LsqEntry); } 7332292SN/A 7342292SN/A /** Sets this instruction as a entry the LSQ. */ 7352731Sktlim@umich.edu void removeInLSQ() { status.reset(LsqEntry); } 7362731Sktlim@umich.edu 7372731Sktlim@umich.edu /** Returns whether or not this instruction is in the LSQ. */ 7382731Sktlim@umich.edu bool isInLSQ() const { return status[LsqEntry]; } 7392292SN/A 7402292SN/A /** Sets this instruction as squashed in the LSQ. */ 7412731Sktlim@umich.edu void setSquashedInLSQ() { status.set(SquashedInLSQ);} 7422292SN/A 7432292SN/A /** Returns whether or not this instruction is squashed in the LSQ. */ 7442731Sktlim@umich.edu bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 7452292SN/A 7462292SN/A 7472292SN/A //Reorder Buffer Functions 7482292SN/A //----------------------- 7492292SN/A /** Sets this instruction as a entry the ROB. */ 7502731Sktlim@umich.edu void setInROB() { status.set(RobEntry); } 7512292SN/A 7522292SN/A /** Sets this instruction as a entry the ROB. */ 7532731Sktlim@umich.edu void clearInROB() { status.reset(RobEntry); } 7542731Sktlim@umich.edu 7552731Sktlim@umich.edu /** Returns whether or not this instruction is in the ROB. */ 7562731Sktlim@umich.edu bool isInROB() const { return status[RobEntry]; } 7572292SN/A 7582292SN/A /** Sets this instruction as squashed in the ROB. */ 7592731Sktlim@umich.edu void setSquashedInROB() { status.set(SquashedInROB); } 7602292SN/A 7612292SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 7622731Sktlim@umich.edu bool isSquashedInROB() const { return status[SquashedInROB]; } 7632292SN/A 7647720Sgblack@eecs.umich.edu /** Read the PC state of this instruction. */ 7657720Sgblack@eecs.umich.edu const TheISA::PCState pcState() const { return pc; } 7667720Sgblack@eecs.umich.edu 7677720Sgblack@eecs.umich.edu /** Set the PC state of this instruction. */ 7687720Sgblack@eecs.umich.edu const void pcState(const TheISA::PCState &val) { pc = val; } 7697720Sgblack@eecs.umich.edu 7701060SN/A /** Read the PC of this instruction. */ 7717720Sgblack@eecs.umich.edu const Addr instAddr() const { return pc.instAddr(); } 7727720Sgblack@eecs.umich.edu 7737720Sgblack@eecs.umich.edu /** Read the PC of the next instruction. */ 7747720Sgblack@eecs.umich.edu const Addr nextInstAddr() const { return pc.nextInstAddr(); } 7751060SN/A 7764636Sgblack@eecs.umich.edu /**Read the micro PC of this instruction. */ 7777720Sgblack@eecs.umich.edu const Addr microPC() const { return pc.microPC(); } 7784636Sgblack@eecs.umich.edu 7797597Sminkyu.jeong@arm.com bool readPredicate() 7807597Sminkyu.jeong@arm.com { 7817597Sminkyu.jeong@arm.com return predicate; 7827597Sminkyu.jeong@arm.com } 7837597Sminkyu.jeong@arm.com 7847597Sminkyu.jeong@arm.com void setPredicate(bool val) 7857597Sminkyu.jeong@arm.com { 7867597Sminkyu.jeong@arm.com predicate = val; 7877600Sminkyu.jeong@arm.com 7887600Sminkyu.jeong@arm.com if (traceData) { 7897600Sminkyu.jeong@arm.com traceData->setPredicate(val); 7907600Sminkyu.jeong@arm.com } 7917597Sminkyu.jeong@arm.com } 7927597Sminkyu.jeong@arm.com 7932702Sktlim@umich.edu /** Sets the ASID. */ 7942292SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 7952292SN/A 7962702Sktlim@umich.edu /** Sets the thread id. */ 7976221Snate@binkert.org void setTid(ThreadID tid) { threadNumber = tid; } 7982292SN/A 7992731Sktlim@umich.edu /** Sets the pointer to the thread state. */ 8002702Sktlim@umich.edu void setThreadState(ImplState *state) { thread = state; } 8011060SN/A 8022731Sktlim@umich.edu /** Returns the thread context. */ 8032680Sktlim@umich.edu ThreadContext *tcBase() { return thread->getTC(); } 8041464SN/A 8051464SN/A private: 8061684SN/A /** Instruction effective address. 8071684SN/A * @todo: Consider if this is necessary or not. 8081684SN/A */ 8091464SN/A Addr instEffAddr; 8102292SN/A 8111684SN/A /** Whether or not the effective address calculation is completed. 8121684SN/A * @todo: Consider if this is necessary or not. 8131684SN/A */ 8141464SN/A bool eaCalcDone; 8151464SN/A 8164032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 8174032Sktlim@umich.edu bool isUncacheable; 8184032Sktlim@umich.edu 8194032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8204032Sktlim@umich.edu bool reqMade; 8214032Sktlim@umich.edu 8221464SN/A public: 8231684SN/A /** Sets the effective address. */ 8241464SN/A void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 8251684SN/A 8261684SN/A /** Returns the effective address. */ 8271464SN/A const Addr &getEA() const { return instEffAddr; } 8281684SN/A 8291684SN/A /** Returns whether or not the eff. addr. calculation has been completed. */ 8301464SN/A bool doneEACalc() { return eaCalcDone; } 8311684SN/A 8321684SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 8331464SN/A bool eaSrcsReady(); 8341681SN/A 8352292SN/A /** Whether or not the memory operation is done. */ 8362292SN/A bool memOpDone; 8372292SN/A 8384032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 8394032Sktlim@umich.edu bool uncacheable() { return isUncacheable; } 8404032Sktlim@umich.edu 8414032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8424032Sktlim@umich.edu bool hasRequest() { return reqMade; } 8434032Sktlim@umich.edu 8441681SN/A public: 8451684SN/A /** Load queue index. */ 8461681SN/A int16_t lqIdx; 8471684SN/A 8481684SN/A /** Store queue index. */ 8491681SN/A int16_t sqIdx; 8502292SN/A 8512292SN/A /** Iterator pointing to this BaseDynInst in the list of all insts. */ 8522292SN/A ListIt instListIt; 8532292SN/A 8542292SN/A /** Returns iterator to this instruction in the list of all insts. */ 8552292SN/A ListIt &getInstListIt() { return instListIt; } 8562292SN/A 8572292SN/A /** Sets iterator for this instruction in the list of all insts. */ 8582292SN/A void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 8593326Sktlim@umich.edu 8603326Sktlim@umich.edu public: 8613326Sktlim@umich.edu /** Returns the number of consecutive store conditional failures. */ 8623326Sktlim@umich.edu unsigned readStCondFailures() 8633326Sktlim@umich.edu { return thread->storeCondFailures; } 8643326Sktlim@umich.edu 8653326Sktlim@umich.edu /** Sets the number of consecutive store conditional failures. */ 8663326Sktlim@umich.edu void setStCondFailures(unsigned sc_failures) 8673326Sktlim@umich.edu { thread->storeCondFailures = sc_failures; } 8681060SN/A}; 8691060SN/A 8701060SN/Atemplate<class Impl> 8717520Sgblack@eecs.umich.eduFault 8727520Sgblack@eecs.umich.eduBaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data, 8737520Sgblack@eecs.umich.edu unsigned size, unsigned flags) 8741060SN/A{ 8754032Sktlim@umich.edu reqMade = true; 8767944SGiacomo.Gabrielli@arm.com Request *req = NULL; 8776974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 8786974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 8796974Stjones1@inf.ed.ac.uk 8807944SGiacomo.Gabrielli@arm.com if (reqMade && translationStarted) { 8817944SGiacomo.Gabrielli@arm.com req = savedReq; 8827944SGiacomo.Gabrielli@arm.com sreqLow = savedSreqLow; 8837944SGiacomo.Gabrielli@arm.com sreqHigh = savedSreqHigh; 8847944SGiacomo.Gabrielli@arm.com } else { 8857944SGiacomo.Gabrielli@arm.com req = new Request(asid, addr, size, flags, this->pc.instAddr(), 8867944SGiacomo.Gabrielli@arm.com thread->contextId(), threadNumber); 8874032Sktlim@umich.edu 8887944SGiacomo.Gabrielli@arm.com // Only split the request if the ISA supports unaligned accesses. 8897944SGiacomo.Gabrielli@arm.com if (TheISA::HasUnalignedMemAcc) { 8907944SGiacomo.Gabrielli@arm.com splitRequest(req, sreqLow, sreqHigh); 8917944SGiacomo.Gabrielli@arm.com } 8927944SGiacomo.Gabrielli@arm.com initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 8931060SN/A } 8941060SN/A 8957944SGiacomo.Gabrielli@arm.com if (translationCompleted) { 8967944SGiacomo.Gabrielli@arm.com if (fault == NoFault) { 8977944SGiacomo.Gabrielli@arm.com effAddr = req->getVaddr(); 8988199SAli.Saidi@ARM.com effSize = size; 8997944SGiacomo.Gabrielli@arm.com effAddrValid = true; 9007944SGiacomo.Gabrielli@arm.com fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); 9017944SGiacomo.Gabrielli@arm.com } else { 9027944SGiacomo.Gabrielli@arm.com // Commit will have to clean up whatever happened. Set this 9037944SGiacomo.Gabrielli@arm.com // instruction as executed. 9047944SGiacomo.Gabrielli@arm.com this->setExecuted(); 9057944SGiacomo.Gabrielli@arm.com } 9067944SGiacomo.Gabrielli@arm.com 9077944SGiacomo.Gabrielli@arm.com if (fault != NoFault) { 9087944SGiacomo.Gabrielli@arm.com // Return a fixed value to keep simulation deterministic even 9097944SGiacomo.Gabrielli@arm.com // along misspeculated paths. 9107944SGiacomo.Gabrielli@arm.com if (data) 9117944SGiacomo.Gabrielli@arm.com bzero(data, size); 9127944SGiacomo.Gabrielli@arm.com } 9137577SAli.Saidi@ARM.com } 9147577SAli.Saidi@ARM.com 9151060SN/A if (traceData) { 9161060SN/A traceData->setAddr(addr); 9171060SN/A } 9181060SN/A 9191060SN/A return fault; 9201060SN/A} 9211060SN/A 9221060SN/Atemplate<class Impl> 9231060SN/Atemplate<class T> 9242132SN/Ainline Fault 9257520Sgblack@eecs.umich.eduBaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 9267520Sgblack@eecs.umich.edu{ 9277520Sgblack@eecs.umich.edu Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags); 9287520Sgblack@eecs.umich.edu 9297520Sgblack@eecs.umich.edu data = TheISA::gtoh(data); 9307520Sgblack@eecs.umich.edu 9317520Sgblack@eecs.umich.edu if (traceData) { 9327520Sgblack@eecs.umich.edu traceData->setData(data); 9337520Sgblack@eecs.umich.edu } 9347520Sgblack@eecs.umich.edu 9357520Sgblack@eecs.umich.edu return fault; 9367520Sgblack@eecs.umich.edu} 9377520Sgblack@eecs.umich.edu 9387520Sgblack@eecs.umich.edutemplate<class Impl> 9397520Sgblack@eecs.umich.eduFault 9407520Sgblack@eecs.umich.eduBaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size, 9417520Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 9421060SN/A{ 9431060SN/A if (traceData) { 9441060SN/A traceData->setAddr(addr); 9451060SN/A } 9461060SN/A 9474032Sktlim@umich.edu reqMade = true; 9487944SGiacomo.Gabrielli@arm.com Request *req = NULL; 9496974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 9506974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 9516974Stjones1@inf.ed.ac.uk 9527944SGiacomo.Gabrielli@arm.com if (reqMade && translationStarted) { 9537944SGiacomo.Gabrielli@arm.com req = savedReq; 9547944SGiacomo.Gabrielli@arm.com sreqLow = savedSreqLow; 9557944SGiacomo.Gabrielli@arm.com sreqHigh = savedSreqHigh; 9567944SGiacomo.Gabrielli@arm.com } else { 9577944SGiacomo.Gabrielli@arm.com req = new Request(asid, addr, size, flags, this->pc.instAddr(), 9587944SGiacomo.Gabrielli@arm.com thread->contextId(), threadNumber); 9597944SGiacomo.Gabrielli@arm.com 9607944SGiacomo.Gabrielli@arm.com // Only split the request if the ISA supports unaligned accesses. 9617944SGiacomo.Gabrielli@arm.com if (TheISA::HasUnalignedMemAcc) { 9627944SGiacomo.Gabrielli@arm.com splitRequest(req, sreqLow, sreqHigh); 9637944SGiacomo.Gabrielli@arm.com } 9647944SGiacomo.Gabrielli@arm.com initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 9656974Stjones1@inf.ed.ac.uk } 9664032Sktlim@umich.edu 9677944SGiacomo.Gabrielli@arm.com if (fault == NoFault && translationCompleted) { 9682678Sktlim@umich.edu effAddr = req->getVaddr(); 9698199SAli.Saidi@ARM.com effSize = size; 9704032Sktlim@umich.edu effAddrValid = true; 9716975Stjones1@inf.ed.ac.uk fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 9721060SN/A } 9731060SN/A 9741060SN/A return fault; 9751060SN/A} 9761060SN/A 9776973Stjones1@inf.ed.ac.uktemplate<class Impl> 9787520Sgblack@eecs.umich.edutemplate<class T> 9797520Sgblack@eecs.umich.eduinline Fault 9807520Sgblack@eecs.umich.eduBaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 9817520Sgblack@eecs.umich.edu{ 9827520Sgblack@eecs.umich.edu if (traceData) { 9837520Sgblack@eecs.umich.edu traceData->setData(data); 9847520Sgblack@eecs.umich.edu } 9857520Sgblack@eecs.umich.edu data = TheISA::htog(data); 9867520Sgblack@eecs.umich.edu return writeBytes((uint8_t *)&data, sizeof(T), addr, flags, res); 9877520Sgblack@eecs.umich.edu} 9887520Sgblack@eecs.umich.edu 9897520Sgblack@eecs.umich.edutemplate<class Impl> 9906973Stjones1@inf.ed.ac.ukinline void 9916974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 9926974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh) 9936974Stjones1@inf.ed.ac.uk{ 9946974Stjones1@inf.ed.ac.uk // Check to see if the request crosses the next level block boundary. 9956974Stjones1@inf.ed.ac.uk unsigned block_size = cpu->getDcachePort()->peerBlockSize(); 9966974Stjones1@inf.ed.ac.uk Addr addr = req->getVaddr(); 9976974Stjones1@inf.ed.ac.uk Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 9986974Stjones1@inf.ed.ac.uk assert(split_addr <= addr || split_addr - addr < block_size); 9996974Stjones1@inf.ed.ac.uk 10006974Stjones1@inf.ed.ac.uk // Spans two blocks. 10016974Stjones1@inf.ed.ac.uk if (split_addr > addr) { 10026974Stjones1@inf.ed.ac.uk req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 10036974Stjones1@inf.ed.ac.uk } 10046974Stjones1@inf.ed.ac.uk} 10056974Stjones1@inf.ed.ac.uk 10066974Stjones1@inf.ed.ac.uktemplate<class Impl> 10076974Stjones1@inf.ed.ac.ukinline void 10086974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 10096974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 10106973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode) 10116973Stjones1@inf.ed.ac.uk{ 10127944SGiacomo.Gabrielli@arm.com translationStarted = true; 10137944SGiacomo.Gabrielli@arm.com 10146974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 10156974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 10166974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, NULL, res, mode); 10176974Stjones1@inf.ed.ac.uk 10186974Stjones1@inf.ed.ac.uk // One translation if the request isn't split. 10196974Stjones1@inf.ed.ac.uk DataTranslation<BaseDynInst<Impl> > *trans = 10206974Stjones1@inf.ed.ac.uk new DataTranslation<BaseDynInst<Impl> >(this, state); 10216974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 10227944SGiacomo.Gabrielli@arm.com if (!translationCompleted) { 10237944SGiacomo.Gabrielli@arm.com // Save memory requests. 10247944SGiacomo.Gabrielli@arm.com savedReq = state->mainReq; 10257944SGiacomo.Gabrielli@arm.com savedSreqLow = state->sreqLow; 10267944SGiacomo.Gabrielli@arm.com savedSreqHigh = state->sreqHigh; 10277944SGiacomo.Gabrielli@arm.com } 10286974Stjones1@inf.ed.ac.uk } else { 10296974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 10306974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 10316974Stjones1@inf.ed.ac.uk 10326974Stjones1@inf.ed.ac.uk // Two translations when the request is split. 10336974Stjones1@inf.ed.ac.uk DataTranslation<BaseDynInst<Impl> > *stransLow = 10346974Stjones1@inf.ed.ac.uk new DataTranslation<BaseDynInst<Impl> >(this, state, 0); 10356974Stjones1@inf.ed.ac.uk DataTranslation<BaseDynInst<Impl> > *stransHigh = 10366974Stjones1@inf.ed.ac.uk new DataTranslation<BaseDynInst<Impl> >(this, state, 1); 10376974Stjones1@inf.ed.ac.uk 10386974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 10396974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 10407944SGiacomo.Gabrielli@arm.com if (!translationCompleted) { 10417944SGiacomo.Gabrielli@arm.com // Save memory requests. 10427944SGiacomo.Gabrielli@arm.com savedReq = state->mainReq; 10437944SGiacomo.Gabrielli@arm.com savedSreqLow = state->sreqLow; 10447944SGiacomo.Gabrielli@arm.com savedSreqHigh = state->sreqHigh; 10457944SGiacomo.Gabrielli@arm.com } 10466974Stjones1@inf.ed.ac.uk } 10476973Stjones1@inf.ed.ac.uk} 10486973Stjones1@inf.ed.ac.uk 10496973Stjones1@inf.ed.ac.uktemplate<class Impl> 10506973Stjones1@inf.ed.ac.ukinline void 10516973Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 10526973Stjones1@inf.ed.ac.uk{ 10536973Stjones1@inf.ed.ac.uk fault = state->getFault(); 10546973Stjones1@inf.ed.ac.uk 10556973Stjones1@inf.ed.ac.uk if (state->isUncacheable()) 10566973Stjones1@inf.ed.ac.uk isUncacheable = true; 10576973Stjones1@inf.ed.ac.uk 10586973Stjones1@inf.ed.ac.uk if (fault == NoFault) { 10596973Stjones1@inf.ed.ac.uk physEffAddr = state->getPaddr(); 10606973Stjones1@inf.ed.ac.uk memReqFlags = state->getFlags(); 10616973Stjones1@inf.ed.ac.uk 10626973Stjones1@inf.ed.ac.uk if (state->mainReq->isCondSwap()) { 10636973Stjones1@inf.ed.ac.uk assert(state->res); 10646973Stjones1@inf.ed.ac.uk state->mainReq->setExtraData(*state->res); 10656973Stjones1@inf.ed.ac.uk } 10666973Stjones1@inf.ed.ac.uk 10676973Stjones1@inf.ed.ac.uk } else { 10686973Stjones1@inf.ed.ac.uk state->deleteReqs(); 10696973Stjones1@inf.ed.ac.uk } 10706973Stjones1@inf.ed.ac.uk delete state; 10717944SGiacomo.Gabrielli@arm.com 10727944SGiacomo.Gabrielli@arm.com translationCompleted = true; 10736973Stjones1@inf.ed.ac.uk} 10746973Stjones1@inf.ed.ac.uk 10751464SN/A#endif // __CPU_BASE_DYN_INST_HH__ 1076