base_dyn_inst.hh revision 6023
11060SN/A/* 22702Sktlim@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 31060SN/A * All rights reserved. 41060SN/A * 51060SN/A * Redistribution and use in source and binary forms, with or without 61060SN/A * modification, are permitted provided that the following conditions are 71060SN/A * met: redistributions of source code must retain the above copyright 81060SN/A * notice, this list of conditions and the following disclaimer; 91060SN/A * redistributions in binary form must reproduce the above copyright 101060SN/A * notice, this list of conditions and the following disclaimer in the 111060SN/A * documentation and/or other materials provided with the distribution; 121060SN/A * neither the name of the copyright holders nor the names of its 131060SN/A * contributors may be used to endorse or promote products derived from 141060SN/A * this software without specific prior written permission. 151060SN/A * 161060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291060SN/A */ 301060SN/A 311464SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 321464SN/A#define __CPU_BASE_DYN_INST_HH__ 331060SN/A 342731Sktlim@umich.edu#include <bitset> 352292SN/A#include <list> 361464SN/A#include <string> 371060SN/A 382669Sktlim@umich.edu#include "arch/faults.hh" 391060SN/A#include "base/fast_alloc.hh" 401060SN/A#include "base/trace.hh" 411858SN/A#include "config/full_system.hh" 423770Sgblack@eecs.umich.edu#include "cpu/o3/comm.hh" 431464SN/A#include "cpu/exetrace.hh" 441464SN/A#include "cpu/inst_seq.hh" 452669Sktlim@umich.edu#include "cpu/op_class.hh" 461060SN/A#include "cpu/static_inst.hh" 472669Sktlim@umich.edu#include "mem/packet.hh" 482292SN/A#include "sim/system.hh" 496023Snate@binkert.org#include "sim/tlb.hh" 501060SN/A 511060SN/A/** 521060SN/A * @file 531060SN/A * Defines a dynamic instruction context. 541060SN/A */ 551060SN/A 561061SN/A// Forward declaration. 571061SN/Aclass StaticInstPtr; 581060SN/A 591060SN/Atemplate <class Impl> 601061SN/Aclass BaseDynInst : public FastAlloc, public RefCounted 611060SN/A{ 621060SN/A public: 631060SN/A // Typedef for the CPU. 642733Sktlim@umich.edu typedef typename Impl::CPUType ImplCPU; 652733Sktlim@umich.edu typedef typename ImplCPU::ImplState ImplState; 661060SN/A 672292SN/A // Logical register index type. 682107SN/A typedef TheISA::RegIndex RegIndex; 692690Sktlim@umich.edu // Integer register type. 702107SN/A typedef TheISA::IntReg IntReg; 712690Sktlim@umich.edu // Floating point register type. 722690Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 731060SN/A 742292SN/A // The DynInstPtr type. 752292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 762292SN/A 772292SN/A // The list of instructions iterator type. 782292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 792292SN/A 801060SN/A enum { 815543Ssaidi@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 825543Ssaidi@eecs.umich.edu MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 831060SN/A }; 841060SN/A 852292SN/A /** The StaticInst used by this BaseDynInst. */ 862107SN/A StaticInstPtr staticInst; 871060SN/A 881060SN/A //////////////////////////////////////////// 891060SN/A // 901060SN/A // INSTRUCTION EXECUTION 911060SN/A // 921060SN/A //////////////////////////////////////////// 932292SN/A /** InstRecord that tracks this instructions. */ 941060SN/A Trace::InstRecord *traceData; 951060SN/A 965358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 975358Sgblack@eecs.umich.edu { 985358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 995358Sgblack@eecs.umich.edu } 1005358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1015358Sgblack@eecs.umich.edu { 1025358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1035358Sgblack@eecs.umich.edu } 1045358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1055358Sgblack@eecs.umich.edu { 1065358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1075358Sgblack@eecs.umich.edu } 1085358Sgblack@eecs.umich.edu 1092292SN/A /** 1102292SN/A * Does a read to a given address. 1112292SN/A * @param addr The address to read. 1122292SN/A * @param data The read's data is written into this parameter. 1132292SN/A * @param flags The request's flags. 1142292SN/A * @return Returns any fault due to the read. 1152292SN/A */ 1161060SN/A template <class T> 1172132SN/A Fault read(Addr addr, T &data, unsigned flags); 1181060SN/A 1192292SN/A /** 1202292SN/A * Does a write to a given address. 1212292SN/A * @param data The data to be written. 1222292SN/A * @param addr The address to write to. 1232292SN/A * @param flags The request's flags. 1242292SN/A * @param res The result of the write (for load locked/store conditionals). 1252292SN/A * @return Returns any fault due to the write. 1262292SN/A */ 1271060SN/A template <class T> 1282132SN/A Fault write(T data, Addr addr, unsigned flags, 1291060SN/A uint64_t *res); 1301060SN/A 1311060SN/A void prefetch(Addr addr, unsigned flags); 1321060SN/A void writeHint(Addr addr, int size, unsigned flags); 1332132SN/A Fault copySrcTranslate(Addr src); 1342132SN/A Fault copy(Addr dest); 1351060SN/A 1361684SN/A /** @todo: Consider making this private. */ 1371060SN/A public: 1381060SN/A /** The sequence number of the instruction. */ 1391060SN/A InstSeqNum seqNum; 1401060SN/A 1412731Sktlim@umich.edu enum Status { 1422731Sktlim@umich.edu IqEntry, /// Instruction is in the IQ 1432731Sktlim@umich.edu RobEntry, /// Instruction is in the ROB 1442731Sktlim@umich.edu LsqEntry, /// Instruction is in the LSQ 1452731Sktlim@umich.edu Completed, /// Instruction has completed 1462731Sktlim@umich.edu ResultReady, /// Instruction has its result 1472731Sktlim@umich.edu CanIssue, /// Instruction can issue and execute 1482731Sktlim@umich.edu Issued, /// Instruction has issued 1492731Sktlim@umich.edu Executed, /// Instruction has executed 1502731Sktlim@umich.edu CanCommit, /// Instruction can commit 1512731Sktlim@umich.edu AtCommit, /// Instruction has reached commit 1522731Sktlim@umich.edu Committed, /// Instruction has committed 1532731Sktlim@umich.edu Squashed, /// Instruction is squashed 1542731Sktlim@umich.edu SquashedInIQ, /// Instruction is squashed in the IQ 1552731Sktlim@umich.edu SquashedInLSQ, /// Instruction is squashed in the LSQ 1562731Sktlim@umich.edu SquashedInROB, /// Instruction is squashed in the ROB 1572731Sktlim@umich.edu RecoverInst, /// Is a recover instruction 1582731Sktlim@umich.edu BlockingInst, /// Is a blocking instruction 1592731Sktlim@umich.edu ThreadsyncWait, /// Is a thread synchronization instruction 1602731Sktlim@umich.edu SerializeBefore, /// Needs to serialize on 1612731Sktlim@umich.edu /// instructions ahead of it 1622731Sktlim@umich.edu SerializeAfter, /// Needs to serialize instructions behind it 1632731Sktlim@umich.edu SerializeHandled, /// Serialization has been handled 1642731Sktlim@umich.edu NumStatus 1652731Sktlim@umich.edu }; 1662292SN/A 1672731Sktlim@umich.edu /** The status of this BaseDynInst. Several bits can be set. */ 1682731Sktlim@umich.edu std::bitset<NumStatus> status; 1691060SN/A 1701060SN/A /** The thread this instruction is from. */ 1711060SN/A short threadNumber; 1721060SN/A 1731060SN/A /** data address space ID, for loads & stores. */ 1741060SN/A short asid; 1751060SN/A 1762292SN/A /** How many source registers are ready. */ 1772292SN/A unsigned readyRegs; 1782292SN/A 1792733Sktlim@umich.edu /** Pointer to the Impl's CPU object. */ 1802733Sktlim@umich.edu ImplCPU *cpu; 1811060SN/A 1822680Sktlim@umich.edu /** Pointer to the thread state. */ 1832292SN/A ImplState *thread; 1841060SN/A 1851060SN/A /** The kind of fault this instruction has generated. */ 1862132SN/A Fault fault; 1871060SN/A 1882702Sktlim@umich.edu /** Pointer to the data for the memory access. */ 1892669Sktlim@umich.edu uint8_t *memData; 1902292SN/A 1911060SN/A /** The effective virtual address (lds & stores only). */ 1921060SN/A Addr effAddr; 1931060SN/A 1944032Sktlim@umich.edu /** Is the effective virtual address valid. */ 1954032Sktlim@umich.edu bool effAddrValid; 1964032Sktlim@umich.edu 1971060SN/A /** The effective physical address. */ 1981060SN/A Addr physEffAddr; 1991060SN/A 2001060SN/A /** Effective virtual address for a copy source. */ 2011060SN/A Addr copySrcEffAddr; 2021060SN/A 2031060SN/A /** Effective physical address for a copy source. */ 2041060SN/A Addr copySrcPhysEffAddr; 2051060SN/A 2061060SN/A /** The memory request flags (from translation). */ 2071060SN/A unsigned memReqFlags; 2081060SN/A 2091464SN/A union Result { 2101464SN/A uint64_t integer; 2112356SN/A// float fp; 2121464SN/A double dbl; 2131464SN/A }; 2141060SN/A 2151464SN/A /** The result of the instruction; assumes for now that there's only one 2161464SN/A * destination register. 2171464SN/A */ 2181464SN/A Result instResult; 2191060SN/A 2203326Sktlim@umich.edu /** Records changes to result? */ 2213326Sktlim@umich.edu bool recordResult; 2223326Sktlim@umich.edu 2231060SN/A /** PC of this instruction. */ 2241060SN/A Addr PC; 2251060SN/A 2264636Sgblack@eecs.umich.edu /** Micro PC of this instruction. */ 2274636Sgblack@eecs.umich.edu Addr microPC; 2284636Sgblack@eecs.umich.edu 2293965Sgblack@eecs.umich.edu protected: 2301060SN/A /** Next non-speculative PC. It is not filled in at fetch, but rather 2311060SN/A * once the target of the branch is truly known (either decode or 2321060SN/A * execute). 2331060SN/A */ 2341060SN/A Addr nextPC; 2351060SN/A 2362935Sksewell@umich.edu /** Next non-speculative NPC. Target PC for Mips or Sparc. */ 2372935Sksewell@umich.edu Addr nextNPC; 2382935Sksewell@umich.edu 2394636Sgblack@eecs.umich.edu /** Next non-speculative micro PC. */ 2404636Sgblack@eecs.umich.edu Addr nextMicroPC; 2414636Sgblack@eecs.umich.edu 2421060SN/A /** Predicted next PC. */ 2431060SN/A Addr predPC; 2441060SN/A 2453794Sgblack@eecs.umich.edu /** Predicted next NPC. */ 2463794Sgblack@eecs.umich.edu Addr predNPC; 2473794Sgblack@eecs.umich.edu 2484636Sgblack@eecs.umich.edu /** Predicted next microPC */ 2494636Sgblack@eecs.umich.edu Addr predMicroPC; 2504636Sgblack@eecs.umich.edu 2513794Sgblack@eecs.umich.edu /** If this is a branch that was predicted taken */ 2523794Sgblack@eecs.umich.edu bool predTaken; 2533794Sgblack@eecs.umich.edu 2543965Sgblack@eecs.umich.edu public: 2553965Sgblack@eecs.umich.edu 2562292SN/A#ifdef DEBUG 2572292SN/A void dumpSNList(); 2582292SN/A#endif 2592292SN/A 2602292SN/A /** Whether or not the source register is ready. 2612292SN/A * @todo: Not sure this should be here vs the derived class. 2621060SN/A */ 2631060SN/A bool _readySrcRegIdx[MaxInstSrcRegs]; 2641060SN/A 2653770Sgblack@eecs.umich.edu protected: 2663770Sgblack@eecs.umich.edu /** Flattened register index of the destination registers of this 2673770Sgblack@eecs.umich.edu * instruction. 2683770Sgblack@eecs.umich.edu */ 2693770Sgblack@eecs.umich.edu TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 2703770Sgblack@eecs.umich.edu 2713770Sgblack@eecs.umich.edu /** Flattened register index of the source registers of this 2723770Sgblack@eecs.umich.edu * instruction. 2733770Sgblack@eecs.umich.edu */ 2743770Sgblack@eecs.umich.edu TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 2753770Sgblack@eecs.umich.edu 2763770Sgblack@eecs.umich.edu /** Physical register index of the destination registers of this 2773770Sgblack@eecs.umich.edu * instruction. 2783770Sgblack@eecs.umich.edu */ 2793770Sgblack@eecs.umich.edu PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 2803770Sgblack@eecs.umich.edu 2813770Sgblack@eecs.umich.edu /** Physical register index of the source registers of this 2823770Sgblack@eecs.umich.edu * instruction. 2833770Sgblack@eecs.umich.edu */ 2843770Sgblack@eecs.umich.edu PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 2853770Sgblack@eecs.umich.edu 2863770Sgblack@eecs.umich.edu /** Physical register index of the previous producers of the 2873770Sgblack@eecs.umich.edu * architected destinations. 2883770Sgblack@eecs.umich.edu */ 2893770Sgblack@eecs.umich.edu PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 2903770Sgblack@eecs.umich.edu 2911060SN/A public: 2923770Sgblack@eecs.umich.edu 2933770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th destination 2943770Sgblack@eecs.umich.edu * register. 2953770Sgblack@eecs.umich.edu */ 2963770Sgblack@eecs.umich.edu PhysRegIndex renamedDestRegIdx(int idx) const 2973770Sgblack@eecs.umich.edu { 2983770Sgblack@eecs.umich.edu return _destRegIdx[idx]; 2993770Sgblack@eecs.umich.edu } 3003770Sgblack@eecs.umich.edu 3013770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th source register. */ 3023770Sgblack@eecs.umich.edu PhysRegIndex renamedSrcRegIdx(int idx) const 3033770Sgblack@eecs.umich.edu { 3043770Sgblack@eecs.umich.edu return _srcRegIdx[idx]; 3053770Sgblack@eecs.umich.edu } 3063770Sgblack@eecs.umich.edu 3073770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th destination 3083770Sgblack@eecs.umich.edu * register. 3093770Sgblack@eecs.umich.edu */ 3103770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedDestRegIdx(int idx) const 3113770Sgblack@eecs.umich.edu { 3123770Sgblack@eecs.umich.edu return _flatDestRegIdx[idx]; 3133770Sgblack@eecs.umich.edu } 3143770Sgblack@eecs.umich.edu 3153770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th source register */ 3163770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedSrcRegIdx(int idx) const 3173770Sgblack@eecs.umich.edu { 3183770Sgblack@eecs.umich.edu return _flatSrcRegIdx[idx]; 3193770Sgblack@eecs.umich.edu } 3203770Sgblack@eecs.umich.edu 3213770Sgblack@eecs.umich.edu /** Returns the physical register index of the previous physical register 3223770Sgblack@eecs.umich.edu * that remapped to the same logical register index. 3233770Sgblack@eecs.umich.edu */ 3243770Sgblack@eecs.umich.edu PhysRegIndex prevDestRegIdx(int idx) const 3253770Sgblack@eecs.umich.edu { 3263770Sgblack@eecs.umich.edu return _prevDestRegIdx[idx]; 3273770Sgblack@eecs.umich.edu } 3283770Sgblack@eecs.umich.edu 3293770Sgblack@eecs.umich.edu /** Renames a destination register to a physical register. Also records 3303770Sgblack@eecs.umich.edu * the previous physical register that the logical register mapped to. 3313770Sgblack@eecs.umich.edu */ 3323770Sgblack@eecs.umich.edu void renameDestReg(int idx, 3333770Sgblack@eecs.umich.edu PhysRegIndex renamed_dest, 3343770Sgblack@eecs.umich.edu PhysRegIndex previous_rename) 3353770Sgblack@eecs.umich.edu { 3363770Sgblack@eecs.umich.edu _destRegIdx[idx] = renamed_dest; 3373770Sgblack@eecs.umich.edu _prevDestRegIdx[idx] = previous_rename; 3383770Sgblack@eecs.umich.edu } 3393770Sgblack@eecs.umich.edu 3403770Sgblack@eecs.umich.edu /** Renames a source logical register to the physical register which 3413770Sgblack@eecs.umich.edu * has/will produce that logical register's result. 3423770Sgblack@eecs.umich.edu * @todo: add in whether or not the source register is ready. 3433770Sgblack@eecs.umich.edu */ 3443770Sgblack@eecs.umich.edu void renameSrcReg(int idx, PhysRegIndex renamed_src) 3453770Sgblack@eecs.umich.edu { 3463770Sgblack@eecs.umich.edu _srcRegIdx[idx] = renamed_src; 3473770Sgblack@eecs.umich.edu } 3483770Sgblack@eecs.umich.edu 3493770Sgblack@eecs.umich.edu /** Flattens a source architectural register index into a logical index. 3503770Sgblack@eecs.umich.edu */ 3513770Sgblack@eecs.umich.edu void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 3523770Sgblack@eecs.umich.edu { 3533770Sgblack@eecs.umich.edu _flatSrcRegIdx[idx] = flattened_src; 3543770Sgblack@eecs.umich.edu } 3553770Sgblack@eecs.umich.edu 3563770Sgblack@eecs.umich.edu /** Flattens a destination architectural register index into a logical 3573770Sgblack@eecs.umich.edu * index. 3583770Sgblack@eecs.umich.edu */ 3593770Sgblack@eecs.umich.edu void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 3603770Sgblack@eecs.umich.edu { 3613770Sgblack@eecs.umich.edu _flatDestRegIdx[idx] = flattened_dest; 3623770Sgblack@eecs.umich.edu } 3634636Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. 3644636Sgblack@eecs.umich.edu * @param staticInst A StaticInstPtr to the underlying instruction. 3654636Sgblack@eecs.umich.edu * @param PC The PC of the instruction. 3664636Sgblack@eecs.umich.edu * @param pred_PC The predicted next PC. 3674636Sgblack@eecs.umich.edu * @param pred_NPC The predicted next NPC. 3684636Sgblack@eecs.umich.edu * @param seq_num The sequence number of the instruction. 3694636Sgblack@eecs.umich.edu * @param cpu Pointer to the instruction's CPU. 3704636Sgblack@eecs.umich.edu */ 3714636Sgblack@eecs.umich.edu BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC, 3724636Sgblack@eecs.umich.edu Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 3734636Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu); 3743770Sgblack@eecs.umich.edu 3752292SN/A /** BaseDynInst constructor given a binary instruction. 3762292SN/A * @param inst The binary instruction. 3772292SN/A * @param PC The PC of the instruction. 3782292SN/A * @param pred_PC The predicted next PC. 3793794Sgblack@eecs.umich.edu * @param pred_NPC The predicted next NPC. 3802292SN/A * @param seq_num The sequence number of the instruction. 3812292SN/A * @param cpu Pointer to the instruction's CPU. 3822292SN/A */ 3834636Sgblack@eecs.umich.edu BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC, 3844636Sgblack@eecs.umich.edu Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 3853770Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu); 3861060SN/A 3872292SN/A /** BaseDynInst constructor given a StaticInst pointer. 3882292SN/A * @param _staticInst The StaticInst for this BaseDynInst. 3892292SN/A */ 3902107SN/A BaseDynInst(StaticInstPtr &_staticInst); 3911060SN/A 3921060SN/A /** BaseDynInst destructor. */ 3931060SN/A ~BaseDynInst(); 3941060SN/A 3951464SN/A private: 3961684SN/A /** Function to initialize variables in the constructors. */ 3971464SN/A void initVars(); 3981060SN/A 3991464SN/A public: 4001060SN/A /** Dumps out contents of this BaseDynInst. */ 4011060SN/A void dump(); 4021060SN/A 4031060SN/A /** Dumps out contents of this BaseDynInst into given string. */ 4041060SN/A void dump(std::string &outstring); 4051060SN/A 4063326Sktlim@umich.edu /** Read this CPU's ID. */ 4075712Shsul@eecs.umich.edu int cpuId() { return cpu->cpuId(); } 4083326Sktlim@umich.edu 4095714Shsul@eecs.umich.edu /** Read this context's system-wide ID **/ 4105714Shsul@eecs.umich.edu int contextId() { return thread->contextId(); } 4115714Shsul@eecs.umich.edu 4121060SN/A /** Returns the fault type. */ 4132132SN/A Fault getFault() { return fault; } 4141060SN/A 4151060SN/A /** Checks whether or not this instruction has had its branch target 4161060SN/A * calculated yet. For now it is not utilized and is hacked to be 4171060SN/A * always false. 4182292SN/A * @todo: Actually use this instruction. 4191060SN/A */ 4201060SN/A bool doneTargCalc() { return false; } 4211060SN/A 4221684SN/A /** Returns the next PC. This could be the speculative next PC if it is 4231684SN/A * called prior to the actual branch target being calculated. 4241684SN/A */ 4251060SN/A Addr readNextPC() { return nextPC; } 4261060SN/A 4272935Sksewell@umich.edu /** Returns the next NPC. This could be the speculative next NPC if it is 4282935Sksewell@umich.edu * called prior to the actual branch target being calculated. 4292935Sksewell@umich.edu */ 4303965Sgblack@eecs.umich.edu Addr readNextNPC() 4313965Sgblack@eecs.umich.edu { 4323965Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 4333965Sgblack@eecs.umich.edu return nextNPC; 4343965Sgblack@eecs.umich.edu#else 4353965Sgblack@eecs.umich.edu return nextPC + sizeof(TheISA::MachInst); 4363965Sgblack@eecs.umich.edu#endif 4373965Sgblack@eecs.umich.edu } 4382935Sksewell@umich.edu 4394636Sgblack@eecs.umich.edu Addr readNextMicroPC() 4404636Sgblack@eecs.umich.edu { 4414636Sgblack@eecs.umich.edu return nextMicroPC; 4424636Sgblack@eecs.umich.edu } 4434636Sgblack@eecs.umich.edu 4441060SN/A /** Set the predicted target of this current instruction. */ 4454636Sgblack@eecs.umich.edu void setPredTarg(Addr predicted_PC, Addr predicted_NPC, 4464636Sgblack@eecs.umich.edu Addr predicted_MicroPC) 4473794Sgblack@eecs.umich.edu { 4483794Sgblack@eecs.umich.edu predPC = predicted_PC; 4493794Sgblack@eecs.umich.edu predNPC = predicted_NPC; 4504636Sgblack@eecs.umich.edu predMicroPC = predicted_MicroPC; 4513794Sgblack@eecs.umich.edu } 4521060SN/A 4533794Sgblack@eecs.umich.edu /** Returns the predicted PC immediately after the branch. */ 4543794Sgblack@eecs.umich.edu Addr readPredPC() { return predPC; } 4553794Sgblack@eecs.umich.edu 4563794Sgblack@eecs.umich.edu /** Returns the predicted PC two instructions after the branch */ 4573794Sgblack@eecs.umich.edu Addr readPredNPC() { return predNPC; } 4581060SN/A 4594636Sgblack@eecs.umich.edu /** Returns the predicted micro PC after the branch */ 4604636Sgblack@eecs.umich.edu Addr readPredMicroPC() { return predMicroPC; } 4614636Sgblack@eecs.umich.edu 4621060SN/A /** Returns whether the instruction was predicted taken or not. */ 4633794Sgblack@eecs.umich.edu bool readPredTaken() 4643794Sgblack@eecs.umich.edu { 4653794Sgblack@eecs.umich.edu return predTaken; 4663794Sgblack@eecs.umich.edu } 4673794Sgblack@eecs.umich.edu 4683794Sgblack@eecs.umich.edu void setPredTaken(bool predicted_taken) 4693794Sgblack@eecs.umich.edu { 4703794Sgblack@eecs.umich.edu predTaken = predicted_taken; 4713794Sgblack@eecs.umich.edu } 4721060SN/A 4731060SN/A /** Returns whether the instruction mispredicted. */ 4742935Sksewell@umich.edu bool mispredicted() 4753794Sgblack@eecs.umich.edu { 4763965Sgblack@eecs.umich.edu return readPredPC() != readNextPC() || 4774636Sgblack@eecs.umich.edu readPredNPC() != readNextNPC() || 4784636Sgblack@eecs.umich.edu readPredMicroPC() != readNextMicroPC(); 4793794Sgblack@eecs.umich.edu } 4803794Sgblack@eecs.umich.edu 4811060SN/A // 4821060SN/A // Instruction types. Forward checks to StaticInst object. 4831060SN/A // 4845543Ssaidi@eecs.umich.edu bool isNop() const { return staticInst->isNop(); } 4855543Ssaidi@eecs.umich.edu bool isMemRef() const { return staticInst->isMemRef(); } 4865543Ssaidi@eecs.umich.edu bool isLoad() const { return staticInst->isLoad(); } 4875543Ssaidi@eecs.umich.edu bool isStore() const { return staticInst->isStore(); } 4882336SN/A bool isStoreConditional() const 4892336SN/A { return staticInst->isStoreConditional(); } 4901060SN/A bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 4911060SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 4921060SN/A bool isCopy() const { return staticInst->isCopy(); } 4935543Ssaidi@eecs.umich.edu bool isInteger() const { return staticInst->isInteger(); } 4945543Ssaidi@eecs.umich.edu bool isFloating() const { return staticInst->isFloating(); } 4955543Ssaidi@eecs.umich.edu bool isControl() const { return staticInst->isControl(); } 4965543Ssaidi@eecs.umich.edu bool isCall() const { return staticInst->isCall(); } 4975543Ssaidi@eecs.umich.edu bool isReturn() const { return staticInst->isReturn(); } 4985543Ssaidi@eecs.umich.edu bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 4991060SN/A bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 5005543Ssaidi@eecs.umich.edu bool isCondCtrl() const { return staticInst->isCondCtrl(); } 5015543Ssaidi@eecs.umich.edu bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 5022935Sksewell@umich.edu bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 5031060SN/A bool isThreadSync() const { return staticInst->isThreadSync(); } 5041060SN/A bool isSerializing() const { return staticInst->isSerializing(); } 5052292SN/A bool isSerializeBefore() const 5062731Sktlim@umich.edu { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 5072292SN/A bool isSerializeAfter() const 5082731Sktlim@umich.edu { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 5091060SN/A bool isMemBarrier() const { return staticInst->isMemBarrier(); } 5101060SN/A bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 5111060SN/A bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 5122292SN/A bool isQuiesce() const { return staticInst->isQuiesce(); } 5132336SN/A bool isIprAccess() const { return staticInst->isIprAccess(); } 5142308SN/A bool isUnverifiable() const { return staticInst->isUnverifiable(); } 5154828Sgblack@eecs.umich.edu bool isSyscall() const { return staticInst->isSyscall(); } 5164654Sgblack@eecs.umich.edu bool isMacroop() const { return staticInst->isMacroop(); } 5174654Sgblack@eecs.umich.edu bool isMicroop() const { return staticInst->isMicroop(); } 5184636Sgblack@eecs.umich.edu bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 5194654Sgblack@eecs.umich.edu bool isLastMicroop() const { return staticInst->isLastMicroop(); } 5204654Sgblack@eecs.umich.edu bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 5214636Sgblack@eecs.umich.edu bool isMicroBranch() const { return staticInst->isMicroBranch(); } 5222292SN/A 5232292SN/A /** Temporarily sets this instruction as a serialize before instruction. */ 5242731Sktlim@umich.edu void setSerializeBefore() { status.set(SerializeBefore); } 5252292SN/A 5262292SN/A /** Clears the serializeBefore part of this instruction. */ 5272731Sktlim@umich.edu void clearSerializeBefore() { status.reset(SerializeBefore); } 5282292SN/A 5292292SN/A /** Checks if this serializeBefore is only temporarily set. */ 5302731Sktlim@umich.edu bool isTempSerializeBefore() { return status[SerializeBefore]; } 5312292SN/A 5322292SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 5332731Sktlim@umich.edu void setSerializeAfter() { status.set(SerializeAfter); } 5342292SN/A 5352292SN/A /** Clears the serializeAfter part of this instruction.*/ 5362731Sktlim@umich.edu void clearSerializeAfter() { status.reset(SerializeAfter); } 5372292SN/A 5382292SN/A /** Checks if this serializeAfter is only temporarily set. */ 5392731Sktlim@umich.edu bool isTempSerializeAfter() { return status[SerializeAfter]; } 5402292SN/A 5412731Sktlim@umich.edu /** Sets the serialization part of this instruction as handled. */ 5422731Sktlim@umich.edu void setSerializeHandled() { status.set(SerializeHandled); } 5432292SN/A 5442292SN/A /** Checks if the serialization part of this instruction has been 5452292SN/A * handled. This does not apply to the temporary serializing 5462292SN/A * state; it only applies to this instruction's own permanent 5472292SN/A * serializing state. 5482292SN/A */ 5492731Sktlim@umich.edu bool isSerializeHandled() { return status[SerializeHandled]; } 5501060SN/A 5511464SN/A /** Returns the opclass of this instruction. */ 5521464SN/A OpClass opClass() const { return staticInst->opClass(); } 5531464SN/A 5541464SN/A /** Returns the branch target address. */ 5551464SN/A Addr branchTarget() const { return staticInst->branchTarget(PC); } 5561464SN/A 5572292SN/A /** Returns the number of source registers. */ 5585543Ssaidi@eecs.umich.edu int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 5591684SN/A 5602292SN/A /** Returns the number of destination registers. */ 5611060SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 5621060SN/A 5631060SN/A // the following are used to track physical register usage 5641060SN/A // for machines with separate int & FP reg files 5651060SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 5661060SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 5671060SN/A 5681060SN/A /** Returns the logical register index of the i'th destination register. */ 5692292SN/A RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 5701060SN/A 5711060SN/A /** Returns the logical register index of the i'th source register. */ 5722292SN/A RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 5731060SN/A 5741684SN/A /** Returns the result of an integer instruction. */ 5751464SN/A uint64_t readIntResult() { return instResult.integer; } 5761684SN/A 5771684SN/A /** Returns the result of a floating point instruction. */ 5782356SN/A float readFloatResult() { return (float)instResult.dbl; } 5791684SN/A 5801684SN/A /** Returns the result of a floating point (double) instruction. */ 5811464SN/A double readDoubleResult() { return instResult.dbl; } 5821060SN/A 5832702Sktlim@umich.edu /** Records an integer register being set to a value. */ 5843735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 5851060SN/A { 5863326Sktlim@umich.edu if (recordResult) 5873326Sktlim@umich.edu instResult.integer = val; 5881060SN/A } 5891060SN/A 5902702Sktlim@umich.edu /** Records an fp register being set to a value. */ 5913735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 5923735Sstever@eecs.umich.edu int width) 5932690Sktlim@umich.edu { 5943326Sktlim@umich.edu if (recordResult) { 5953326Sktlim@umich.edu if (width == 32) 5963326Sktlim@umich.edu instResult.dbl = (double)val; 5973326Sktlim@umich.edu else if (width == 64) 5983326Sktlim@umich.edu instResult.dbl = val; 5993326Sktlim@umich.edu else 6003326Sktlim@umich.edu panic("Unsupported width!"); 6013326Sktlim@umich.edu } 6022690Sktlim@umich.edu } 6032690Sktlim@umich.edu 6042702Sktlim@umich.edu /** Records an fp register being set to a value. */ 6053735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 6061060SN/A { 6073326Sktlim@umich.edu if (recordResult) 6083326Sktlim@umich.edu instResult.dbl = (double)val; 6092308SN/A } 6101060SN/A 6112702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 6123735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 6133735Sstever@eecs.umich.edu int width) 6142308SN/A { 6153326Sktlim@umich.edu if (recordResult) 6163326Sktlim@umich.edu instResult.integer = val; 6172308SN/A } 6181060SN/A 6192702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 6203735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 6212308SN/A { 6223326Sktlim@umich.edu if (recordResult) 6233326Sktlim@umich.edu instResult.integer = val; 6241060SN/A } 6251060SN/A 6262190SN/A /** Records that one of the source registers is ready. */ 6272292SN/A void markSrcRegReady(); 6282190SN/A 6292331SN/A /** Marks a specific register as ready. */ 6302292SN/A void markSrcRegReady(RegIndex src_idx); 6312190SN/A 6321684SN/A /** Returns if a source register is ready. */ 6331464SN/A bool isReadySrcRegIdx(int idx) const 6341464SN/A { 6351464SN/A return this->_readySrcRegIdx[idx]; 6361464SN/A } 6371464SN/A 6381684SN/A /** Sets this instruction as completed. */ 6392731Sktlim@umich.edu void setCompleted() { status.set(Completed); } 6401464SN/A 6412292SN/A /** Returns whether or not this instruction is completed. */ 6422731Sktlim@umich.edu bool isCompleted() const { return status[Completed]; } 6431464SN/A 6442731Sktlim@umich.edu /** Marks the result as ready. */ 6452731Sktlim@umich.edu void setResultReady() { status.set(ResultReady); } 6462308SN/A 6472731Sktlim@umich.edu /** Returns whether or not the result is ready. */ 6482731Sktlim@umich.edu bool isResultReady() const { return status[ResultReady]; } 6492308SN/A 6501060SN/A /** Sets this instruction as ready to issue. */ 6512731Sktlim@umich.edu void setCanIssue() { status.set(CanIssue); } 6521060SN/A 6531060SN/A /** Returns whether or not this instruction is ready to issue. */ 6542731Sktlim@umich.edu bool readyToIssue() const { return status[CanIssue]; } 6551060SN/A 6564032Sktlim@umich.edu /** Clears this instruction being able to issue. */ 6574032Sktlim@umich.edu void clearCanIssue() { status.reset(CanIssue); } 6584032Sktlim@umich.edu 6591060SN/A /** Sets this instruction as issued from the IQ. */ 6602731Sktlim@umich.edu void setIssued() { status.set(Issued); } 6611060SN/A 6621060SN/A /** Returns whether or not this instruction has issued. */ 6632731Sktlim@umich.edu bool isIssued() const { return status[Issued]; } 6641060SN/A 6654032Sktlim@umich.edu /** Clears this instruction as being issued. */ 6664032Sktlim@umich.edu void clearIssued() { status.reset(Issued); } 6674032Sktlim@umich.edu 6681060SN/A /** Sets this instruction as executed. */ 6692731Sktlim@umich.edu void setExecuted() { status.set(Executed); } 6701060SN/A 6711060SN/A /** Returns whether or not this instruction has executed. */ 6722731Sktlim@umich.edu bool isExecuted() const { return status[Executed]; } 6731060SN/A 6741060SN/A /** Sets this instruction as ready to commit. */ 6752731Sktlim@umich.edu void setCanCommit() { status.set(CanCommit); } 6761060SN/A 6771061SN/A /** Clears this instruction as being ready to commit. */ 6782731Sktlim@umich.edu void clearCanCommit() { status.reset(CanCommit); } 6791061SN/A 6801060SN/A /** Returns whether or not this instruction is ready to commit. */ 6812731Sktlim@umich.edu bool readyToCommit() const { return status[CanCommit]; } 6822731Sktlim@umich.edu 6832731Sktlim@umich.edu void setAtCommit() { status.set(AtCommit); } 6842731Sktlim@umich.edu 6852731Sktlim@umich.edu bool isAtCommit() { return status[AtCommit]; } 6861060SN/A 6872292SN/A /** Sets this instruction as committed. */ 6882731Sktlim@umich.edu void setCommitted() { status.set(Committed); } 6892292SN/A 6902292SN/A /** Returns whether or not this instruction is committed. */ 6912731Sktlim@umich.edu bool isCommitted() const { return status[Committed]; } 6922292SN/A 6931060SN/A /** Sets this instruction as squashed. */ 6942731Sktlim@umich.edu void setSquashed() { status.set(Squashed); } 6951060SN/A 6961060SN/A /** Returns whether or not this instruction is squashed. */ 6972731Sktlim@umich.edu bool isSquashed() const { return status[Squashed]; } 6981060SN/A 6992292SN/A //Instruction Queue Entry 7002292SN/A //----------------------- 7012292SN/A /** Sets this instruction as a entry the IQ. */ 7022731Sktlim@umich.edu void setInIQ() { status.set(IqEntry); } 7032292SN/A 7042292SN/A /** Sets this instruction as a entry the IQ. */ 7052731Sktlim@umich.edu void clearInIQ() { status.reset(IqEntry); } 7062731Sktlim@umich.edu 7072731Sktlim@umich.edu /** Returns whether or not this instruction has issued. */ 7082731Sktlim@umich.edu bool isInIQ() const { return status[IqEntry]; } 7092292SN/A 7101060SN/A /** Sets this instruction as squashed in the IQ. */ 7112731Sktlim@umich.edu void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 7121060SN/A 7131060SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 7142731Sktlim@umich.edu bool isSquashedInIQ() const { return status[SquashedInIQ]; } 7152292SN/A 7162292SN/A 7172292SN/A //Load / Store Queue Functions 7182292SN/A //----------------------- 7192292SN/A /** Sets this instruction as a entry the LSQ. */ 7202731Sktlim@umich.edu void setInLSQ() { status.set(LsqEntry); } 7212292SN/A 7222292SN/A /** Sets this instruction as a entry the LSQ. */ 7232731Sktlim@umich.edu void removeInLSQ() { status.reset(LsqEntry); } 7242731Sktlim@umich.edu 7252731Sktlim@umich.edu /** Returns whether or not this instruction is in the LSQ. */ 7262731Sktlim@umich.edu bool isInLSQ() const { return status[LsqEntry]; } 7272292SN/A 7282292SN/A /** Sets this instruction as squashed in the LSQ. */ 7292731Sktlim@umich.edu void setSquashedInLSQ() { status.set(SquashedInLSQ);} 7302292SN/A 7312292SN/A /** Returns whether or not this instruction is squashed in the LSQ. */ 7322731Sktlim@umich.edu bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 7332292SN/A 7342292SN/A 7352292SN/A //Reorder Buffer Functions 7362292SN/A //----------------------- 7372292SN/A /** Sets this instruction as a entry the ROB. */ 7382731Sktlim@umich.edu void setInROB() { status.set(RobEntry); } 7392292SN/A 7402292SN/A /** Sets this instruction as a entry the ROB. */ 7412731Sktlim@umich.edu void clearInROB() { status.reset(RobEntry); } 7422731Sktlim@umich.edu 7432731Sktlim@umich.edu /** Returns whether or not this instruction is in the ROB. */ 7442731Sktlim@umich.edu bool isInROB() const { return status[RobEntry]; } 7452292SN/A 7462292SN/A /** Sets this instruction as squashed in the ROB. */ 7472731Sktlim@umich.edu void setSquashedInROB() { status.set(SquashedInROB); } 7482292SN/A 7492292SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 7502731Sktlim@umich.edu bool isSquashedInROB() const { return status[SquashedInROB]; } 7512292SN/A 7521060SN/A /** Read the PC of this instruction. */ 7531464SN/A const Addr readPC() const { return PC; } 7541060SN/A 7554636Sgblack@eecs.umich.edu /**Read the micro PC of this instruction. */ 7564636Sgblack@eecs.umich.edu const Addr readMicroPC() const { return microPC; } 7574636Sgblack@eecs.umich.edu 7581060SN/A /** Set the next PC of this instruction (its actual target). */ 7594636Sgblack@eecs.umich.edu void setNextPC(Addr val) 7602308SN/A { 7612308SN/A nextPC = val; 7622308SN/A } 7632190SN/A 7642935Sksewell@umich.edu /** Set the next NPC of this instruction (the target in Mips or Sparc).*/ 7654636Sgblack@eecs.umich.edu void setNextNPC(Addr val) 7662935Sksewell@umich.edu { 7674632Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 7682935Sksewell@umich.edu nextNPC = val; 7694632Sgblack@eecs.umich.edu#endif 7702935Sksewell@umich.edu } 7712935Sksewell@umich.edu 7724636Sgblack@eecs.umich.edu void setNextMicroPC(Addr val) 7734636Sgblack@eecs.umich.edu { 7744636Sgblack@eecs.umich.edu nextMicroPC = val; 7754636Sgblack@eecs.umich.edu } 7764636Sgblack@eecs.umich.edu 7772702Sktlim@umich.edu /** Sets the ASID. */ 7782292SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 7792292SN/A 7802702Sktlim@umich.edu /** Sets the thread id. */ 7812702Sktlim@umich.edu void setTid(unsigned tid) { threadNumber = tid; } 7822292SN/A 7832731Sktlim@umich.edu /** Sets the pointer to the thread state. */ 7842702Sktlim@umich.edu void setThreadState(ImplState *state) { thread = state; } 7851060SN/A 7862731Sktlim@umich.edu /** Returns the thread context. */ 7872680Sktlim@umich.edu ThreadContext *tcBase() { return thread->getTC(); } 7881464SN/A 7891464SN/A private: 7901684SN/A /** Instruction effective address. 7911684SN/A * @todo: Consider if this is necessary or not. 7921684SN/A */ 7931464SN/A Addr instEffAddr; 7942292SN/A 7951684SN/A /** Whether or not the effective address calculation is completed. 7961684SN/A * @todo: Consider if this is necessary or not. 7971684SN/A */ 7981464SN/A bool eaCalcDone; 7991464SN/A 8004032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 8014032Sktlim@umich.edu bool isUncacheable; 8024032Sktlim@umich.edu 8034032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8044032Sktlim@umich.edu bool reqMade; 8054032Sktlim@umich.edu 8061464SN/A public: 8071684SN/A /** Sets the effective address. */ 8081464SN/A void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 8091684SN/A 8101684SN/A /** Returns the effective address. */ 8111464SN/A const Addr &getEA() const { return instEffAddr; } 8121684SN/A 8131684SN/A /** Returns whether or not the eff. addr. calculation has been completed. */ 8141464SN/A bool doneEACalc() { return eaCalcDone; } 8151684SN/A 8161684SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 8171464SN/A bool eaSrcsReady(); 8181681SN/A 8192292SN/A /** Whether or not the memory operation is done. */ 8202292SN/A bool memOpDone; 8212292SN/A 8224032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 8234032Sktlim@umich.edu bool uncacheable() { return isUncacheable; } 8244032Sktlim@umich.edu 8254032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8264032Sktlim@umich.edu bool hasRequest() { return reqMade; } 8274032Sktlim@umich.edu 8281681SN/A public: 8291684SN/A /** Load queue index. */ 8301681SN/A int16_t lqIdx; 8311684SN/A 8321684SN/A /** Store queue index. */ 8331681SN/A int16_t sqIdx; 8342292SN/A 8352292SN/A /** Iterator pointing to this BaseDynInst in the list of all insts. */ 8362292SN/A ListIt instListIt; 8372292SN/A 8382292SN/A /** Returns iterator to this instruction in the list of all insts. */ 8392292SN/A ListIt &getInstListIt() { return instListIt; } 8402292SN/A 8412292SN/A /** Sets iterator for this instruction in the list of all insts. */ 8422292SN/A void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 8433326Sktlim@umich.edu 8443326Sktlim@umich.edu public: 8453326Sktlim@umich.edu /** Returns the number of consecutive store conditional failures. */ 8463326Sktlim@umich.edu unsigned readStCondFailures() 8473326Sktlim@umich.edu { return thread->storeCondFailures; } 8483326Sktlim@umich.edu 8493326Sktlim@umich.edu /** Sets the number of consecutive store conditional failures. */ 8503326Sktlim@umich.edu void setStCondFailures(unsigned sc_failures) 8513326Sktlim@umich.edu { thread->storeCondFailures = sc_failures; } 8521060SN/A}; 8531060SN/A 8541060SN/Atemplate<class Impl> 8551060SN/Atemplate<class T> 8562132SN/Ainline Fault 8571060SN/ABaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 8581060SN/A{ 8594032Sktlim@umich.edu reqMade = true; 8604032Sktlim@umich.edu Request *req = new Request(); 8614032Sktlim@umich.edu req->setVirt(asid, addr, sizeof(T), flags, this->PC); 8625714Shsul@eecs.umich.edu req->setThreadContext(thread->contextId(), threadNumber); 8632292SN/A 8646023Snate@binkert.org fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Read); 8651060SN/A 8664032Sktlim@umich.edu if (req->isUncacheable()) 8674032Sktlim@umich.edu isUncacheable = true; 8684032Sktlim@umich.edu 8692678Sktlim@umich.edu if (fault == NoFault) { 8702678Sktlim@umich.edu effAddr = req->getVaddr(); 8714032Sktlim@umich.edu effAddrValid = true; 8722678Sktlim@umich.edu physEffAddr = req->getPaddr(); 8732678Sktlim@umich.edu memReqFlags = req->getFlags(); 8741060SN/A 8752690Sktlim@umich.edu#if 0 8762292SN/A if (cpu->system->memctrl->badaddr(physEffAddr)) { 8772292SN/A fault = TheISA::genMachineCheckFault(); 8782292SN/A data = (T)-1; 8792292SN/A this->setExecuted(); 8802292SN/A } else { 8812292SN/A fault = cpu->read(req, data, lqIdx); 8822292SN/A } 8832292SN/A#else 8841681SN/A fault = cpu->read(req, data, lqIdx); 8852632Sstever@eecs.umich.edu#endif 8861684SN/A } else { 8871060SN/A // Return a fixed value to keep simulation deterministic even 8881060SN/A // along misspeculated paths. 8891060SN/A data = (T)-1; 8902292SN/A 8912292SN/A // Commit will have to clean up whatever happened. Set this 8922292SN/A // instruction as executed. 8932292SN/A this->setExecuted(); 8944032Sktlim@umich.edu delete req; 8951060SN/A } 8961060SN/A 8971060SN/A if (traceData) { 8981060SN/A traceData->setAddr(addr); 8991060SN/A traceData->setData(data); 9001060SN/A } 9011060SN/A 9021060SN/A return fault; 9031060SN/A} 9041060SN/A 9051060SN/Atemplate<class Impl> 9061060SN/Atemplate<class T> 9072132SN/Ainline Fault 9081060SN/ABaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 9091060SN/A{ 9101060SN/A if (traceData) { 9111060SN/A traceData->setAddr(addr); 9121060SN/A traceData->setData(data); 9131060SN/A } 9141060SN/A 9154032Sktlim@umich.edu reqMade = true; 9164032Sktlim@umich.edu Request *req = new Request(); 9172669Sktlim@umich.edu req->setVirt(asid, addr, sizeof(T), flags, this->PC); 9185714Shsul@eecs.umich.edu req->setThreadContext(thread->contextId(), threadNumber); 9191060SN/A 9206023Snate@binkert.org fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write); 9211060SN/A 9224032Sktlim@umich.edu if (req->isUncacheable()) 9234032Sktlim@umich.edu isUncacheable = true; 9244032Sktlim@umich.edu 9252090SN/A if (fault == NoFault) { 9262678Sktlim@umich.edu effAddr = req->getVaddr(); 9274032Sktlim@umich.edu effAddrValid = true; 9282678Sktlim@umich.edu physEffAddr = req->getPaddr(); 9292678Sktlim@umich.edu memReqFlags = req->getFlags(); 9304350Sgblack@eecs.umich.edu 9314350Sgblack@eecs.umich.edu if (req->isCondSwap()) { 9324350Sgblack@eecs.umich.edu assert(res); 9334350Sgblack@eecs.umich.edu req->setExtraData(*res); 9344350Sgblack@eecs.umich.edu } 9352690Sktlim@umich.edu#if 0 9362292SN/A if (cpu->system->memctrl->badaddr(physEffAddr)) { 9372292SN/A fault = TheISA::genMachineCheckFault(); 9382292SN/A } else { 9392292SN/A fault = cpu->write(req, data, sqIdx); 9402292SN/A } 9412292SN/A#else 9421681SN/A fault = cpu->write(req, data, sqIdx); 9432632Sstever@eecs.umich.edu#endif 9444032Sktlim@umich.edu } else { 9454032Sktlim@umich.edu delete req; 9461060SN/A } 9471060SN/A 9481060SN/A return fault; 9491060SN/A} 9501060SN/A 9511464SN/A#endif // __CPU_BASE_DYN_INST_HH__ 952